A dual system merging unit selection circuit

Abstract

The utility model discloses a kind of merging unit selection circuit of double system, belong to intelligent control circuit technical field, including control unit, power supply, logic judging circuit, multipath selection circuit, SV receiving circuit, SV sending circuit and isolation circuit;The control unit includes control unit 1 and control unit 2 that mutually independent and can carry out data interaction.The utility model is by deploying two sets of completely independent and parallel working control unit and two sets of independent SV signal receiving channel, constitutes the core redundancy from signal input to processing, when any control unit or any SV receiving channel fails, another set of healthy system can seamlessly take over all work, continue to output correct SV signal, which fundamentally solves the major risk of the loss of entire system function caused by a component failure in traditional single system design.

Description

Technical Field

[0001] This utility model relates to the field of intelligent control circuit technology, and in particular to a dual-system merging unit selection circuit. Background Technology

[0002] In power systems, the stability of bus voltage is crucial for the normal operation of the entire power grid. To enhance system reliability, a dual-bus structure is typically employed, where two independent bus systems operate in parallel. This ensures that if one bus fails, the other can immediately take over the power supply, thereby guaranteeing the continuity and stability of power supply. To achieve this goal, an intelligent selection and switching device must be designed. This device should be able to automatically select a healthy and stable bus voltage for power supply based on the operating status of the two bus systems.

[0003] In the circuit design of traditional intelligent bus voltage selection and switching devices, it is often necessary to rely on a single-system hardware circuit to receive the sampled value (SV) signals from two sets of bus merging units, such as... Figure 1 As shown. However, this design has a significant drawback: if the hardware circuitry of a single system malfunctions, such as a fault or damage, the SV signals of the two bus merging units cannot be accurately received and processed. In this situation, the intelligent selection and switching device will be unable to obtain accurate bus voltage information, leading to an inability to make correct switching decisions, thereby increasing the risk of a failure in the entire power system.

[0004] Therefore, in the current circuit design of intelligent bus voltage selection and switching devices, it is necessary to focus on improving the redundancy and robustness of the system to ensure that when one bus system fails, the other can seamlessly take over the power supply task, thereby ensuring the stable operation of the power system. Based on this, a dual-system merging unit selection circuit is proposed. Utility Model Content

[0005] The purpose of this invention is to solve the problems existing in the prior art by proposing a dual-system merging unit selection circuit.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A dual-system merging unit selection circuit includes a control unit, a power supply, a logic judgment circuit, a multiplexing circuit, an SV receiving circuit, an SV transmitting circuit, and an isolation circuit;

[0008] The control unit includes a control unit 1 and a control unit 2 that are independent of each other and capable of data interaction;

[0009] The power supply includes power supply 1, power supply 2 and power supply 3. Power supply 1 supplies power to control unit 1, power supply 2 supplies power to control unit 2, power supply 1 and power supply 2 together supply power to power supply 3, and power supply 3 supplies power to logic judgment circuit, multiplexing circuit, SV receiving circuit and SV transmitting circuit.

[0010] The SV receiving circuit includes two independent SV receiving circuits 1 and 2, which are used to receive the A-set merging unit signal SVA and the B-set merging unit signal SVB, respectively.

[0011] The control unit 1 and control unit 2 are respectively connected to SV receiving circuit 1 and SV receiving circuit 2 to receive SVA signal and SVB signal;

[0012] The control unit 1 is used to generate the SV1 signal and select the flag bit sel_1 according to the SVA and SVB signals, and the control unit 2 is used to generate the SV2 signal and select the flag bit sel_2 according to the SVA and SVB signals.

[0013] The input terminal of the logic judgment circuit is connected to control unit 1 and control unit 2 to receive sel_1 and sel_2, and its output terminal is connected to a multiplexer circuit to output an enable signal EN and an output selection signal OE.

[0014] The input of the multiplexing circuit receives SV1 and SV2 signals, and its output is connected to the SV transmitting circuit, which is used to select whether to output SV1, SV2, or no signal based on the EN and OE signals.

[0015] As a preferred embodiment, power supply 1, power supply 2 and power supply 3 are set independently of each other, so that if any power supply is abnormal, it will not affect the normal operation of the other two power supplies.

[0016] As a preferred embodiment, an isolation circuit is provided on the data interaction channel between the control unit 1 and the control unit 2.

[0017] As a preferred embodiment, isolation circuits are provided on the connection channels between the SV receiving circuit 1, the SV receiving circuit 2 and the control unit 1, the control unit 2.

[0018] As a preferred embodiment, the isolation circuit is used to achieve physical isolation.

[0019] As a preferred embodiment, the logic judgment circuit is configured as follows:

[0020] When sel_1 is 1 and sel_2 is 0, the output EN is 1 and OE is 0.

[0021] When sel_1 is 1 and sel_2 is 1, the output EN is 1 and OE is 0.

[0022] When sel_1 is 0 and sel_2 is 1, the output EN is 1 and OE is 1.

[0023] When sel_1 is 0 and sel_2 is 0, the output EN is 0 and OE is 0.

[0024] As a preferred embodiment, the multiplexing circuit is configured as follows:

[0025] When EN is 1 and OE is 0, the SV1 signal is selected and output to the SV transmitting circuit;

[0026] When EN is 1 and OE is 1, the SV2 signal is selected and output to the SV transmitting circuit;

[0027] When EN is 0 and OE is 0, no SV signal is output.

[0028] As a preferred embodiment, the logic judgment circuit is composed of hardware gate circuits.

[0029] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0030] 1. This solution establishes core redundancy from signal input to processing by deploying two completely independent and parallel control units and two independent SV signal receiving channels. When any control unit or any SV receiving channel fails, the other healthy system can seamlessly take over all work and continue to output the correct SV signal. This fundamentally solves the major risk of the entire system losing its function due to the failure of a single component in traditional single-system design.

[0031] 2. This solution adopts a dual power supply system. If one power supply fails, the other power supply will continue to supply power to the circuit, ensuring the normal operation of the signal selection and output logic circuits and further improving the reliability of the system. Attached Figure Description

[0032] Figure 1 A circuit block diagram of a single-system bus voltage intelligent selection and switching device;

[0033] Figure 2 The circuit diagram is for a dual-system merging unit selection circuit proposed in this utility model. Detailed Implementation

[0034] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0035] Example

[0036] Reference Figure 1 - Figure 2 A dual-system merging unit selection circuit, comprising a control unit, a power supply, a logic judgment circuit, a multiplexing circuit, an SV receiving circuit, an SV transmitting circuit, and an isolation circuit.

[0037] The control unit includes two completely independent control units, 1 and 2, which serve as hot backups for each other.

[0038] The power supply adopts a three-level independent design, including power supply 1, power supply 2 and power supply 3. Among them, power supply 1 is dedicated to powering control unit 1, power supply 2 is dedicated to powering control unit 2, power supply 1 and power supply 2 together power supply 3, and power supply 3 powers the logic judgment circuit, multiplexing circuit, SV receiving circuit and SV transmitting circuit. If any power supply fails, it will not affect the normal operation of the other two power supplies, thus realizing the redundancy of the power supply system.

[0039] The SV receiving circuit has two independent channels, namely SV receiving circuit 1 and SV receiving circuit 2, which are used to receive the A-set merging unit signal SVA and the B-set merging unit signal SVB, respectively.

[0040] It is worth noting that both control unit 1 and control unit 2 are connected to SV receiving circuit 1 and SV receiving circuit 2 simultaneously, so that both control units can independently acquire complete SVA and SVB signals.

[0041] After processing the two acquired signals, control unit 1 generates SV1 signal and a selection flag bit sel_1 representing its own working status and signal quality. Similarly, control unit 2 generates SV2 signal and selection flag bit sel_2.

[0042] The logic judgment circuit is composed of hardware gate circuits. It receives sel_1 and sel_2 signals from two sets of control units, makes judgments according to preset logic rules, and outputs two control signals: enable signal EN and selection signal OE, and multi-channel selection circuit.

[0043] The multiplexing circuit receives two signals, SV1 and SV2, and determines whether to output SV1, SV2, or no signal based on the combination of EN and OE signals. The selected signal is then sent to the SV transmitting circuit.

[0044] The SV transmitting circuit is responsible for forwarding the final SV signal to subsequent protection or measurement and control devices.

[0045] In addition, isolation circuits are provided between control unit 1 and control unit 2, as well as between the SV receiving circuit and the control unit, to achieve physical electrical isolation and prevent interference and fault propagation.

[0046] Two parallel signal processing links:

[0047] The first link is centered around control unit 1. Control unit 1 simultaneously receives the SVA signal from SV receiving circuit 1 and the SVB signal from SV receiving circuit 2. It has built-in processing logic to check and judge the quality of these two signals, ultimately synthesizing them into a high-quality SV1 signal, and simultaneously generating a selection flag bit sel_1 representing its own state and decision result. The SV1 signal is sent to the "0" channel of the multiplexing circuit, and sel_1 is sent to the logic judgment circuit.

[0048] The second link, centered on control unit 2, operates identically to the first link, independently generating the SV2 signal and the selection flag sel_2. The SV2 signal is sent to channel "1" of the multiplexer circuit.

[0049] Logic circuits act as the "arbitrators" of a system.

[0050] When sel_1 is 1 and sel_2 is 0, the logic judgment circuit outputs EN as 1 and OE as 0.

[0051] When sel_1 is 1 and sel_2 is 1, the logic judgment circuit outputs EN as 1 and OE as 0.

[0052] When sel_1 is 0 and sel_2 is 1, the logic judgment circuit outputs EN as 1 and OE as 1.

[0053] When sel_1 is 0 and sel_2 is 0, the logic judgment circuit outputs EN as 0 and OE as 0.

[0054] When the EN output is 1 and the OE output is 0, the multiplexer selects the SV1 signal and sends it to the SV transmitting circuit.

[0055] When the EN output is 1 and the OE output is 1, the multiplexer selects the SV2 signal and sends it to the SV transmitting circuit.

[0056] When the EN output is 0 and the OE output is 0, the multiplexer circuit does not output the SV signal to the SV transmitting circuit.

[0057] The SV transmitting circuit forwards the SV signal received from the multiplexer circuit.

[0058] The power supply system operates as follows: Power supply 1 and power supply 2 isolate and convert the external input power to power their respective control units. Simultaneously, they both serve as the input to power supply 3; power supply 3 then isolates and converts the power supply again to power the common components of the system (logic judgment, multiplexing, SV transceiver circuits).

[0059] This design ensures that even if either power supply 1 or power supply 2 fails, power supply 3 can still be powered by the other power supply; and even if power supply 3 fails, the two control units can still operate independently and display abnormal alarm status, and the system will not malfunction.

[0060] The isolation circuitry is strategically placed in three key locations: on the communication path between control units 1 and 2, after the output of SV receiver circuit 1, and after the output of SV receiver circuit 2. This ensures electrical isolation between different power domains and signal sources.

[0061] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A dual-system merging unit selection circuit, characterized in that: Includes control unit, power supply, logic judgment circuit, multiplexing circuit, SV receiving circuit, SV transmitting circuit and isolation circuit; The control unit includes a control unit 1 and a control unit 2 that are independent of each other and capable of data interaction; The power supply includes power supply 1, power supply 2 and power supply 3. Power supply 1 supplies power to control unit 1, power supply 2 supplies power to control unit 2, power supply 1 and power supply 2 together supply power to power supply 3, and power supply 3 supplies power to logic judgment circuit, multiplexing circuit, SV receiving circuit and SV transmitting circuit. The SV receiving circuit includes two independent SV receiving circuits 1 and 2, which are used to receive the A-set merging unit signal SVA and the B-set merging unit signal SVB, respectively. The control unit 1 and control unit 2 are respectively connected to SV receiving circuit 1 and SV receiving circuit 2 to receive SVA signal and SVB signal; The control unit 1 is used to generate the SV1 signal and select the flag bit sel_1 according to the SVA and SVB signals, and the control unit 2 is used to generate the SV2 signal and select the flag bit sel_2 according to the SVA and SVB signals. The input terminal of the logic judgment circuit is connected to control unit 1 and control unit 2 to receive sel_1 and sel_2, and its output terminal is connected to a multiplexer circuit to output an enable signal EN and an output selection signal OE. The input of the multiplexing circuit receives SV1 and SV2 signals, and its output is connected to the SV transmitting circuit, which is used to select whether to output SV1, SV2, or no signal based on the EN and OE signals.

2. The dual-system merging unit selection circuit according to claim 1, characterized in that, The power supply 1, power supply 2 and power supply 3 are set up independently, and if any power supply is abnormal, it will not affect the normal operation of the other two power supplies.

3. The dual-system merging unit selection circuit according to claim 1, characterized in that, An isolation circuit is provided on the data interaction channel between control unit 1 and control unit 2.

4. The dual-system merging unit selection circuit according to claim 1, characterized in that, Isolation circuits are provided on the connection channels between the SV receiving circuit 1 and SV receiving circuit 2 and the control unit 1 and control unit 2.

5. The dual-system merging unit selection circuit according to claim 1, characterized in that, The isolation circuit is used to achieve physical isolation.

6. The dual-system merging unit selection circuit according to claim 1, characterized in that, The logic judgment circuit is configured as follows: When sel_1 is 1 and sel_2 is 0, the output EN is 1 and OE is 0. When sel_1 is 1 and sel_2 is 1, the output EN is 1 and OE is 0. When sel_1 is 0 and sel_2 is 1, the output EN is 1 and OE is 1. When sel_1 is 0 and sel_2 is 0, the output EN is 0 and OE is 0.

7. The dual-system merging unit selection circuit according to claim 1, characterized in that, The multiplexing circuit is configured as follows: When EN is 1 and OE is 0, the SV1 signal is selected and output to the SV transmitting circuit; When EN is 1 and OE is 1, the SV2 signal is selected and output to the SV transmitting circuit; When EN is 0 and OE is 0, no SV signal is output.

8. The dual-system merging unit selection circuit according to claim 1, characterized in that, The logic judgment circuit is composed of hardware gate circuits.

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