Adaptive blanking control circuit, flyback converter circuit and electronic device

Abstract

The application discloses an adaptive blanking control circuit, a flyback converter circuit and electronic equipment. The adaptive blanking control circuit is applied to the flyback converter circuit, and the adaptive blanking control circuit comprises a blanking time adaptive circuit and a primary side current sampling circuit. The blanking time adaptive circuit is used for generating a blanking time signal as an enable signal of the primary side current sampling circuit based on a sampling bus voltage of the flyback converter circuit and a pulse width modulation signal of the flyback converter circuit. The enable width of the enable signal is positively correlated with the size of the sampling bus voltage. When the adaptive blanking control circuit is not enabled in response to the blanking time signal, the primary side current sampling circuit stops working. When the adaptive blanking control circuit is enabled in response to the blanking time signal, the primary side current sampling circuit works. In the above manner, the adaptive blanking control circuit can adaptively adjust the blanking time according to the input bus voltage, thereby reducing the possibility of false triggering and damage of power devices.

Description

Technical Field

[0001] This application relates to the fields of integrated circuits and switching power supply technology, specifically to an adaptive blanking control circuit, a flyback converter circuit, and electronic equipment. Background Technology

[0002] In flyback converter circuits, secondary-side feedback regulation increases system cost and complicates the architecture, while primary-side feedback regulation has a wider range of applications. When the control chip of a primary-side feedback flyback converter obtains system current information, it must sample the current of the electrically isolated output side at the system input side. However, when the primary-side main switch is turned on, its own junction capacitance and the parasitic capacitance of the transformer will cause a large spike current at the moment the main switch is turned on. This spike current will exceed the peak current of the primary side during normal operation. If not handled, it will falsely trigger the overcurrent protection of the flyback converter circuit. To avoid the influence of the spike current at the moment the main switch is turned on, the existing solution is to set a fixed blanking time in the primary-side current sampling circuit to shield the spike current at the moment of turn-on, and then sample the primary-side current after the blanking time has passed. However, different bus voltages will cause different rising slopes of the primary excitation current. Therefore, a fixed blanking time setting is difficult to meet the requirements of different bus voltage inputs. When the blanking time is set too long, the current may surge too high after a primary overcurrent or short circuit, causing damage to the transformer and power devices. In addition, it will also filter out normal current waveforms during normal operation, affecting the system current sampling control and overall efficiency. When the blanking time is set too short, it may not be able to shield current spikes, thus falsely triggering the overcurrent protection of the flyback converter circuit. Utility Model Content

[0003] This application proposes an adaptive blanking control circuit, a flyback converter circuit, and an electronic device to solve the above-mentioned problems.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide an adaptive blanking control circuit, which is applied to a flyback converter circuit. The adaptive blanking control circuit includes a blanking time adaptive circuit and a primary-side current sampling circuit. The blanking time adaptive circuit generates a blanking time signal as an enable signal for the primary-side current sampling circuit based on the sampling bus voltage of the flyback converter circuit and the pulse width modulation signal of the flyback converter circuit. The enable width of the enable signal is positively correlated with the magnitude of the sampling bus voltage. When the blanking time signal is not enabled, the primary-side current sampling circuit stops working; when the blanking time signal is enabled, the primary-side current sampling circuit works.

[0005] The blanking time adaptive circuit includes a voltage-to-current conversion circuit and a blanking time signal generation circuit. The voltage-to-current conversion circuit receives the sampled bus voltage and generates a corresponding current signal. The magnitude of the current signal is positively correlated with the magnitude of the sampled bus voltage. The blanking time signal generation circuit is coupled to the voltage-to-current conversion circuit and is used to receive the pulse width modulation signal and the current signal. It generates a blanking time signal based on the pulse width modulation signal and the current signal. The enable width of the blanking time signal is positively correlated with the magnitude of the current signal.

[0006] The voltage-to-current conversion circuit includes a preset power supply and a variable current source. The preset power supply is connected to one end of the variable current source, and the other end of the variable current source is coupled to the blanking time signal generation circuit. The magnitude of the current signal generated by the variable current source is positively correlated with the magnitude of the sampling bus voltage.

[0007] The blanking time signal generation circuit includes an inverter, a capacitor, a first switch, and a voltage-time conversion circuit. The input terminal of the inverter receives the pulse width modulation signal, and the output terminal of the inverter is connected to the control terminal of the first switch and the voltage-time conversion circuit. The first terminal of the capacitor and the first path terminal of the first switch are both coupled to the other end of the variable current source to receive the current signal. The second terminal of the capacitor and the second path terminal of the first switch are grounded. The connection between the first terminal of the capacitor and the other end of the variable current source serves as the output terminal and is connected to the voltage-time conversion circuit. In response to a high-level pulse width modulation signal, the first switch is turned off, and the current signal charges the capacitor. In response to a low-level pulse width modulation signal, the first switch is turned on, and the capacitor discharges through the first switch.

[0008] The voltage-to-time conversion circuit includes a comparator, a logic gate, and a latch. The first input of the comparator is connected to the first terminal of the capacitor and the other end of the variable current source. The second input of the comparator receives a reference voltage. The first input of the logic gate is connected to the output of the comparator, and the second input of the logic gate receives a pulse width modulation signal. The output of the logic gate is connected to the set terminal of the latch. The reset terminal of the latch is connected to the output of the inverter. The output of the latch outputs a blanking time signal. In response to a high-level pulse width modulation signal, the first switch is turned off, and the current signal charges the capacitor. When the capacitor voltage is less than the reference voltage, the comparator outputs a low-level signal, the AND gate outputs a low-level signal, and the latch outputs a blanking time signal that is disabled. When the capacitor voltage is greater than the reference voltage, the comparator outputs a high-level signal, the AND gate outputs a high-level signal, and the latch outputs a blanking time signal that is enabled. In response to the pulse width modulation signal being low, the first switch is turned on, the capacitor discharges through the first switch, the AND gate outputs a low-level signal, and the latch outputs a blanking time signal that is disabled.

[0009] The primary-side current sampling circuit includes a second switch. The control terminal of the second switch receives a blanking time signal. When the blanking time signal is disabled, the second switch is turned off; when the blanking time signal is enabled, the second switch is turned on.

[0010] The primary-side current sampling circuit includes a current sampling module and a conversion module. The first path terminal of the second switch is connected to the current sampling point of the flyback converter circuit, and the second path terminal of the second switch is connected to the current sampling module. The current sampling module and the conversion module are connected. The current sampling module is used to acquire the sampled current signal of the flyback converter circuit, and the conversion module is used to acquire the converted voltage signal based on the sampled current signal. When the blanking time signal is disabled, the second switch is turned off, and the current sampling module and the conversion module stop working. When the blanking time signal is enabled, the second switch is turned on, and the current sampling module and the conversion module work.

[0011] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a flyback converter circuit, which includes the adaptive blanking control circuit of any one of the above-mentioned features.

[0012] The flyback converter circuit also includes a pulse width modulation module, a drive circuit, a transformer, a third switch, a resistor, a diode, and a load. The bus voltage is connected to one end of the primary side of the transformer, and the other end of the primary side of the transformer is connected to the first path terminal of the third switch. One end of the secondary side of the transformer is connected to the positive terminal of the diode, and the negative terminal of the diode is connected to the load. The load and the other end of the secondary side of the transformer are grounded. The second path terminal of the third switch is connected to the first end of the resistor, and the second end of the resistor is grounded. The current sampling point of the primary side current sampling circuit is coupled to the connection between the second path terminal of the third switch and the first end of the resistor. The primary side current sampling circuit is also used to generate a converted voltage signal based on the sampled current signal. The output terminal of the primary side current sampling circuit is connected to the pulse width modulation module. The pulse width modulation module is used to generate a pulse width modulation signal based on the voltage output signal of the secondary side of the transformer and the converted voltage signal. The drive circuit is connected to the pulse width modulation module and is used to generate a voltage control signal based on the pulse width modulation signal and send it to the control terminal of the third switch.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide an electronic device that includes the flyback converter circuit of any one of the above-mentioned methods.

[0014] The beneficial effects of this application are as follows: Unlike existing technologies, the adaptive blanking control circuit of this application includes a blanking time adaptive circuit and a primary-side current sampling circuit. The blanking time adaptive circuit generates a blanking time signal based on the sampled bus voltage of the flyback converter circuit and the pulse width modulation signal of the flyback converter circuit, which serves as the enable signal for the primary-side current sampling circuit. The enable width of the enable signal is positively correlated with the magnitude of the sampled bus voltage. When the blanking time signal is disabled, the primary-side current sampling circuit stops operating; when the blanking time signal is enabled, the primary-side current sampling circuit operates. Through this method, the adaptive blanking control circuit of this application can adaptively adjust the blanking time according to the input bus voltage, thereby reducing the possibility of false triggering and damage to power devices. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of a traditional primary-side flyback converter circuit; Figure 2 This is a schematic diagram of the primary-side peak error caused by different bus voltages; Figure 3This is a schematic diagram of the measured waveform of a primary-side flyback converter circuit under short circuit conditions. Figure 4 This is a schematic diagram of the structure of the first embodiment of the adaptive blanking control circuit provided in this application; Figure 5 This is a schematic diagram of the structure of the first embodiment of the blanking time adaptive circuit provided in this application; Figure 6 This is a schematic diagram of the circuit structure of the second embodiment of the blanking time adaptive circuit provided in this application; Figure 7 This is a schematic diagram of the control waveform of the blanking time adaptive circuit provided in this application; Figure 8 This is a schematic diagram of the circuit structure of an embodiment of the flyback converter circuit provided in this application; Figure 9 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0017] In flyback converter circuits, secondary-side feedback regulation increases system cost and complicates the architecture, while primary-side feedback regulation has a wider range of applications. When the control chip of a primary-side feedback flyback converter obtains system current information, it must sample the current of the electrically isolated output side at the system input side. However, when the primary-side main switch is turned on, its own junction capacitance and the parasitic capacitance of the transformer will cause a large spike current at the moment the main switch is turned on. This spike current will exceed the peak current of the primary side during normal operation. If not handled, it will falsely trigger the overcurrent protection of the flyback converter circuit. To avoid the influence of the spike current at the moment the main switch is turned on, the existing solution is to set a fixed blanking time in the primary-side current sampling circuit to shield the spike current at the moment of turn-on, and then sample the primary-side current after the blanking time has passed. However, different bus voltages will cause different rising slopes of the primary excitation current. Therefore, a fixed blanking time setting is difficult to meet the requirements of different bus voltage inputs. When the blanking time is set too long, the current may surge too high after a primary overcurrent or short circuit, causing damage to the transformer and power devices. In addition, it will also filter out normal current waveforms during normal operation, affecting the system current sampling control and overall efficiency. When the blanking time is set too short, it may not be able to shield current spikes, thus falsely triggering the overcurrent protection of the flyback converter circuit.

[0018] For example, please refer to Figure 1 , Figure 1 This is a schematic diagram of a traditional primary-side flyback converter circuit. (Example:) Figure 1 As shown, the primary-side main switch of a traditional primary-side flyback converter circuit uses a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS). When the MOS is off, its junction capacitance and the transformer's parasitic capacitance store charge. When the primary-side main switch is turned on, the junction capacitance of the MOS and the parasitic capacitance of the transformer discharge instantaneously. If the primary-side flyback converter circuit operates in continuous conduction mode, the reverse recovery current of the secondary-side diode will also be transferred to the primary side. Therefore, a large spike current will be generated at the moment the main switch is turned on, which may exceed the peak current of the primary side during normal operation. If no measures are taken, the primary-side flyback converter circuit may falsely trigger overcurrent protection if it samples this current. To avoid the influence of the spike current at the moment the main switch is turned on, the existing technology uses a circuit that generates a fixed blanking time for the primary-side current sampling circuit to shield the spike current at the moment of turn-on, and then samples the primary-side current after this period.

[0019] However, after the primary-side main switch is turned on, the rising slope of the primary-side excitation current is different under different input bus voltages. The slope is Vin / Lm, where Vin is the bus voltage and Lm is the inductance of the transformer primary winding. Clearly, the higher the bus voltage, the faster the rising slope of the excitation current. If the blanking time is fixed, the final magnitude of the excitation current will be different within this blanking time, causing peak current sampling errors. When the bus voltage is high, the rising slope of the excitation current is very fast. Due to the fixed blanking time (not required for high bus voltage inputs), primary-side current sampling is blocked during this period. After an overcurrent / short circuit, the excitation current may surge very high, exceeding the overcurrent protection point of the primary-side flyback converter circuit, causing damage to the transformer and power devices.

[0020] Please see Figure 2 , Figure 2 This is a schematic diagram illustrating the primary-side peak error caused by different bus voltages. See below. Figure 2As shown, within a fixed blanking time tLEB, the peak current corresponding to higher and lower bus voltages is inconsistent. When the bus voltage is higher, the corresponding primary-side peak current is larger after the fixed blanking time tLEB ends. Therefore, setting a fixed blanking time tLEB is difficult to satisfy the requirements of high / low bus voltage input. If the blanking time is set too long, the current may surge excessively after a primary-side overcurrent or short circuit, causing damage to the transformer and power devices. Furthermore, it will filter out normal current waveforms during normal operation, affecting system current sampling control and overall efficiency. If the blanking time is set too short, it may fail to shield current spikes, thus falsely triggering the overcurrent protection of the flyback converter circuit. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of the measured waveform of a primary-side flyback converter circuit under short circuit conditions. (Example:) Figure 3 As shown, Figure 3 The first channel CH1 in the diagram represents the output voltage Vo. Figure 3 The second channel CH2 in the diagram represents the drain voltage Vds of the main switch. Figure 3 The third channel CH3 in the diagram represents the primary-side magnetizing current Ipri. When the primary-side flyback converter circuit is short-circuited, due to the high slope of the magnetizing current, the primary-side magnetizing current Ipri spikes very high within the fixed blanking time. The controller of the primary-side flyback converter circuit only reacts and shuts off the primary-side main switch after the fixed blanking time ends. However, within the fixed blanking time, an excessively large spike in the primary-side magnetizing current Ipri can cause stress spikes in the primary-side main switch, potentially leading to primary-side main switch failure or transformer current saturation, such as... Figure 3 The spike in the middle box shown.

[0021] To address the aforementioned issues, this application provides an adaptive blanking control circuit. Please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of the structure of the first embodiment of the adaptive blanking control circuit provided in this application. Figure 4 As shown, the adaptive blanking control circuit 100 in this embodiment includes a blanking time adaptive circuit 10 and a primary-side current sampling circuit 20.

[0022] In this embodiment, the blanking time adaptive circuit 10 is used to generate a blanking time signal as an enable signal for the primary current sampling circuit 20 based on the sampling bus voltage of the flyback converter circuit and the pulse width modulation signal of the flyback converter circuit. The enable width of the enable signal is positively correlated with the magnitude of the sampling bus voltage. When the blanking time signal is not enabled, the primary current sampling circuit 20 stops working, and when the blanking time signal is enabled, the primary current sampling circuit 20 starts working.

[0023] In this embodiment, the blanking time adaptive circuit 10 takes the sampled input bus voltage Vin and the pulse width modulation signal as inputs. After processing by the internal circuit of the blanking time adaptive circuit 10, it can output a blanking time signal. This signal can be used to control the primary-side current sampling circuit 20. When the blanking time signal is enabled, the primary-side current sampling circuit 20 operates to acquire the primary-side sampled current signal. Furthermore, the enable signal is the blanking time signal, and the enable width of the blanking time signal is the operating time for the primary-side current sampling circuit 20 to sample the current. The enable width of the enable signal is positively correlated with the magnitude of the sampled bus voltage. This can be understood as follows: the larger the sampled bus voltage, the longer the operating time of the primary-side current sampling circuit 20 to sample the current, and the shorter the blanking time; that is, when the sampled bus voltage is high, the blanking time is reduced, and when the sampled bus voltage is low, the blanking time is increased. The circuit structure and principle of the blanking time adaptive circuit 10 are described below and will not be described in detail here.

[0024] Unlike existing technologies, the adaptive blanking control circuit 100 of this application includes a blanking time adaptive circuit 10 and a primary-side current sampling circuit 20. The blanking time adaptive circuit 10 generates a blanking time signal based on the sampled bus voltage of the flyback converter circuit and the pulse width modulation signal of the flyback converter circuit, which serves as the enable signal for the primary-side current sampling circuit 20. The enable width of the enable signal is positively correlated with the magnitude of the sampled bus voltage. When the blanking time signal is disabled, the primary-side current sampling circuit 20 stops operating; when the blanking time signal is enabled, the primary-side current sampling circuit 20 operates. Through this method, the adaptive blanking control circuit 100 of this application can adaptively adjust the blanking time according to the input bus voltage, thereby reducing the possibility of false triggering and damage to power devices.

[0025] Optionally, please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of the first embodiment of the blanking time adaptive circuit provided in this application. Figure 5 As shown, the blanking time adaptive circuit 10 of this embodiment includes a voltage-to-current conversion circuit 11 and a blanking time signal generation circuit 12. The voltage-to-current conversion circuit 11 receives the sampled bus voltage and generates a corresponding current signal. The magnitude of the current signal is positively correlated with the magnitude of the sampled bus voltage. The blanking time signal generation circuit 12 is coupled to the voltage-to-current conversion circuit 11 and is used to receive the pulse width modulation signal and the current signal, and generate a blanking time signal based on the pulse width modulation signal and the current signal. The enable width of the blanking time signal is positively correlated with the magnitude of the current signal.

[0026] In this embodiment, the voltage-to-current conversion circuit 11 can convert the sampling bus voltage into a corresponding current signal. The magnitude of the current signal is positively correlated with the magnitude of the sampling bus voltage; that is, the larger the sampling bus voltage, the larger the current signal; and the smaller the sampling bus voltage, the smaller the current signal. After the voltage-to-current conversion circuit 11 converts the sampling bus voltage into a corresponding current signal, the blanking time signal generation circuit 12 can generate a blanking time signal based on the pulse width modulation signal and the current signal. The enable width of the blanking time signal is positively correlated with the magnitude of the current signal; that is, the larger the current signal, the larger the enable width of the blanking time signal, meaning the longer the primary-side current sampling circuit 20 operates for current sampling, and the shorter the blanking time; conversely, the smaller the current signal, the smaller the enable width of the blanking time signal, meaning the shorter the primary-side current sampling circuit 20 operates for current sampling, and the longer the blanking time.

[0027] Optionally, please refer to Figure 6 , Figure 6 This is a schematic diagram of the circuit structure of the second embodiment of the adaptive blanking time circuit provided in this application. Figure 6 As shown, the voltage-to-current conversion circuit 11 of this embodiment includes a preset power supply Vcc and a variable current source I. The preset power supply Vcc is connected to one end of the variable current source I, and the other end of the variable current source I is coupled to the blanking time signal generation circuit 12. The magnitude of the current signal generated by the variable current source I is positively correlated with the magnitude of the sampling bus voltage.

[0028] like Figure 6 As shown, the preset power supply Vcc in this embodiment can be an internal voltage source of the system. The voltage of the preset power supply Vcc can be set based on actual conditions and is not limited here. Furthermore, the variable current source I in this embodiment can be configured to adjust the magnitude of the current signal by sampling the bus voltage. The adjustment logic is as follows: as the sampling bus voltage increases, the adjusted current signal increases, and the two change in the same direction. That is, the magnitude of the current signal generated by the variable current source I is positively correlated with the magnitude of the sampling bus voltage. The above relationship can be implemented in this embodiment using semiconductor integration technology.

[0029] Optionally, such as Figure 6As shown, the blanking time signal generation circuit 12 in this embodiment includes an inverter D1, a capacitor C1, a first switch K1, and a voltage-time conversion circuit 121. The input terminal of the inverter D1 receives the pulse width modulation signal, and the output terminal of the inverter D1 is connected to the control terminal of the first switch K1 and the voltage-time conversion circuit 121. The first terminal of the capacitor C1 and the first pass terminal of the first switch K1 are both coupled to the other end of the variable current source I to receive the current signal. The second terminal of the capacitor C1 and the second pass terminal of the first switch K1 are grounded. The connection point between the first terminal of the capacitor C1 and the other end of the variable current source I serves as the output terminal and is connected to the voltage-time conversion circuit 121. In response to the pulse width modulation signal being a high-level signal, the first switch K1 is turned off, and the current signal charges the capacitor C1. In response to the pulse width modulation signal being a low-level signal, the first switch K1 is turned on, and the capacitor C1 discharges through the first switch K1.

[0030] In this embodiment, when the pulse width modulation signal is a high-level signal, it becomes a low-level signal after passing through the inverter D1. At this time, the first switch K1 is open, and the variable current source I charges the capacitor C1, forming an integrating circuit. When the pulse width modulation signal is a low-level signal, it becomes a high-level signal after passing through the inverter D1. At this time, the first switch K1 is turned on, and the capacitor C1 discharges, resetting for the next switching cycle.

[0031] Optionally, such as Figure 6As shown, the voltage-time conversion circuit 121 of this embodiment includes a comparator COMP1, a logic device AND gate D2, and a latch Q1. The first input terminal of the comparator COMP1 is connected to the first terminal of the capacitor C1 and the other end of the variable current source I. The second input terminal of the comparator COMP1 receives a reference voltage. The first input terminal of the logic device AND gate D2 is connected to the output terminal of the comparator COMP1. The second input terminal of the logic device AND gate D2 receives a pulse width modulation signal. The output terminal of the logic device AND gate D2 is connected to the set terminal S of the latch Q1. The reset terminal R of the latch Q1 is connected to the output terminal of the inverter D1. The output terminal Q of the latch Q1 outputs a blanking time signal. In response to a high-level pulse width modulation (PWM) signal, the first switch K1 is turned off, and the current signal charges capacitor C1. When the voltage of capacitor C1 is less than the reference voltage, the output of comparator COMP1 is low, the output of AND gate D2 is low, and the blanking time signal output by latch Q1 is disabled. When the voltage of capacitor C1 is greater than the reference voltage, the output of comparator COMP1 is high, the output of AND gate D2 is high, and the blanking time signal output by latch Q1 is enabled. In response to a low-level PWM signal, the first switch K1 is turned on, capacitor C1 discharges through the first switch K1, the output of AND gate D2 is low, and the blanking time signal output by latch Q1 is disabled.

[0032] In this embodiment, latch Q1 can be configured as an RS latch. See also... Figure 7 , Figure 7 This is a schematic diagram of the control waveform of the blanking time adaptive circuit provided in this application. For example... Figure 7As shown, when the pulse width modulation signal is a high-level signal, it becomes a low-level signal after passing through inverter D1. At this time, the first switch K1 is open, and the variable current source I charges capacitor C1. Before the voltage of capacitor C1 reaches the reference voltage, the output of comparator COMP1 is a low-level signal. After passing through the logic device AND gate D2, it becomes a low-level signal. If the RS latch is a NAND gate structure, the control requires the RS latch to not work. Since the output of the RS latch with a NAND gate structure is indeterminate when all inputs are low-level signals, in this embodiment, when all inputs of the RS latch are low-level signals, it needs to be controlled not to work, that is, the output blanking time signal is not enabled. In other embodiments, an RS latch with a NOR gate structure can also be used. When an RS latch with a NOR gate structure is used, both input terminals need to be high-level signals simultaneously when the output is in an indeterminate state. Therefore, if an RS latch with a NOR gate structure is used, when both the set terminal S and the reset terminal R of the RS latch receive low-level signals, the output terminal Q of the RS latch can also output a blanking time signal, and the blanking time signal is not enabled. That is, an RS latch with a NOR gate structure does not need to control the working state of latch Q1.

[0033] In addition, in other embodiments, this embodiment may also use other types of latches, as long as the blanking time signal at the output is not enabled when all inputs are low-level signals.

[0034] like Figure 7 As shown, when the pulse width modulation signal is a high-level signal, it becomes a low-level signal after passing through inverter D1. At this time, the first switch K1 is open. When the voltage of capacitor C1 is charged to the reference voltage, the output of comparator COMP1 outputs a high-level signal. After passing through the AND gate D2, the high-level signal is input to the set terminal S of latch Q1. The reset terminal R of latch Q1 is still a low-level signal, so the output terminal Q of latch Q1 outputs a high-level signal, that is, the blanking time signal is enabled, and the primary-side current sampling circuit 20 works. When the pulse width modulation signal is a low-level signal, it becomes a high-level signal after passing through inverter D1. At this time, the first switch K1 is turned on, and the output of the AND gate D2 outputs a low-level signal to the set terminal S of latch Q1. The reset terminal R of latch Q1 is a high-level signal. At this time, the output terminal Q of latch Q1 outputs a low-level signal, that is, the blanking time signal is not enabled, and the primary-side current sampling circuit 20 does not work. Simultaneously, the first switch K1 also closes, and the voltage on capacitor C1 is discharged through the first switch K1, resetting for the next switching cycle. Figure 7 T in LEBThis is represented as the blanking time, which is the period during which the blanking time signal is not enabled. Through the above method, the blanking time adaptive circuit 10 of this embodiment can quickly control the blanking time signal, making the output blanking time signal real-time; moreover, the blanking time adaptive circuit 10 of this embodiment has high reliability, strong anti-interference ability, and fast response.

[0035] In other embodiments, the adaptive blanking control circuit 100 of this application is not limited to flyback converter circuits, but can also be applied to other circuits that require current sampling, without limitation.

[0036] Optionally, please refer to Figure 8 , Figure 8 This is a schematic diagram of the circuit structure of an embodiment of the flyback converter circuit provided in this application. Figure 8 As shown, the primary-side current sampling circuit 20 of this embodiment includes a second switch K2. The control terminal of the second switch K2 receives a blanking time signal. When the blanking time signal is disabled, the second switch K2 is turned off; when the blanking time signal is enabled, the second switch K2 is turned on.

[0037] Optionally, such as Figure 8 As shown, the primary-side current sampling circuit 20 of this embodiment further includes a current sampling module 22 and a conversion module 21. The first path terminal of the second switch K2 is connected to the current sampling point P of the flyback converter circuit 200, and the second path terminal of the second switch K2 is connected to the current sampling module 22. The current sampling module 22 and the conversion module 21 are connected. The current sampling module 22 is used to acquire the sampled current signal Ics of the flyback converter circuit 200, and the conversion module 21 is used to acquire the converted voltage signal Vcs based on the sampled current signal Ics. When the blanking time signal is not enabled, the second switch K2 is turned off, and the current sampling module 22 and the conversion module 21 stop working; when the blanking time signal is enabled, the second switch K2 is turned on, and the current sampling module 22 and the conversion module 21 work.

[0038] Optionally, this application further proposes a flyback converter circuit. For example... Figure 8 As shown, the flyback converter circuit 200 of this embodiment includes the adaptive blanking control circuit 100 of any of the above embodiments.

[0039] Optionally, such as Figure 8As shown, the flyback converter circuit 200 in this embodiment also includes a pulse width modulation module 110, a drive circuit 120, a transformer T1, a third switch M1, a resistor Rcs, a diode D, and a load Cout. The bus voltage Vin is connected to one end of the primary winding of the transformer T1, and the other end of the primary winding of the transformer T1 is connected to the first pass terminal of the third switch M1. One end of the secondary winding of the transformer T1 is connected to the positive terminal of the diode D, and the negative terminal of the diode D is connected to the load Cout. The load Cout and the other end of the secondary winding of the transformer T1 are grounded. The second pass terminal of the third switch M1 is connected to the first terminal of the resistor Rcs, and the second terminal of the resistor Rcs is grounded. The current sampling point P of the primary current sampling circuit 20 is coupled to the connection between the second path terminal of the third switch M1 and the first terminal of the resistor Rcs. The primary current sampling circuit 20 is also used to generate a converted voltage signal Vcs based on the sampled current signal Ics. The output terminal of the primary current sampling circuit 20 is connected to the pulse width modulation module 110. The pulse width modulation module 110 is used to generate a pulse width modulation signal based on the voltage output signal Vo of the secondary side of the transformer T1 and the converted voltage signal Vcs. The drive circuit 120 is connected to the pulse width modulation module 110 and is used to generate a voltage control signal Gate based on the pulse width modulation signal and send it to the control terminal of the third switch M1.

[0040] In this embodiment, when the third switch M1 is off, the secondary diode D is on, forming a loop of transformer T1, secondary diode D, load Cout, and ground. When the third switch M1 is on, the secondary diode D is off, forming a loop of bus voltage, third switch M1, resistor Rcs, and ground. When the blanking time signal is enabled, the primary current sampling circuit 20 samples the current signal Ics and converts it into a converted voltage signal Vcs, which serves as one input signal of the pulse width modulation module 110. The other input signal is the voltage output signal Vo of the secondary side of transformer T1. The pulse width modulation module 110 modulates the two signals to generate a pulse width modulation signal and sends it to the drive circuit 120. The drive circuit 120 outputs a voltage control signal Gate to drive the third switch M1 to turn on and off.

[0041] Optionally, this application further proposes an electronic device, please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Figure 9 As shown, the electronic device 300 of this embodiment includes the flyback converter circuit 200 of any of the above embodiments.

[0042] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An adaptive blanking control circuit, characterized in that, The adaptive blanking control circuit, applied to flyback converter circuits, includes a blanking time adaptive circuit and a primary-side current sampling circuit. The blanking time adaptive circuit generates a blanking time signal as an enable signal for the primary-side current sampling circuit based on the sampling bus voltage and the pulse width modulation signal of the flyback converter circuit. The enable width of the enable signal is positively correlated with the magnitude of the sampling bus voltage. When the blanking time signal is disabled, the primary-side current sampling circuit stops working; when the blanking time signal is enabled, the primary-side current sampling circuit starts working.

2. The adaptive blanking control circuit according to claim 1, characterized in that, The blanking time adaptive circuit includes: A voltage-to-current conversion circuit receives the sampling bus voltage and generates a corresponding current signal, wherein the magnitude of the current signal is positively correlated with the magnitude of the sampling bus voltage. A blanking time signal generation circuit, coupled to the voltage-to-current conversion circuit, is used to receive the pulse width modulation signal and the current signal, and generate the blanking time signal based on the pulse width modulation signal and the current signal, wherein the enable width of the blanking time signal is positively correlated with the magnitude of the current signal.

3. The adaptive blanking control circuit according to claim 2, characterized in that, The voltage-to-current conversion circuit includes a preset power supply and a variable current source. The preset power supply is connected to one end of the variable current source, and the other end of the variable current source is coupled to the blanking time signal generation circuit. The magnitude of the current signal generated by the variable current source is positively correlated with the magnitude of the sampling bus voltage.

4. The adaptive blanking control circuit according to claim 3, characterized in that, The blanking time signal generation circuit includes an inverter, a capacitor, a first switch, and a voltage-time conversion circuit. The input terminal of the inverter receives the pulse width modulation signal, and the output terminal of the inverter is connected to the control terminal of the first switch and the voltage-time conversion circuit. The first terminal of the capacitor and the first path terminal of the first switch are both coupled to the other end of the variable current source to receive the current signal. The second terminal of the capacitor and the second path terminal of the first switch are grounded. The connection between the first terminal of the capacitor and the other end of the variable current source serves as the output terminal and is connected to the voltage-time conversion circuit. In response to the pulse width modulation signal being a high-level signal, the first switch is turned off, and the current signal charges the capacitor; in response to the pulse width modulation signal being a low-level signal, the first switch is turned on, and the capacitor discharges through the first switch.

5. The adaptive blanking control circuit according to claim 4, characterized in that, The voltage-to-time conversion circuit includes a comparator, logic devices, AND gates, and latches. The first input terminal of the comparator is connected to the first terminal of the capacitor and the other end of the variable current source. The second input terminal of the comparator receives a reference voltage. The first input terminal of the AND gate is connected to the output terminal of the comparator. The second input terminal of the AND gate receives the pulse width modulation signal. The output terminal of the AND gate is connected to the set terminal of the latch. The reset terminal of the latch is connected to the output terminal of the inverter. The output terminal of the latch outputs the blanking time signal. In response to the pulse width modulation signal being a high-level signal, the first switch is turned off, and the current signal charges the capacitor. When the voltage value of the capacitor is less than the reference voltage, the output of the comparator outputs a low-level signal, the output of the AND gate of the logic device outputs a low-level signal, and the blanking time signal output by the output of the latch is disabled. When the voltage value of the capacitor is greater than the reference voltage, the output of the comparator outputs a high-level signal, the output of the AND gate of the logic device outputs a high-level signal, and the blanking time signal output by the output of the latch is enabled. In response to the pulse width modulation signal being a low-level signal, the first switch is turned on, the capacitor discharges through the first switch, the output of the AND gate of the logic device outputs a low-level signal, and the blanking time signal output by the output of the latch is disabled.

6. The adaptive blanking control circuit according to claim 1, characterized in that, The primary-side current sampling circuit includes a second switch. The control terminal of the second switch receives the blanking time signal. When the blanking time signal is disabled, the second switch is turned off; when the blanking time signal is enabled, the second switch is turned on.

7. The adaptive blanking control circuit according to claim 6, characterized in that, The primary-side current sampling circuit further includes a current sampling module and a conversion module. The first path terminal of the second switch is connected to the current sampling point of the flyback converter circuit, and the second path terminal of the second switch is connected to the current sampling module. The current sampling module and the conversion module are connected. The current sampling module is used to acquire the sampled current signal of the flyback converter circuit, and the conversion module is used to acquire the converted voltage signal based on the sampled current signal. When the blanking time signal is disabled, the second switch is turned off, and the current sampling module and the conversion module stop working. When the blanking time signal is enabled, the second switch is turned on, and the current sampling module and the conversion module work.

8. A flyback converter circuit, characterized in that, Includes the adaptive blanking control circuit as described in any one of claims 1-7.

9. The flyback converter circuit according to claim 8, characterized in that, The flyback converter circuit also includes a pulse width modulation module, a driver circuit, a transformer, a third switch, resistors, diodes, and a load. The bus voltage is connected to one end of the primary side of the transformer, the other end of the primary side of the transformer is connected to the first path terminal of the third switch, one end of the secondary side of the transformer is connected to the positive terminal of the diode, the negative terminal of the diode is connected to the load, the load and the other end of the secondary side of the transformer are grounded, the second path terminal of the third switch is connected to the first end of the resistor, the second end of the resistor is grounded, the current sampling point of the primary side current sampling circuit is coupled to the connection between the second path terminal of the third switch and the first end of the resistor, the primary side current sampling circuit is also used to generate a converted voltage signal based on the sampled current signal, the output terminal of the primary side current sampling circuit is connected to the pulse width modulation module, the pulse width modulation module is used to generate the pulse width modulation signal based on the voltage output signal of the secondary side of the transformer and the converted voltage signal, the drive circuit is connected to the pulse width modulation module, and is used to generate a voltage control signal based on the pulse width modulation signal and send it to the control terminal of the third switch.

10. An electronic device, characterized in that, Includes the flyback converter circuit as described in any one of claims 8-9.

Images