A push-pull inverter circuit with reduced peak voltage

Abstract

The utility model relates to the technical field of inverter, concretely relates to a push-pull inverter circuit of reducing peak voltage, include: push-pull transformer (T), push-pull transformer (T) include multiple primary winding and secondary winding (N3), multiple power switch tube, controllably connect between primary winding and ground terminal, bridge rectifier (2), the input of bridge rectifier (2) connects secondary winding (N3), and the output of bridge rectifier (2) connects a power voltage (E), wherein, every power switch tube is independently connected with a primary winding respectively, forms multiple independent power switch tube-winding series branch circuit, the utility model discloses through with independent primary winding series connection of every power switch tube, forms separate branch circuit, eliminates junction capacitance superposition, effectively suppresses the off reverse peak voltage, avoids single tube overvoltage breakdown, significantly improves the reliability of high power and start, and need not newly add cost.

Description

Technical Field

[0001] This utility model relates to the field of inverter technology, specifically to a push-pull inverter circuit for reducing peak voltage. Background Technology

[0002] In the field of green energy conversion, inverters, as key equipment, play a vital role in applications such as mobile home energy storage, and their reliability and cost directly affect the overall competitiveness of the product. Currently, to reduce production costs, trench wafer technology is commonly used for MOSFETs to reduce on-resistance, but this leads to a significant decrease in the device's avalanche resistance. However, inverters need to withstand currents several times their nominal value during startup or when driving large loads. To improve current withstand capability, the industry typically uses multiple transistors connected in parallel to increase power capacity.

[0003] Although the multi-transistor parallel structure is simple, direct parallel connection leads to a significant increase in junction capacitance, causing problems such as inconsistent conduction times, excessively high peak voltages, and uneven current distribution under high power output conditions. Especially during heavy loads or startup, the reverse peak voltage across multiple parallel MOSFETs further increases, easily causing overvoltage or overcurrent damage to a single transistor. As the number of parallel transistors increases, these problems become more severe, seriously limiting the reliability and lifespan of the inverter. Utility Model Content

[0004] To address the above technical problems, this utility model provides a technical solution for a push-pull inverter circuit that reduces peak voltage.

[0005] The technical problem solved by this utility model can be achieved by the following technical solution:

[0006] A push-pull inverter circuit for reducing peak voltage includes:

[0007] A push-pull transformer, comprising multiple primary windings and secondary windings;

[0008] Multiple power switching transistors are controllably connected between the primary winding and the ground terminal;

[0009] A bridge rectifier, wherein the input terminal of the bridge rectifier is connected to the secondary winding, and the output terminal of the bridge rectifier is connected to a power supply voltage;

[0010] Each of the power switches is independently connected to a primary winding, forming multiple independent power switch-winding series branches.

[0011] Preferably, the push-pull transformer has four primary windings, including a first primary winding, a second primary winding, a third primary winding, and a fourth primary winding.

[0012] The number of power switching transistors is four, including:

[0013] The first power switch is controllably connected between the ground terminal and the second primary winding;

[0014] The second power switch is controllably connected between the ground terminal and the first primary winding;

[0015] The third power switch is controllably connected between the ground terminal and the third primary winding;

[0016] The fourth power switch is controllably connected between the ground terminal and the fourth primary winding.

[0017] Preferably, the drain of the first power switch is connected to the first end of the second primary winding;

[0018] The drain of the second power switch is connected to the first end of the first primary winding;

[0019] The drain of the third power switch is connected to the first end of the third primary winding;

[0020] The drain of the fourth power switch is connected to the first end of the fourth primary winding;

[0021] The sources of the first power switch, the second power switch, the third power switch, and the fourth power switch are all connected to the ground terminal;

[0022] The second ends of the first primary winding, the second primary winding, the third primary winding, and the fourth primary winding are all connected to a DC input power supply.

[0023] Preferably, the second ends of the first primary winding and the second primary winding are connected in parallel to a first common contact, and the second ends of the third primary winding and the fourth primary winding are connected in parallel to a second common contact. The first common contact and the second common contact are both connected to the DC input power supply.

[0024] Preferably, the gates of the first power switch and the second power switch are connected in parallel to the first drive signal terminal;

[0025] The gates of the third power switch and the fourth power switch are connected in parallel to the second drive signal terminal.

[0026] Preferably, the first AC input terminal of the bridge rectifier is connected to the first terminal of the secondary winding, and the second AC input terminal of the bridge rectifier is connected to the second terminal of the secondary winding.

[0027] Preferably, the positive output terminal of the bridge rectifier is connected to the positive terminal of the power supply voltage, and the negative output terminal of the bridge rectifier is connected to the negative terminal of the power supply voltage.

[0028] Preferably, the first power switch, the second power switch, the third power switch, and the fourth power switch are metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors.

[0029] Beneficial effects: This utility model eliminates the junction capacitance superposition effect caused by direct parallel connection of multiple power switches by connecting each power switch in series with a primary winding to form a completely independent power branch. It significantly reduces the reverse peak voltage generated by transformer leakage inductance and junction capacitance resonance at the turn-off time of the switch, thereby avoiding the breakdown and damage of a single switch due to excessive voltage stress. At the same time, it improves the dynamic current sharing characteristics under multi-switch parallel connection, greatly improves the reliability and service life of the inverter during high power output and startup, and does not require additional cost. Attached Figure Description

[0030] Figure 1 This is the circuit diagram of the push-pull inverter of this utility model;

[0031] Figure 2 This is a time-series variation diagram of the square wave signal of this utility model;

[0032] Figure 3 This is a diagram illustrating the peak starting voltage of this utility model. Detailed Implementation

[0033] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0035] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0036] Reference Figure 1 This utility model provides a push-pull inverter circuit for reducing peak voltage, comprising:

[0037] A push-pull transformer T, wherein the push-pull transformer T includes multiple primary windings and secondary windings N3;

[0038] Multiple power switching transistors are controllably connected between the primary winding and the ground terminal;

[0039] Bridge rectifier 2, the input terminal of which is connected to the secondary winding N3, and the output terminal of which is connected to a power supply voltage E;

[0040] Each of the power switches is independently connected to a primary winding, forming multiple independent power switch-winding series branches.

[0041] Specifically, in this embodiment of the invention, in order to address the problems of junction capacitance superposition, excessively high reverse peak voltage and deterioration of dynamic current sharing caused by multiple power transistors in parallel, the junction capacitance multiplication effect caused by direct parallel connection of multiple power transistors is avoided by connecting each power switch transistor in series with a primary winding to form a completely independent power branch. This achieves effective suppression of reverse peak voltage at turn-off time and natural balance of current stress of each power transistor, thereby significantly improving the reliability of the inverter during high power output and startup.

[0042] Specifically, in each independent branch, the inherent junction capacitances of the power switches—including the gate-drain capacitance (GDC), gate-source capacitance (GSC), and drain-source capacitance (DSC)—are no longer connected in parallel with the junction capacitances of other power switches, but exist independently in their respective circuits. During turn-off, the leakage inductance of the push-pull transformer T only needs to charge and discharge the DSC of a single switch, rather than the huge equivalent capacitance of multiple switches connected in parallel. This significantly reduces the induced reverse peak voltage. Simultaneously, since each branch is independent, there is no dynamic current sharing problem as with direct parallel connections, and the current stress on each power switch is naturally balanced, thus significantly improving the reliability of the inverter during high-power output and startup.

[0043] In a preferred embodiment of the present invention, the push-pull transformer T has four primary windings, including a first primary winding N1, a second primary winding N2, a third primary winding N4, and a fourth primary winding N5.

[0044] The number of power switching transistors is four, including:

[0045] The first power switch M1 is controllably connected between the ground terminal and the second primary winding N2;

[0046] The second power switch M2 is controllably connected between the ground terminal and the first primary winding N1;

[0047] The third power switch M3 is controllably connected between the ground terminal and the third primary winding N4;

[0048] The fourth power switch M4 is controllably connected between the ground terminal and the fourth primary winding N5.

[0049] Specifically, in the embodiments of this utility model, referring to Figure 1 The drain D1 of the first power switch M1 is connected to the first terminal 6 of the second primary winding N2;

[0050] The drain of the second power switch M2 is connected to the first terminal 1 of the first primary winding N1;

[0051] The drain of the third power switch M3 is connected to the first terminal 3 of the third primary winding N4;

[0052] The drain of the fourth power switch M4 is connected to the first terminal 7 of the fourth primary winding N5;

[0053] The sources of the first power switch M1, the second power switch M2, the third power switch M3, and the fourth power switch M4 are all connected to the ground terminal;

[0054] The second ends of the first primary winding N1, the second primary winding N2, the third primary winding N4, and the fourth primary winding N5 are all connected to the DC input power supply VDD.

[0055] More specifically, by connecting four power switching transistors (M1-M4) in series with four independent primary windings (N1, N2, N4, N5) to form four independent circuits, and then connecting them in parallel between the DC input power supply VDD and the ground terminal, a unique "series-then-parallel" topology is formed. This structure effectively overcomes the problems of poor switching synchronization, excessively high turn-off voltage spikes, and uneven dynamic current distribution caused by the superposition of junction capacitance in the traditional multi-transistor direct parallel connection method.

[0056] The working principle of this design is that each winding of the push-pull transformer T provides consistent impedance characteristics to its corresponding branch, and achieves automatic current balancing through mutual inductance between the windings. Simultaneously, the junction capacitance of each power transistor is confined to an independent branch, significantly reducing the equivalent parasitic inductance during turn-off and effectively suppressing voltage spikes. This design achieves dynamic current sharing, reduced switching stress, and improved system reliability in multi-transistor parallel applications at low cost.

[0057] In a preferred embodiment of the present invention, the gate of the first power switch M1 and the gate of the second power switch M2 are connected in parallel to the first drive signal terminal PWM1.

[0058] The gate of the third power switch M3 and the gate of the fourth power switch M4 are connected in parallel to the second drive signal terminal PWM2.

[0059] Specifically, in this embodiment of the invention, the driving connection method greatly simplifies the driving circuit structure while ensuring the synchronous operation of each independent branch. By connecting the gates of the power switching transistors (M1 and M2, M3 and M4) operating at the same time to the same driving signal terminal, only two isolated driving signals are needed to control the four power switching transistors, significantly reducing the number of driving chips, isolation devices, and peripheral components. This achieves the technical effect of effectively reducing system cost and complexity while ensuring control synchronization.

[0060] In a preferred embodiment of this utility model, the second ends of the first primary winding N1 and the second primary winding N2 are connected in parallel to the first common contact A, and the second ends of the third primary winding N4 and the fourth primary winding N5 are connected in parallel to the second common contact B. The first common contact A and the second common contact B are both connected to the DC input power supply VDD.

[0061] Specifically, in this embodiment of the invention, the second ends of a group of windings (such as N1 and N2) that operate simultaneously under the same drive signal are first converged to a first common contact A, and the second ends of another group of windings (such as N4 and N5) that operate simultaneously under another drive signal are converged to a second common contact B. Finally, common contacts A and B are connected together to the DC input power supply VDD. This connection method effectively reduces the problem of parasitic parameter differences caused by asymmetrical winding routing.

[0062] Specifically, it connects the windings operating in the same group to a local common contact (such as point A), shortening the loop path of the high-frequency switching current. This helps ensure that the parasitic inductance (mainly trace inductance) faced by the current flowing through the N1-M2 branch and the N2-M1 branch is more consistent. Because the parasitic inductance values ​​are similar, the difference in induced electromotive force generated during high-speed switching is reduced, thereby improving the voltage conditions and switching dynamic consistency of the two branches. This helps reduce current distribution deviations and switching oscillations that may be caused by layout asymmetry, achieving better dynamic current sharing.

[0063] It is evident that this design is a beneficial supplement to the core current sharing structure of "one tube and one winding". By optimizing the wiring, it further ensures the parameter symmetry of each branch in the same group, making the conduction and turn-off characteristics of the switching tube more consistent. This helps to further optimize the current sharing effect, reduce switching oscillation, and ultimately achieve the technical effect of lower system electromagnetic interference (EMI), higher working efficiency and reliability.

[0064] In a preferred embodiment of the present invention, the drive signals output by the first drive signal terminal PWM1 and the second drive signal terminal PWM2 are a set of complementary PWM signals.

[0065] Specifically, in this embodiment of the invention, by configuring the first drive signal terminal PWM1 and the second drive signal terminal PWM2 as a set of complementary PWM signals, this design helps to prevent the risk of power short circuit caused by the simultaneous conduction of two sets of power switches (M1, M2 and M3, M4). The complementary signals ensure that when one set of power switches (such as M1, M2) is turned on, the other set of power switches (M3, M4) is turned off, thereby providing an orderly path for energy conversion through the transformer windings and improving the safety and reliability of the system.

[0066] Accordingly, refer to Figure 2 If the first drive signal terminal PWM1 and the second drive signal terminal PWM2 output a set of complementary square wave signals that alternate with time and have dead time, then the working process of the push-pull inverter T is as follows:

[0067] During the time interval t1 to t2, the first drive signal terminal PWM1 is at a high level while the second drive signal terminal PWM2 is at a low level. At this time, the first set of power switches M1 and M2 are synchronously driven to turn on, while the second set of power switches M3 and M4 are turned off. The current provided by the DC input power supply VDD is distributed to two independent paths: one path flows through the first primary winding N1, the second power switch M2, and to ground; the other path flows through the second primary winding N2, the first power switch M1, and to ground. Energy is transferred from the primary side to the secondary side through the transformer, realizing forward power conversion. At time t2, the falling edge of the first drive signal terminal PWM1 arrives, and the first set of power switches M1 and M2 begin to turn off. Since the drain of each switch is only connected to a single winding, the parasitic inductance and junction capacitance in the turn-off circuit are effectively reduced, significantly suppressing the turn-off overvoltage, allowing the drain-source voltage Vds to rise smoothly, and avoiding high-amplitude oscillations and voltage spikes.

[0068] During the time interval t3 to t4, the second drive signal terminal PWM2 is at a high level while the first drive signal terminal PWM1 is at a low level. At this time, the second set of power switches M3 and M4 are turned on, and the first set of power switches M1 and M2 are turned off. The current path is converted to: one path through the third primary winding N4 and the third power switch M3 to ground; the other path through the fourth primary winding N5 and the fourth power switch M4 to ground. Energy is coupled to the secondary side of the transformer in reverse polarity. At time t4, the falling edge of the second drive signal terminal PWM2 arrives, and M3 and M4 enter the turn-off process. Their drain-source voltage change is similar to the aforementioned process, and the voltage stress is effectively controlled without obvious overshoot.

[0069] This process repeats periodically, using two sets of complementary PWM signals to drive the independent and symmetrical power circuits on both sides to work alternately. This not only expands the output power capability and improves dynamic current sharing, but also significantly reduces switching stress and improves the overall reliability of the system.

[0070] In a preferred embodiment of this utility model, the first AC input terminal of the bridge rectifier 2 is connected to the first terminal 4 of the secondary winding N3, and the second AC input terminal of the bridge rectifier 2 is connected to the second terminal 5 of the secondary winding N3.

[0071] Specifically, in this embodiment of the invention, the connection structure directly feeds the AC voltage induced by the secondary winding N3 of the push-pull transformer T into the AC input terminal of the bridge rectifier 2. Utilizing the full-wave rectifier circuit formed by the diodes inside the rectifier bridge, the alternating positive and negative half-cycle induced voltages are converted into a single-polarity pulsating DC voltage, laying the foundation for subsequent filtering and output. This design achieves efficient high-frequency AC to DC conversion and is a key link in the inverter's energy transfer path.

[0072] In a preferred embodiment of this utility model, the positive output terminal of the bridge rectifier 2 is connected to the positive terminal of the power supply voltage E, and the negative output terminal of the bridge rectifier 2 is connected to the negative terminal of the power supply voltage E.

[0073] Specifically, in this embodiment of the present invention, the connection method directly applies the pulsating DC voltage output by the bridge rectifier 2 to both ends of the power supply voltage E, so that the power supply voltage E works as a filter capacitor and energy storage unit to smooth the voltage waveform after rectification and suppress the output voltage ripple, thereby forming a stable and continuous DC output voltage between the positive and negative terminals of the power supply voltage E, providing a stable power supply for the subsequent load circuit.

[0074] In a preferred embodiment of the present invention, the first power switch M1, the second power switch M2, the third power switch M3 and the fourth power switch M4 are metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs).

[0075] Specifically, in this embodiment of the invention, a metal-oxide-semiconductor field-effect transistor (MOSFET) is preferably used as the power switch. This choice effectively meets the application requirements of high-frequency switching in inverters and fully leverages the current-sharing advantages of the topology of this invention. This is achieved because MOSFETs have the characteristics of simple driving, fast switching speed, and low on-resistance, making them particularly suitable for multi-MOSFET parallel operation and PWM high-frequency driving scenarios. The circuit structure of this invention, through forced current sharing, precisely compensates for the uneven current distribution defects that may be caused by the dispersion of MOSFET parameters, enabling low-cost MOSFETs to operate safely and efficiently in parallel in high-current applications. For higher current density and voltage withstand capability, an insulated-gate bipolar transistor (IGBT) can also be selected.

[0076] In summary, this invention, through its unique connection method of parallel winding of the transformer connected to the power switching transistor, effectively reduces the equivalent junction capacitance and circuit parasitic inductance, thereby significantly suppressing the turn-off reverse peak voltage. (Refer to...) Figure 3 The measured peak startup voltage was significantly reduced from 100.8V in the traditional solution to 86.8V, a decrease of 13.9%. This core improvement fundamentally enhances the reliability of high-power inverters under extreme operating conditions and provides an effective and economical solution to the voltage stress problem of multi-tube parallel systems.

[0077] It is worth mentioning that, in addition to the above-mentioned single-transformer multi-winding design, multiple independent transformers can also be connected in parallel to achieve power expansion. Specifically, the primary windings of multiple push-pull transformers T with identical structures can be connected in series with their corresponding independent power switching transistors, and then connected in parallel to the DC input power supply VDD. The secondary windings are then connected in parallel and together to the input terminal of the bridge rectifier 2.

[0078] However, this solution requires the use of multiple magnetic cores and coil frames, as well as the configuration of multiple independent drive circuits, which significantly increases the number of magnetic components, PCB area and material costs. At the same time, the leakage inductance and parameter dispersion between multiple transformers may introduce new current sharing and oscillation problems. The system volume, weight and overall complexity are higher than the single transformer multi-winding integrated solution proposed in this utility model.

[0079] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model. Those skilled in the art should realize that all solutions obtained by equivalent substitutions and obvious changes made based on the description and illustrations of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A push-pull inverter circuit for reducing peak voltage, characterized in that, include: A push-pull transformer (T), the push-pull transformer (T) comprising multiple primary windings and a secondary winding (N3); Multiple power switching transistors are controllably connected between the primary winding and the ground terminal; A bridge rectifier (2), the input terminal of which is connected to the secondary winding (N3), and the output terminal of which is connected to a power supply voltage (E); Each of the power switches is independently connected to a primary winding, forming multiple independent power switch-winding series branches.

2. The push-pull inverter circuit for reducing peak voltage according to claim 1, characterized in that, The push-pull transformer (T) has four primary windings, including a first primary winding (N1), a second primary winding (N2), a third primary winding (N4), and a fourth primary winding (N5). The number of power switching transistors is four, including: The first power switch (M1) is controllably connected between the ground terminal and the second primary winding (N2); The second power switch (M2) is controllably connected between the ground terminal and the first primary winding (N1); The third power switch (M3) is controllably connected between the ground terminal and the third primary winding (N4); The fourth power switch (M4) is controllably connected between the ground terminal and the fourth primary winding (N5).

3. A push-pull inverter circuit for reducing peak voltage according to claim 2, characterized in that, The drain of the first power switch (M1) is connected to the first end (6) of the second primary winding (N2); The drain of the second power switch (M2) is connected to the first end (1) of the first primary winding (N1); The drain of the third power switch (M3) is connected to the first end (3) of the third primary winding (N4); The drain of the fourth power switch (M4) is connected to the first end (7) of the fourth primary winding (N5); The sources of the first power switch (M1), the second power switch (M2), the third power switch (M3), and the fourth power switch (M4) are all connected to the ground terminal; The second ends of the first primary winding (N1), the second primary winding (N2), the third primary winding (N4), and the fourth primary winding (N5) are all connected to a DC input power supply (VDD).

4. A push-pull inverter circuit for reducing peak voltage according to claim 3, characterized in that, The second ends of the first primary winding (N1) and the second primary winding (N2) are connected in parallel to the first common contact (A), and the second ends of the third primary winding (N4) and the fourth primary winding (N5) are connected in parallel to the second common contact (B). The first common contact (A) and the second common contact (B) are both connected to the DC input power supply (VDD).

5. A push-pull inverter circuit for reducing peak voltage according to claim 2, characterized in that, The gate of the first power switch (M1) and the gate of the second power switch (M2) are connected in parallel to the first drive signal terminal (PWM1); The gates of the third power switch (M3) and the fourth power switch (M4) are connected in parallel to the second drive signal terminal (PWM2).

6. A push-pull inverter circuit for reducing peak voltage according to claim 1, characterized in that, The first AC input terminal of the bridge rectifier (2) is connected to the first terminal (4) of the secondary winding (N3), and the second AC input terminal of the bridge rectifier (2) is connected to the second terminal (5) of the secondary winding (N3).

7. A push-pull inverter circuit for reducing peak voltage according to claim 6, characterized in that, The positive output terminal of the bridge rectifier (2) is connected to the positive terminal of the power supply voltage (E), and the negative output terminal of the bridge rectifier (2) is connected to the negative terminal of the power supply voltage (E).

8. A push-pull inverter circuit for reducing peak voltage according to claim 2, characterized in that, The first power switch (M1), the second power switch (M2), the third power switch (M3) and the fourth power switch (M4) are metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs).

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