Three-level inverter circuit and photovoltaic inverter

Abstract

The utility model provides a kind of three-level inverter circuit and photovoltaic inverter, it is related to power semiconductor technical field, including: four power semiconductor devices are sequentially connected in a straight line, and the collector electrode between the two power semiconductor devices in middle is connected with clamping device;Wherein, diode in each power semiconductor device is junction barrier schottky diode.A beneficial effect is that by replacing fast recovery diode (Si FRD) in power semiconductor device with junction barrier schottky diode (JBS-SiC FRD), effectively improve the high-frequency switching performance and surge resistance of three-level inverter circuit.

Description

Technical Field

[0001] This utility model relates to the field of power semiconductor technology, and in particular to a three-level inverter circuit and a photovoltaic inverter. Background Technology

[0002] As a key component in photovoltaic power generation systems, the performance of photovoltaic inverters directly impacts the overall system's power generation efficiency, reliability, and stability. In traditional photovoltaic inverters, a two-level topology is a common design. This structure requires switching devices to operate at high voltage and high frequency. Since each switching action involves energy loss, the high-frequency switching operations cause these losses to accumulate, reducing the overall inverter efficiency. Simultaneously, the switching devices experience significant voltage stress, necessitating the selection of components with higher voltage ratings, which not only increases cost but may also lead to larger device sizes. Furthermore, the two-level topology generates large voltage and current changes during switching, resulting in significant electromagnetic interference that can disrupt surrounding electronic equipment and affect the system's normal operation.

[0003] To address the problems inherent in two-level topologies, three-level topologies were developed. By introducing an intermediate voltage level, the three-level topology reduces the voltage stress on switching devices to half the bus voltage. This change offers several advantages. First, the reduced voltage stress allows for the selection of switching devices with lower voltage ratings, thus lowering device cost and size. Second, the reduced voltage change rate results in a smoother current change in the inductor, allowing for a smaller inductor size, further saving space and cost. Most importantly, system losses are effectively reduced because the energy loss during switching is decreased, improving the overall inverter efficiency.

[0004] However, when the three-level topology is in high-frequency switching operation, the reverse recovery current (Qrr) of the traditional silicon-based fast recovery diode (SiFRD) is relatively high. This not only leads to increased switching losses, but also makes the device unable to withstand surge current, which can easily cause device failure.

[0005] To address the aforementioned issues, silicon carbide (SiC) devices have gradually come into focus. Silicon carbide is a wide-bandgap semiconductor material with numerous advantages over traditional silicon. First, SiC devices exhibit near-zero reverse recovery current. This means that energy losses due to reverse recovery current during switching are negligible, significantly reducing switching losses. Second, SiC devices possess high voltage withstand characteristics, enabling stable operation at higher voltages, which facilitates the design of higher-power photovoltaic inverters. Furthermore, SiC devices exhibit good high-temperature stability, maintaining stable performance in high-temperature environments and reducing performance fluctuations caused by temperature variations. However, traditional SiC Schottky diodes (SBDs) have relatively weak surge protection; when large surge currents occur in the system, Schottky diodes may fail to withstand the surge and suffer damage.

[0006] Improving the high-frequency switching performance and surge protection of three-level topologies has become an urgent technical problem to be solved. Utility Model Content

[0007] To address the problems existing in the prior art, this utility model provides a three-level inverter circuit, including four power semiconductor devices connected in series in a straight line, and a clamp is connected in series between the collectors of the two middle power semiconductor devices.

[0008] The diodes in each of the power semiconductor devices are junction barrier Schottky diodes.

[0009] Preferably, the linear connection structure includes:

[0010] A first power semiconductor device, wherein the collector of the first power semiconductor device serves as the positive output terminal of a three-level inverter circuit;

[0011] A second power semiconductor device, wherein the collector of the second power semiconductor device is connected to the emitter of the first power semiconductor device and one end of the clamp, respectively;

[0012] A third power semiconductor device, wherein the collector of the third power semiconductor device is connected to the emitter and neutral point of the second power semiconductor device, respectively;

[0013] A fourth power semiconductor device, the collector of which is connected to the emitter of the third power semiconductor device and the other end of the clamp, and the emitter of the fourth power semiconductor device serves as the negative output terminal of the three-level inverter circuit.

[0014] Preferably, the clamp includes:

[0015] A first clamping diode, wherein the cathode of the first clamping diode is connected to the collector of the second power semiconductor device;

[0016] The second clamping diode has its cathode connected to the anode of the first clamping diode, and its anode connected to the collector of the third power semiconductor device.

[0017] Preferably, the first clamping diode and the second clamping diode are junction barrier Schottky diodes.

[0018] Preferably, each of the power semiconductor devices is an N-type power semiconductor device.

[0019] This utility model also provides a photovoltaic inverter, including the above-mentioned three-level inverter circuit.

[0020] The above technical solution has the following advantages or beneficial effects: by replacing the fast recovery diode (Si FRD) in the power semiconductor device with the junction barrier Schottky diode (JBS-SiC FRD), the high-frequency switching performance and surge protection capability of the three-level inverter circuit are effectively improved. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a three-level inverter circuit, which is a preferred embodiment of the present invention. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within its scope.

[0023] In a preferred embodiment of this utility model, based on the above-mentioned problems existing in the prior art, a three-level inverter circuit is provided, such as... Figure 1 As shown, it includes four power semiconductor devices connected in series in a straight line, and a clamp is connected in series between the collectors of the two power semiconductor devices in the middle.

[0024] Among them, the diodes in each power semiconductor device are junction barrier Schottky diodes.

[0025] Specifically, since the surge protection capability of fast recovery diodes in power semiconductor devices is relatively weak, limiting their application in high-voltage scenarios, in this embodiment, the fast recovery diode (Si FRD) in the power semiconductor device is replaced with a junction barrier Schottky diode (JBS-SiC FRD) to improve the high-frequency switching performance and surge protection capability of the three-level inverter circuit.

[0026] Furthermore, the advantages of using a junction barrier Schottky diode (JBS-SiC FRD) are as follows:

[0027] 1. Optimize reverse recovery characteristics

[0028] Because the reverse recovery current of the junction barrier Schottky diode (JBS-SiC FRD) is almost zero, it can significantly reduce high-frequency switching losses by more than 90% compared to the fast recovery diode (Si FRD). This characteristic greatly reduces circuit energy loss in high-frequency switching conditions, thereby improving the overall efficiency of the three-level inverter circuit. Experimental data shows that using the junction barrier Schottky diode (JBS-SiC FRD) can improve inverter efficiency by 2% and increase the switching frequency beyond 100kHz.

[0029] 2. Enhance surge resistance

[0030] The carrier injection effect of the junction barrier Schottky diode (JBS-SiC FRD) enhances its surge current tolerance, enabling it to withstand surge currents up to 11 times the rated current. This effectively avoids the overcurrent risk caused by capacitor charging during power-on, ensuring stable circuit operation under complex conditions. Industry verification shows that devices using the three-level inverter circuit of this invention exhibit high energy handling capabilities in non-clamped inductive load switching tests, meeting the demands of demanding scenarios such as new energy vehicles.

[0031] 3. Enhance reactive power support capability

[0032] During grid voltage dips, the low-loss characteristics enable inverters using the three-level inverter circuit of this invention to continuously output larger reactive currents (e.g., 1.2 times the rated current), quickly supporting grid voltage recovery and complying with various LVRT standards (e.g., China's GB / T 19964-2012).

[0033] 4. Heat dissipation optimization

[0034] The junction barrier Schottky diode (JBS-SiC FRD) utilizes SiC material with high thermal conductivity (3.7 W / cm·K), and combined with a low thermal resistance package (such as TO-247-4), effectively improves heat dissipation efficiency, ensuring that devices using the three-level inverter circuit of this invention maintain good thermal stability during operation. Actual measurement data shows that this packaging scheme can reduce junction temperature by 15% and extend device lifespan.

[0035] 5. High temperature resistance

[0036] Junction Barrier Schottky Diodes (JBS-SiC FRDs) using SiC material can operate stably above 200°C, while silicon-based devices are typically limited to below 150°C. In the high-temperature environment of photovoltaic systems, JBS-SiC FRDs can operate reliably with complex heat dissipation designs, reducing system cooling costs.

[0037] 6. Avalanche resistance

[0038] Replacing the fast recovery diode (Si FRD) in the power semiconductor device with a junction barrier Schottky diode (JBS-SiC FRD) enhances the avalanche immunity of devices using the three-level inverter circuit of this invention. It passes 100% rated withstand voltage testing, ensuring long-term operational reliability. This feature enables the device to adapt to voltage transient scenarios, meeting the requirements of industrial and automotive applications.

[0039] In a preferred embodiment of this utility model, the linear connection structure includes:

[0040] The first power semiconductor device T1, the collector of the first power semiconductor device T1 serves as the positive output terminal P+ of the three-level inverter circuit;

[0041] The collector of the second power semiconductor device T2 is connected to the emitter of the first power semiconductor device T1 and one end of the clamp 100, respectively.

[0042] The collector of the third power semiconductor device T3 is connected to the emitter and neutral point N of the second power semiconductor device T2, respectively.

[0043] The collector of the fourth power semiconductor device T4 is connected to the emitter of the third power semiconductor device T3 and the other end of the clamp 100, respectively. The emitter of the fourth power semiconductor device T4 serves as the negative output terminal P- of the three-level inverter circuit.

[0044] In this device, a first junction barrier Schottky diode D1 is connected between the collector and emitter of the first power semiconductor device T1, a second junction barrier Schottky diode D2 is connected between the collector and emitter of the second power semiconductor device T2, a third junction barrier Schottky diode D3 is connected between the collector and emitter of the third power semiconductor device T3, and a fourth junction barrier Schottky diode D4 is connected between the collector and emitter of the fourth power semiconductor device T4.

[0045] In a preferred embodiment of this utility model, the clamp 100 includes:

[0046] The cathode of the first clamping diode D5 is connected to the collector of the second power semiconductor device T2.

[0047] The cathode of the second clamping diode D6 is connected to the anode of the first clamping diode D5, and the anode of the second clamping diode D6 is connected to the collector of the third power semiconductor device T3.

[0048] In a preferred embodiment of this invention, the first clamping diode D5 and the second clamping diode D6 are junction barrier Schottky diodes.

[0049] In a preferred embodiment of this invention, each power semiconductor device is an N-type power semiconductor device.

[0050] This utility model also provides a photovoltaic inverter, including the above-mentioned three-level inverter circuit.

[0051] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model. Those skilled in the art should realize that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present utility model.

Claims

1. A three-level inverter circuit, characterized in that, It includes four power semiconductor devices connected in series in a line, and a clamp is connected in series between the collectors of the two middle power semiconductor devices. The clamp includes two junction barrier Schottky diodes connected in series. The diodes in each of the power semiconductor devices are junction barrier Schottky diodes.

2. The three-level inverter circuit according to claim 1, characterized in that, The linear connection structure includes: A first power semiconductor device, wherein the collector of the first power semiconductor device serves as the positive output terminal of a three-level inverter circuit; A second power semiconductor device, wherein the collector of the second power semiconductor device is connected to the emitter of the first power semiconductor device and one end of the clamp, respectively; A third power semiconductor device, wherein the collector of the third power semiconductor device is connected to the emitter and neutral point of the second power semiconductor device, respectively; A fourth power semiconductor device, the collector of which is connected to the emitter of the third power semiconductor device and the other end of the clamp, respectively, and the emitter of the fourth power semiconductor device serves as the negative output terminal of the three-level inverter circuit.

3. The three-level inverter circuit according to claim 2, characterized in that, The clamp includes: A first clamping diode, wherein the cathode of the first clamping diode is connected to the collector of the second power semiconductor device; The second clamping diode has its cathode connected to the anode of the first clamping diode, and its anode connected to the collector of the third power semiconductor device.

4. The three-level inverter circuit according to claim 3, characterized in that, The first clamping diode and the second clamping diode are junction barrier Schottky diodes.

5. The three-level inverter circuit according to claim 1, characterized in that, Each of the power semiconductor devices is an N-type power semiconductor device.

6. A photovoltaic inverter, characterized in that, Includes the three-level inverter circuit as described in any one of claims 1-5.

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