A flip-flop circuit, a clock gating circuit, a frequency divider circuit, and an integrated circuit

Abstract

The application provides a flip-flop circuit, a clock gating circuit, a frequency divider circuit and an integrated circuit, and is applied to the technical field of integrated circuits.The flip-flop circuit comprises a sampling circuit, a preprocessing circuit, a maintaining circuit and a driving circuit.The sampling circuit acquires an input signal.The preprocessing circuit outputs a low-level driving signal or a high-level driving signal in response to the input signal.The maintaining circuit maintains the output unchanged in response to the low-level driving signal, or outputs a load signal opposite to the input signal in response to the high-level driving signal.The driving circuit drives a subsequent load circuit in response to the output of the maintaining circuit.The preprocessing circuit adopts a non-full swing structure, and the voltage amplitude between the driving signals output by the preprocessing circuit is smaller than the working voltage amplitude of the flip-flop circuit.Because the dynamic loss of the flip-flop is positively correlated with the swing of the driving signal output by the preprocessing circuit, the adoption of the non-full swing structure by the preprocessing circuit can reduce the swing of the driving signal output by the preprocessing circuit, and thus effectively reduce the dynamic loss of the flip-flop circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a trigger circuit, a clock gate circuit, a frequency divider circuit, and an integrated circuit. Background Technology

[0002] Flip-flops are important unit circuits in integrated circuits, used to implement various functions such as clock control and frequency conversion. With the continuous increase in the scale of integrated circuits in recent years, the number of flip-flops required in integrated circuits is also increasing. Correspondingly, the power consumption of flip-flops accounts for a larger proportion of the overall power consumption of integrated circuits. Taking TSPC (TrueSingle Phase Clock) flip-flops as an example, the dynamic logic of a typical TSPC flip-flop relies on node capacitors to store data. If the system is idle for a long time, it will lead to charge leakage and may cause data errors. In order to ensure reliable data storage, even if the system is idle, a clock signal must be continuously provided to maintain the state of the TSPC flip-flop, resulting in invalid power consumption. Therefore, how to further reduce the power consumption of flip-flops and thus reduce the overall power consumption of integrated circuits has become one of the technical problems that urgently need to be solved by those skilled in the art. Utility Model Content

[0003] In view of this, this application aims to provide a trigger circuit, a clock gate circuit, a frequency divider circuit, and an integrated circuit to solve the problem that the high power consumption of triggers in the prior art makes it difficult to meet the needs of practical applications.

[0004] In a first aspect, this application provides a trigger circuit, comprising: A sampling circuit is used to acquire the input signal; The preprocessing circuit is connected to the sampling circuit and outputs a low-level drive signal or a high-level drive signal in response to the input signal. A sustaining circuit, connected to the preprocessing circuit, maintains the output unchanged in response to the high-level drive signal, or outputs a load signal opposite to the input signal in response to the low-level drive signal; A driving circuit, connected to the sustaining circuit, drives the subsequent load circuit in response to the output of the sustaining circuit; The preprocessing circuit adopts a non-full swing structure, and the voltage amplitude between the high-level drive signal and the low-level drive signal is less than the operating voltage amplitude of the trigger circuit.

[0005] In one optional embodiment, the preprocessing circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein, The source of the first PMOS transistor is used to receive the operating voltage of the flip-flop circuit, the gate of the first PMOS transistor is used to receive the clock signal, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; The source of the third PMOS transistor is used to receive the operating voltage, the gate of the third PMOS transistor is used to receive the clock signal, and the drain of the third PMOS transistor is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is used to receive the clock signal, and the source of the third NMOS transistor is grounded. The gate of the second PMOS transistor and the gate of the second NMOS transistor are respectively connected to the output terminal of the adoption circuit; The connection point between the second PMOS transistor and the first NMOS transistor serves as the first output terminal of the preprocessing circuit. The connection point between the first NMOS transistor and the second NMOS transistor serves as the second output terminal of the preprocessing circuit.

[0006] In one optional implementation, the sustaining circuit includes: a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein, The source of the fourth PMOS transistor is used to receive the operating voltage, the gate of the fourth PMOS transistor is connected to the second output terminal of the preprocessing circuit, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is used to receive the clock signal, and the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the first output terminal of the preprocessing circuit, and the source of the fifth NMOS transistor is grounded.

[0007] In one optional implementation, the driving circuit includes: a fifth PMOS transistor and a sixth NMOS transistor, wherein, The source of the fifth PMOS transistor is used to receive the operating voltage of the trigger circuit, and the drain of the fifth PMOS transistor is connected to the drain of the sixth NMOS transistor. The source of the sixth NMOS transistor is grounded; The gate of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor, and the resulting connection point serves as the input terminal of the driving circuit. The connection point between the drain of the fifth PMOS transistor and the drain of the sixth NMOS transistor serves as the output terminal of the driving circuit.

[0008] In one optional implementation, the sampling circuit includes: a sixth PMOS transistor, a seventh PMOS transistor, and a seventh NMOS transistor, wherein, The source of the sixth PMOS transistor is used to receive the operating voltage of the trigger circuit, and the drain of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor. The gate of the seventh PMOS transistor serves as the clock input terminal of the sampling circuit, and the drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is grounded; The gate of the sixth PMOS transistor is connected to the gate of the seventh NMOS transistor, and the resulting connection point serves as the input terminal of the sampling circuit. The connection point between the seventh PMOS transistor and the seventh NMOS transistor serves as the output terminal of the sampling circuit.

[0009] Secondly, this application provides a clock-gated circuit, comprising: a combinational logic circuit and a flip-flop circuit as provided in any embodiment of the first aspect of this application, wherein... The clock input terminal of the combinational logic circuit is connected to the clock input terminal of the sampling circuit in the flip-flop circuit; The signal input terminal of the combinational logic circuit is connected to the output terminal of the drive circuit in the flip-flop circuit.

[0010] In one alternative implementation, the combinational logic circuit includes: AND gate, OR gate, and NOR gate.

[0011] Thirdly, this application provides a frequency divider circuit, including: A sampling circuit is used to acquire the input signal; The preprocessing circuit is connected to the sampling circuit and outputs a low-level drive signal or a high-level drive signal in response to the input signal. A sustaining circuit, connected to the preprocessing circuit, maintains the output unchanged in response to the high-level drive signal, or outputs a load signal opposite to the input signal in response to the low-level drive signal; A driving circuit, connected to the sustaining circuit, drives the subsequent load circuit in response to the output of the sustaining circuit; The sustaining circuit is also connected to the sampling circuit, and the signal output by the sustaining circuit serves as the input signal. The preprocessing circuit adopts a non-full swing structure, and the voltage amplitude between the high-level drive signal and the low-level drive signal is less than the operating voltage amplitude of the trigger circuit.

[0012] Fourthly, this application provides a frequency divider circuit, including: a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first NAND gate circuit, and a second NAND gate circuit, wherein... The first trigger circuit, the second trigger circuit, and the third trigger circuit are each adopted as provided in any embodiment of the first aspect of this application; The output terminal of the driving circuit in the first flip-flop circuit is connected to the input terminal of the sampling circuit in the second flip-flop circuit; The output of the driving circuit in the second flip-flop is connected to the first input of the first NAND gate circuit, and the output of the holding circuit in the second flip-flop is connected to the first input of the second NAND gate circuit. The output of the second NAND gate is connected to the input of the sampling circuit in the third flip-flop circuit; The output terminal of the driving circuit in the third flip-flop circuit is connected to the second input terminal of the first NAND gate circuit, and the output terminal of the first NAND gate circuit is connected to the input terminal of the sampling circuit in the first flip-flop circuit. The second input terminal of the second NAND gate is used to receive a control signal, which is used to adjust the division ratio of the frequency divider circuit.

[0013] Fifthly, this application provides an integrated circuit including at least one trigger circuit as provided in any embodiment of the first aspect of this application.

[0014] Based on the above, the trigger circuit provided in this application includes a sampling circuit, a preprocessing circuit, a holding circuit, and a driving circuit. The sampling circuit acquires the input signal, the preprocessing circuit outputs a low-level driving signal or a high-level driving signal in response to the input signal, the holding circuit maintains the output unchanged in response to the low-level driving signal, or outputs a load signal opposite to the input signal in response to the high-level driving signal, and the driving circuit drives the subsequent load circuit in response to the output of the holding circuit. Compared with the trigger circuits using a full-swing structure in the prior art, the trigger circuit provided in this application uses a non-full-swing structure in the preprocessing circuit. The voltage amplitude between the high-level driving signal and the low-level driving signal output by the preprocessing circuit is less than the operating voltage amplitude of the trigger circuit. Since the dynamic loss of the trigger is positively correlated with the swing of the output driving signal of the preprocessing circuit, the non-full-swing structure of the preprocessing circuit can reduce the swing of its output driving signal, thereby effectively reducing the dynamic loss of the trigger circuit and helping to reduce the overall loss of the integrated circuit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a structural block diagram of a trigger circuit provided in an embodiment of the present invention.

[0017] Figure 2 This is a circuit topology diagram of a trigger circuit provided in an embodiment of this utility model.

[0018] Figure 3 This is a structural block diagram of a clock gating circuit provided in an embodiment of the present invention.

[0019] Figure 4 This is a structural block diagram of a frequency divider circuit provided in an embodiment of this utility model.

[0020] Figure 5 This is a structural block diagram of another frequency divider circuit provided in this embodiment of the present invention. Detailed Implementation The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The efficient operation of core computing circuits in high-speed digital signal processing, artificial intelligence, and high-performance computing relies on strong hardware support. Large-scale computing power requires a large number of computing chips. Reducing power consumption and increasing computing speed are important issues facing large-scale integrated circuits.

[0022] Flip-flops are important unit circuits in integrated circuits, used to implement various functions such as clock control and frequency conversion. With the continuous increase in the scale of integrated circuits in recent years, the number of flip-flops required in integrated circuits is also increasing. Correspondingly, the power consumption of flip-flops accounts for a larger proportion of the overall power consumption of integrated circuits. Taking TSPC flip-flops as an example, the dynamic logic of a typical TSPC flip-flop relies on node capacitors to store data. If the system is idle for a long time, it will lead to charge leakage and may cause data errors. In order to ensure reliable data storage, even if the system is idle, a clock signal must be continuously provided to maintain the state of the TSPC flip-flop, resulting in invalid power consumption. Therefore, how to further reduce the power consumption of flip-flops and thus reduce the overall power consumption of integrated circuits has become one of the technical problems that urgently need to be solved by those skilled in the art.

[0023] To address the aforementioned issues, this application provides a trigger circuit in which a preprocessing circuit employing a non-full-swing structure is incorporated. Compared to existing trigger circuits employing a full-swing structure, the voltage amplitude between the drive signals output by the preprocessing circuit is smaller than the operating voltage amplitude of the trigger circuit. Since the dynamic loss of the trigger is positively correlated with the swing of the drive signal output by the preprocessing circuit, the non-full-swing structure of the preprocessing circuit can reduce the swing of its output drive signal, thereby effectively reducing the dynamic loss of the trigger circuit and contributing to a reduction in the overall loss of the integrated circuit.

[0024] Based on the above, see Figure 1 As shown, the trigger circuit provided in this application embodiment includes: a sampling circuit 10, a preprocessing circuit 20, a sustaining circuit 30, and a driving circuit 40.

[0025] Combination Figure 1 As shown, the sampling circuit 10 has an input terminal and an output terminal. The input terminal of the sampling circuit 10 is used to receive the input signal. In practical applications, the input signal is provided by the pre-stage circuit connected to the trigger circuit. The input signal can be a high-level signal or a low-level signal. The output terminal of the sampling circuit 10 is connected to the pre-processing circuit 20, and the input signal is obtained through the sampling circuit 10.

[0026] In one alternative implementation, the sampling process of the sampling circuit 10 for the input signal is controlled by a clock signal. Based on this, the sampling circuit 10 is also provided with a clock input terminal. Figure 1(Not shown in the diagram) The sampling circuit 10 receives a clock signal through its clock input terminal. In practical applications, the clock signal can be provided by the clock source in the integrated circuit to which the flip-flop circuit belongs. Of course, the clock signal can also be provided to the sampling circuit 10 in other ways, which will not be described in detail here. The sampling circuit 10 responds to the obtained clock signal and samples the input signal when the clock signal is valid (for example, it can be configured to be valid on the rising edge or the falling edge), and further outputs the result to the subsequent preprocessing circuit 20.

[0027] The input terminal of the preprocessing circuit 20 is connected to the output terminal of the sampling circuit 10, and the output terminal of the preprocessing circuit 20 is connected to the input terminal of the subsequent holding circuit 30. The preprocessing circuit 10 outputs a low-level drive signal or a high-level drive signal in response to the obtained input signal. The specific process by which the preprocessing circuit 10 outputs a low-level drive signal or a high-level drive signal based on the input signal will be detailed later and will not be elaborated here. Compared to preprocessing circuits using a full-swing structure in related technologies, the trigger circuit provided in this embodiment uses a non-full-swing sampling structure in the preprocessing circuit 20. The voltage amplitude between the high-level drive signal and the low-level drive signal output by the preprocessing circuit 20 is smaller than the operating voltage amplitude of the trigger circuit.

[0028] In one optional implementation, the process of the preprocessing circuit 20 outputting the drive signal is controlled by a clock signal. Based on this, the preprocessing circuit 20 is also provided with a clock input terminal. Figure 1 (Not shown in the diagram) The preprocessing circuit 20 receives a clock signal through a clock input terminal. In practical applications, the preprocessing circuit 20 can use the same clock source as the sampling circuit 10. In response to the received clock signal, the preprocessing circuit 20 outputs a low-level drive signal or a high-level drive signal when the clock signal is valid (e.g., it can be configured to be rising edge valid or falling edge valid).

[0029] The sustaining circuit 30 is connected to both the preprocessing circuit 20 and the driving circuit 40. Responding to a low-level driving signal provided by the preprocessing circuit 20, the sustaining circuit 30 maintains its output unchanged; that is, it maintains the output unchanged when the preprocessing circuit 20 outputs a high-level driving signal. In other words, when the preprocessing circuit 20 outputs a low-level driving signal, the output of the sustaining circuit 30 remains unchanged. Furthermore, when the preprocessing circuit 20 outputs a high-level driving signal, the sustaining circuit 30 responds to the received high-level driving signal by outputting a load signal opposite to the input signal. That is, when the input signal is high-level, the sustaining circuit 30 outputs a low-level load signal, and when the input signal is low-level, the sustaining circuit 30 outputs a high-level load signal.

[0030] In one alternative implementation, the process of maintaining the output drive signal of the sustaining circuit 30 is controlled by a clock signal. Based on this, the sustaining circuit 30 is also provided with a clock input terminal. Figure 1 (Not shown in the diagram) The clock signal is received through the clock input terminal. In practical applications, the sustaining circuit 30 can use the same clock source as the sampling circuit 10 and the preprocessing circuit 20. In response to the received clock signal, the sustaining circuit 30 maintains the output unchanged or outputs a load signal opposite to the input signal when the clock signal is valid.

[0031] The input terminal of the drive circuit 40 is connected to the sustaining circuit 30, and the output terminal of the drive circuit 40 is used to connect to the load circuit after the trigger circuit. In response to the output of the sustaining circuit 30, it drives the load circuit. As described above, the sustaining circuit 30 outputs a load signal opposite to the input signal. To correctly drive the load circuit, the signal ultimately output by the drive circuit 40 to the load circuit should be consistent with the input signal. Therefore, the drive circuit 40 should invert the output of the sustaining circuit 30. Specifically, when the sustaining circuit 30 outputs a low-level load signal, the drive circuit 40 outputs a high-level signal to the load circuit; conversely, when the sustaining circuit 30 outputs a high-level load signal, the drive circuit 40 outputs a low-level signal to the load circuit.

[0032] In practical applications, the power consumption of the trigger circuit mainly includes three aspects: dynamic power consumption, short-circuit power consumption and leakage power consumption. Among them, dynamic power consumption is the power consumption caused by the charging and discharging switching nodes in the circuit, which can be expressed by the following formula (1).

[0033] (1) in, Indicates dynamic power consumption; V DD This indicates the operating voltage of the trigger circuit; V SW This represents the capacitor voltage of the junction capacitance of the power device in the trigger circuit, which is also the voltage amplitude between the high-level drive signal and the low-level drive signal output by the preprocessing circuit. C L This represents the equivalent load capacitance of the subsequent load circuit. V out This indicates the output voltage of the trigger circuit.

[0034] Based on the above formula (1), the average dynamic power consumption of the trigger circuit can be expressed as: (2) in, Indicates average dynamic loss; Indicates the change over time; This indicates the switching activity, that is, the probability that a clock signal flip will cause a 0→1 flip at the output of the corresponding device; f represents the operating frequency of the flip-flop circuit.

[0035] Based on the aforementioned formula (2), for the full swing structure circuit in the related technology, Therefore, its corresponding dynamic power consumption can be expressed as: (3) For the non-full-swing structure circuit provided in this application, its corresponding dynamic power consumption can be expressed as: (4) Since VSW < VDD, therefore we have < That is, the dynamic loss of the trigger circuit provided in this application is less than the dynamic loss of the trigger circuit using the full swing circuit structure in related technologies.

[0036] In summary, compared to the existing trigger circuits that use a full-swing structure, the trigger circuit provided in this application uses a non-full-swing structure for the preprocessing circuit. The voltage amplitude between the high-level drive signal and the low-level drive signal output by the preprocessing circuit is less than the operating voltage amplitude of the trigger circuit. Since the dynamic loss of the trigger is positively correlated with the swing of the output drive signal of the preprocessing circuit, the use of a non-full-swing structure in the preprocessing circuit can reduce the swing of its output drive signal, thereby effectively reducing the dynamic loss of the trigger circuit and helping to reduce the overall loss of the integrated circuit.

[0037] Based on the above core idea, this application further provides an optional implementation of the trigger circuit, see [link to relevant documentation]. Figure 2 As shown, this embodiment provides a specific implementation topology for a trigger circuit.

[0038] Specifically, the sampling circuit 10 includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a seventh NMOS transistor N7. Combined with... Figure 2 As shown, the source of the sixth PMOS transistor P6 is used to receive the operating voltage V of the trigger circuit. DD The drain of the sixth PMOS transistor P6 is connected to the source of the seventh PMOS transistor P7. The gate of the seventh PMOS transistor P7 serves as the clock input of the sampling circuit, receiving the clock signal CK. The drain of the seventh PMOS transistor P7 is connected to the drain of the seventh NMOS transistor N7. The source of the seventh NMOS transistor N7 is grounded, i.e., connected to V. SSThe gate of the sixth PMOS transistor P6 is connected to the gate of the seventh NMOS transistor N7, and the resulting connection point serves as the input terminal of the sampling circuit. The connection point between the seventh PMOS transistor P7 and the seventh NMOS transistor N7 serves as the output terminal of the sampling circuit, receiving the input signal from the preceding stage circuit. Figure 1 The symbol X represents the character.

[0039] Combination Figure 2 As shown, the sampling circuit 10 functions the same as the inverter. Therefore, the signal output from the output terminal X of the sampling circuit 10 is at the opposite level to the input signal, i.e., X = .

[0040] The preprocessing circuit 20 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3.

[0041] Combination Figure 2 As shown, the source of the first PMOS transistor P1 is used to receive the operating voltage V of the trigger circuit. DD The gate of the first PMOS transistor P1 is used to receive the clock signal CK. The drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the drain of the first NMOS transistor N1. The source of the third PMOS transistor P3 is used to receive the working voltage. The gate of the third PMOS transistor P3 is used to receive the clock signal CK. The drain of the third PMOS transistor P3 is connected to the gate of the first NMOS transistor N1.

[0042] The source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, the source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3, the gate of the third NMOS transistor N3 is used to receive the clock signal CK, and the source of the third NMOS transistor N3 is grounded (V). SS ).

[0043] The gate of the second PMOS transistor P2 is connected to the gate of the second NMOS transistor N2, and the resulting connection point is connected to the output terminal X of the sampling circuit 10. That is, the gates of the second PMOS transistor P2 and the second NMOS transistor N2 are respectively connected to the output terminal X of the sampling circuit 10.

[0044] The connection point between the second PMOS transistor P2 and the first NMOS transistor N1 serves as the first output terminal of the preprocessing circuit 20. Figure 2 The term A represents the connection point between the first NMOS transistor N1 and the second NMOS transistor N2, which serves as the second output terminal of the preprocessing circuit 20. Figure 2 The middle part is represented by B.

[0045] The sustaining circuit 30 includes a fourth PMOS transistor P4, a fourth NMOS transistor N4, and a fifth NMOS transistor N5, wherein the source of the fourth PMOS transistor P4 is used to receive the operating voltage V. DD The gate of the fourth PMOS transistor P4 is connected to the second output terminal B of the preprocessing circuit 20. The drain of the fourth PMOS transistor P4 is connected to the drain of the fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 is used to receive the clock signal CK. The source of the fourth NMOS transistor N4 is connected to the drain of the fifth NMOS transistor N5. The gate of the fifth NMOS transistor N5 is connected to the first output terminal A of the preprocessing circuit. The source of the fifth NMOS transistor N5 is grounded (i.e., V). SS The connection point between the drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 serves as the output terminal of the sustaining circuit 30. Figure 2 It is represented as Qn.

[0046] The driving circuit 40 includes a fifth PMOS transistor P5 and a sixth NMOS transistor N6, wherein the source of the fifth PMOS transistor P5 is used to receive the operating voltage V of the trigger circuit. DD The drain of the fifth PMOS transistor P5 is connected to the drain of the sixth NMOS transistor N6, and the source of the sixth NMOS transistor N6 is grounded (i.e., V). SS The gate of the fifth PMOS transistor P5 is connected to the gate of the sixth NMOS transistor N6, and the resulting connection point serves as the input terminal of the drive circuit 40, which is connected to the output terminal Qn of the sustaining circuit 30. The drain of the fifth PMOS transistor P5 is connected to the drain of the sixth NMOS transistor N6, and the resulting connection point serves as the output terminal of the drive circuit 40. Figure 2 The middle part is represented by Q.

[0047] Combination Figure 2 As shown, the driving circuit 40 functions similarly to the inverter. Therefore, the signal output from the output terminal Q of the driving circuit 40 is opposite to the level output by the holding circuit 30. Furthermore, after two inversion processes by the sampling circuit 10 and the driving circuit 40, the final output of the driving circuit 40 is consistent with the input signal, i.e., Q = =D.

[0048] The following is combined Figure 2 The circuit topology shown illustrates the basic working process of the flip-flop circuit provided in this embodiment: When the clock signal CK=0, the sixth PMOS transistor P6, the third PMOS transistor P3, and the first PMOS transistor P1 are turned on, while the third NMOS transistor N3 and the fourth NMOS transistor N4 are turned off.

[0049] Based on the above premise, the output X of sampling circuit 10 = The output level of sampling circuit 10, X, is opposite to that of the input signal.

[0050] When the third PMOS transistor P3, the first PMOS transistor P1, and the first NMOS transistor N1 in the preprocessing circuit 20 are turned on, and X=0, the potential of the first output terminal A of the preprocessing circuit 20 is high, the preprocessing circuit 20 is in a pre-charge state, and the output terminal Qn of the maintenance circuit 30 is in a floating state, keeping the output unchanged.

[0051] Since the output of the maintaining circuit 30 remains unchanged, the output of the driving circuit 40 also remains unchanged.

[0052] When the clock signal CK=1, the third NMOS transistor N3 and the fourth NMOS transistor N4 are turned on, while the sixth PMOS transistor P6, the third PMOS transistor P3, and the first PMOS transistor P1 are turned off.

[0053] If the input signal is a low-level signal, the output terminal X of sampling circuit 10 floats and maintains a high-level output. Conversely, if the input signal is a high-level signal, the output terminal X of sampling circuit 10 outputs a low-level signal, satisfying X = .

[0054] Furthermore, the third NMOS transistor N3 in the preprocessing circuit 20 is turned on. When the output terminal X of the sampling circuit 10 is 1, the second output terminal B of the preprocessing circuit 20 is 0; correspondingly, when the output terminal X of the sampling circuit 10 is 0, the first output terminal A of the preprocessing circuit 20 is 1.

[0055] The output of the sustaining circuit 30 satisfies Qn= The output of the drive circuit satisfies Q= The final output of the flip-flop circuit satisfies Q= =D, at this point, the input signal processing is complete.

[0056] It should be noted that the preprocessing circuit 20 adopts a non-full swing structure, which makes the voltage amplitude between the first output terminal A and the second output terminal B of the preprocessing circuit 20 less than the operating voltage V of the trigger circuit. DD That is, less than V DD To V SS It has a full swing range, but its output voltage range can still drive NMOS and PMOS transistors in subsequent circuits.

[0057] For the preprocessing circuit 20, when the clock signal CK=0, the sampling circuit 10 satisfies X= The potential of node X is opposite to that of the input signal D. In the preprocessing circuit 20, the third PMOS transistor P3, the first PMOS transistor P1, and the first NMOS transistor N1 are turned on. When X=0, the potential of the first output terminal A of the preprocessing circuit 20 is high, indicating a pre-charge state. Furthermore, when the clock signal CK=1, the sampling circuit 10 satisfies X= The potential of node X is opposite to that of the input signal D. The third NMOS transistor N3 in the preprocessing circuit 20 is turned on. If the output terminal X of the sampling circuit 10 is 1, then the second output terminal B of the preprocessing circuit 20 is 0; if the output terminal X of the sampling circuit 10 is 0, then the first output terminal A of the preprocessing circuit 20 is 1. It can be seen that the input signal is transmitted from node X to the subsequent circuit, thus obtaining the value of the input signal. This process is called evaluation.

[0058] As mentioned above, the power consumption of the trigger circuit mainly includes three aspects: dynamic power consumption, short-circuit power consumption, and leakage power consumption. The preprocessing circuit with a non-full swing structure can effectively reduce dynamic power consumption. On this basis, the trigger circuit provided in this application embodiment can also effectively reduce short-circuit loss and leakage loss.

[0059] Specifically, based on the working process of the trigger circuit described above, it can be seen that during actual operation, different power devices in the preprocessing circuit may conduct simultaneously, thereby generating power (i.e., V). DD ) to the ground (i.e., V) SS This creates a direct path for the circuit, which in turn causes a short-circuit current.

[0060] The short-circuit current energy consumption of the preprocessing circuit during a single conduction state flip can be expressed as: (5) Among them, E SC Indicates short-circuit loss; t1 and t2 represent the time range during which the power devices in the preprocessing circuit are simultaneously turned on; I(t) represents the short-circuit current that varies with time.

[0061] exist Figure 2 In the trigger circuit provided in the illustrated embodiment, since the time during which the second PMOS transistor P2 and the second NMOS transistor N2 are simultaneously turned on is very short, the time during which the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are simultaneously turned on in this embodiment is shorter than the time during which the power devices in the preprocessing circuit are simultaneously turned on in the related art. Therefore, in the trigger circuit provided in this embodiment, the short-circuit loss of the preprocessing circuit during one turn-on and flip is less than the short-circuit loss of a single preprocessing circuit in the related art.

[0062] Furthermore, leakage current loss mainly refers to the power consumption that exists in the circuit when it is in a static state, which is the loss caused by static leakage current.

[0063] The leakage current of a power device can be expressed as (6) Among them, I off W represents the leakage current, L represents the effective channel width of the power device, and I represents the effective channel length of the power device. DS0 V represents the unit saturation current. T0 The threshold voltage of the power device is represented by S, which represents the slope coefficient, and the gate-source voltage V is the minimum required to reduce the drain current to one-tenth. GS How much should it be reduced? It represents thermoelectric potential.

[0064] Based on the above formula, it can be understood that if we want to reduce leakage current, we can use a stacking method to reduce subthreshold leakage current. The formula for the stacked leakage current can be expressed as: (7) Among them, V X This represents the drain-source voltage of the MOSFET.

[0065] The value of Vx is less than V. DD This reduces the subthreshold leakage current. Based on this, the preprocessing circuit provided in this embodiment stacks a total of 5 devices (first PMOS transistor P1, second PMOS transistor P2, first NMOS transistor N1, second NMOS transistor N2 and third NMOS transistor N3). Therefore, the subthreshold leakage current of the preprocessing circuit provided in this embodiment is less than the subthreshold leakage current of the preprocessing circuit in the related art.

[0066] In summary, the trigger circuit provided in this embodiment can effectively reduce the dynamic loss, short-circuit loss and leakage loss of the circuit, thereby comprehensively reducing the power consumption of the trigger circuit, and at the same time helping to reduce the overall loss of the integrated circuit.

[0067] This application also provides a clock gating circuit, see [link to relevant documentation] Figure 3 As shown, the clock gating circuit provided in this embodiment includes combinational logic circuitry and flip-flop circuitry as provided in any of the preceding embodiments, wherein, The clock input of the combinational logic circuit is connected to the clock input of the sampling circuit in the flip-flop circuit, and the signal input of the combinational logic circuit is connected to the output of the driving circuit in the flip-flop circuit, i.e., the output of the flip-flop circuit.

[0068] In practical applications, combinational logic circuits can be any of the following: AND gate, OR gate, NOT gate, etc. Of course, they can also be other types of logic circuits, which will not be listed here. As long as they do not exceed the core idea of ​​this application, they also fall within the scope of protection of this application.

[0069] In practical applications, clock gating circuits are important units in large-scale integrated circuits, used to reduce system power consumption. The clock gating circuit constructed based on the flip-flop circuit and combinational logic circuit provided in this application uses the enable signal of the clock gating circuit as the input signal. The output of the flip-flop circuit and the clock signal start or stop the operation of the system according to the logical relationship determined by AND, OR, NOT, etc. Especially in large-scale integrated circuits, the power consumption of the system can be reduced by clock gating circuits. By using the flip-flop circuit provided in this application to construct the clock gating circuit, the system power consumption can be reduced while ensuring fast signal transmission.

[0070] This application also provides a frequency divider circuit, see [link]. Figure 4 As shown, the frequency divider circuit provided in this embodiment includes: a sampling circuit, a preprocessing circuit, a sustaining circuit, and a driving circuit.

[0071] The sampling circuit is used to acquire the input signal. The preprocessing circuit is connected to the sampling circuit and outputs a low-level drive signal or a high-level drive signal in response to the input signal provided by the sampling circuit. The preprocessing circuit adopts a non-full-swing structure, and the voltage amplitude between its output high-level drive signal and low-level drive signal is less than the operating voltage amplitude of the trigger circuit. The holding circuit is connected to the preprocessing circuit and maintains the output unchanged in response to the low-level drive signal output by the preprocessing circuit, or outputs a load signal opposite to the input signal in response to the high-level drive signal output by the preprocessing circuit. The driving circuit is connected to the holding circuit and drives the subsequent load circuit in response to the output of the holding circuit. The holding circuit is also connected to the sampling circuit, and the signal output by the holding circuit is used as the input signal. The specific implementation of the sampling circuit, preprocessing circuit, holding circuit, and driving circuit can refer to the implementation method of the trigger circuit provided in the foregoing embodiments, and will not be repeated here.

[0072] Combination Figure 4 As shown, in the frequency divider circuit provided in this embodiment, since the output of the sustain circuit is opposite to the final output logic of the flip-flop circuit and also opposite to the output logic of the sampling circuit, connecting the output of the sustain circuit to the input of the sampling circuit can form a frequency divider circuit. Frequency divider circuits are widely used in large-scale integrated circuits. The power consumption and delay of the frequency divider will have a certain impact on large-scale circuits. Therefore, the frequency divider circuit constructed based on the flip-flop circuit topology provided in this application can realize fast and low-power frequency division processing, thereby reducing the power consumption of large-scale integrated circuits.

[0073] In practical applications, this divider circuit can be connected to the clock signal of the next stage divider circuit to form a cascaded divider circuit of multiple divider circuits, thereby achieving a higher division ratio.

[0074] This application also provides another frequency divider circuit, see [link to application]. Figure 5 As shown, the frequency divider circuit provided in this application embodiment includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first NAND gate circuit U1, and a second NAND gate circuit U2, wherein the first flip-flop circuit, the second flip-flop circuit, and the third flip-flop circuit respectively adopt the flip-flop circuit provided in any of the foregoing embodiments of this application.

[0075] Combination Figure 5 As shown, the output terminal (Q1) of the driving circuit in the first flip-flop circuit is connected to the input terminal (D2) of the sampling circuit in the second flip-flop circuit. The output terminal (Q2) of the driving circuit in the second flip-flop circuit is connected to the first input terminal of the first NAND gate circuit U1. The output terminal (Q2') of the holding circuit in the second flip-flop circuit is connected to the first input terminal of the second NAND gate circuit U2. The output terminal of the second NAND gate circuit U2 is connected to the input terminal (D3) of the sampling circuit in the third flip-flop circuit. The output terminal (Q3) of the driving circuit in the third flip-flop circuit is connected to the second input terminal of the first NAND gate circuit U1. The output terminal of the first NAND gate circuit U1 is connected to the input terminal (D1) of the sampling circuit in the first flip-flop circuit. The clock input terminals of the first, second, and third flip-flop circuits receive the same clock signal.

[0076] Based on the above connections, the first flip-flop circuit receives the input signal, the second flip-flop circuit transmits the signal when the clock signal is valid, and the second input of the second NAND gate U2 receives the control signal, which is used to adjust the division ratio of the frequency divider circuit. The specific adjustment process will be discussed later and will not be detailed here. The third flip-flop circuit outputs the signal to be divided when the clock signal is valid and drives the subsequent load circuit. The first NAND gate U1 combines the outputs of the third flip-flop circuit and the second flip-flop circuit to finally achieve the frequency division result.

[0077] Combination Figure 5 As shown, the frequency divider provided in this embodiment includes two frequency division modes. Specifically, when the control signal is high, it is in the five-way frequency division mode, and when the control signal is low, it is in the four-way frequency division mode. By switching the control signal, you can choose to perform four-way or five-way frequency division according to your needs.

[0078] Since the speed and power consumption of a multi-mode frequency divider are mainly determined by the trigger circuit, the trigger circuit provided in this application can effectively reduce the overall power consumption of the frequency divider, thereby realizing a fast and low-power multi-mode frequency divider circuit.

[0079] Furthermore, in practical applications, the frequency divider circuit provided in this embodiment can also be combined with the aforementioned... Figure 4 The frequency divider circuits provided in the illustrated embodiment are used in combination to achieve a higher frequency division ratio.

[0080] This application also provides an integrated circuit including at least one trigger circuit as provided in any of the foregoing embodiments of this application.

[0081] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0082] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0083] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0084] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A trigger circuit, characterized in that, include: A sampling circuit is used to acquire the input signal; The preprocessing circuit is connected to the sampling circuit and outputs a low-level drive signal or a high-level drive signal in response to the input signal. A sustaining circuit, connected to the preprocessing circuit, maintains the output unchanged in response to the high-level drive signal, or outputs a load signal opposite to the input signal in response to the low-level drive signal; A driving circuit, connected to the sustaining circuit, drives the subsequent load circuit in response to the output of the sustaining circuit; The preprocessing circuit adopts a non-full swing structure, and the voltage amplitude between the high-level drive signal and the low-level drive signal is less than the operating voltage amplitude of the trigger circuit.

2. The trigger circuit according to claim 1, characterized in that, The preprocessing circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein, The source of the first PMOS transistor is used to receive the operating voltage of the flip-flop circuit, the gate of the first PMOS transistor is used to receive the clock signal, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; The source of the third PMOS transistor is used to receive the operating voltage, the gate of the third PMOS transistor is used to receive the clock signal, and the drain of the third PMOS transistor is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is used to receive the clock signal, and the source of the third NMOS transistor is grounded. The gate of the second PMOS transistor and the gate of the second NMOS transistor are respectively connected to the output terminal of the adoption circuit; The connection point between the second PMOS transistor and the first NMOS transistor serves as the first output terminal of the preprocessing circuit. The connection point between the first NMOS transistor and the second NMOS transistor serves as the second output terminal of the preprocessing circuit.

3. The trigger circuit according to claim 2, characterized in that, The sustaining circuit includes: a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein, The source of the fourth PMOS transistor is used to receive the operating voltage, the gate of the fourth PMOS transistor is connected to the second output terminal of the preprocessing circuit, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is used to receive the clock signal, and the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the first output terminal of the preprocessing circuit, and the source of the fifth NMOS transistor is grounded.

4. The trigger circuit according to claim 1, characterized in that, The driving circuit includes: a fifth PMOS transistor and a sixth NMOS transistor, wherein, The source of the fifth PMOS transistor is used to receive the operating voltage of the trigger circuit, and the drain of the fifth PMOS transistor is connected to the drain of the sixth NMOS transistor. The source of the sixth NMOS transistor is grounded; The gate of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor, and the resulting connection point serves as the input terminal of the driving circuit. The connection point between the drain of the fifth PMOS transistor and the drain of the sixth NMOS transistor serves as the output terminal of the driving circuit.

5. The trigger circuit according to claim 1, characterized in that, The sampling circuit includes: a sixth PMOS transistor, a seventh PMOS transistor, and a seventh NMOS transistor, wherein... The source of the sixth PMOS transistor is used to receive the operating voltage of the trigger circuit, and the drain of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor. The gate of the seventh PMOS transistor serves as the clock input terminal of the sampling circuit, and the drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is grounded; The gate of the sixth PMOS transistor is connected to the gate of the seventh NMOS transistor, and the resulting connection point serves as the input terminal of the sampling circuit. The connection point between the seventh PMOS transistor and the seventh NMOS transistor serves as the output terminal of the sampling circuit.

6. A clock gating circuit, characterized in that, include: Combinational logic circuits and flip-flop circuits as described in any one of claims 1 to 5, wherein, The clock input terminal of the combinational logic circuit is connected to the clock input terminal of the sampling circuit in the flip-flop circuit; The signal input terminal of the combinational logic circuit is connected to the output terminal of the drive circuit in the flip-flop circuit.

7. The clock gating circuit according to claim 6, characterized in that, The combinational logic circuits include: AND gates, OR gates, and NOR gates.

8. A frequency divider circuit, characterized in that, include: A sampling circuit is used to acquire the input signal; The preprocessing circuit is connected to the sampling circuit and outputs a low-level drive signal or a high-level drive signal in response to the input signal. A sustaining circuit, connected to the preprocessing circuit, maintains the output unchanged in response to the high-level drive signal, or outputs a load signal opposite to the input signal in response to the low-level drive signal; A driving circuit, connected to the sustaining circuit, drives the subsequent load circuit in response to the output of the sustaining circuit; The sustaining circuit is also connected to the sampling circuit, and the signal output by the sustaining circuit serves as the input signal. The preprocessing circuit adopts a non-full swing structure, and the voltage amplitude between the high-level drive signal and the low-level drive signal is less than the operating voltage amplitude of the trigger circuit.

9. A frequency divider circuit, characterized in that, include: The circuits include a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first NAND gate circuit, and a second NAND gate circuit, wherein... The first flip-flop circuit, the second flip-flop circuit, and the third flip-flop circuit each employ a flip-flop circuit as described in any one of claims 1 to 5; The output terminal of the driving circuit in the first flip-flop circuit is connected to the input terminal of the sampling circuit in the second flip-flop circuit; The output of the driving circuit in the second flip-flop is connected to the first input of the first NAND gate circuit, and the output of the holding circuit in the second flip-flop is connected to the first input of the second NAND gate circuit. The output of the second NAND gate is connected to the input of the sampling circuit in the third flip-flop circuit; The output terminal of the driving circuit in the third flip-flop circuit is connected to the second input terminal of the first NAND gate circuit, and the output terminal of the first NAND gate circuit is connected to the input terminal of the sampling circuit in the first flip-flop circuit. The second input terminal of the second NAND gate is used to receive a control signal, which is used to adjust the division ratio of the frequency divider circuit.

10. An integrated circuit, characterized in that, It includes at least one trigger circuit as described in any one of claims 1 to 5.

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