A delay circuit based on double schmitt trigger inverters

Abstract

The utility model discloses a kind of delay circuit based on double schmitt trigger inverter, it is related to circuit technical field, comprising: main control chip, main control chip adopts double schmitt trigger inverter, main control chip has two inverters;One of the input end of inverter is connected with first capacitor charging and discharging circuit, two inverters are connected by second capacitor charging and discharging circuit, first capacitor charging and discharging circuit is composed of capacitor, resistance and output voltage, the input end of another inverter is connected with the output end of inverter of first capacitor charging and discharging circuit by second capacitor charging and discharging circuit;Output voltage is used to power supply for the inverter of input end connection first capacitor charging and discharging circuit, the output end of inverter of input end connection second capacitor charging and discharging circuit is used to output reset signal.The utility model circuit simple structure, small, low power consumption, reset signal high-low level switching time is short, meet the demand of actual production.

Description

Technical Field

[0001] This utility model relates to the field of circuit technology, specifically to a delay circuit based on a dual Schmitt trigger inverter. Background Technology

[0002] The reset signal allows the user to determine the system mode state of the circuit system, ensuring that the circuit starts working from the initial state after the user resets the circuit system, thereby improving system reliability.

[0003] However, many current timing control chips have complex peripheral circuit structures, occupy a large space on printed circuit boards (PCBs), or have inaccurate delay durations and poor anti-interference capabilities.

[0004] Therefore, how to provide a circuit system with more accurate delay duration is an important issue that the industry urgently needs to address. Utility Model Content

[0005] In view of this, the present invention provides a delay circuit based on dual Schmitt trigger inverters to solve the problems of complex circuit structure, inaccurate delay duration, and poor anti-interference capability in the prior art.

[0006] According to a first aspect, embodiments of the present invention provide a delay circuit based on dual Schmitt trigger inverters, comprising: The main control chip uses dual Schmitt trigger inverters and has two inverters. One inverter's input terminal is connected to a first capacitor charging / discharging circuit. The two inverters are connected via a second capacitor charging / discharging circuit. The first capacitor charging / discharging circuit consists of a capacitor, a resistor, and an output voltage. It is used to charge the capacitor to increase the voltage at the inverter's input terminal. The input terminal of the other inverter is connected to the output terminal of the inverter connected to the first capacitor charging / discharging circuit via the second capacitor charging / discharging circuit. The second capacitor charging / discharging circuit consists of a capacitor and a resistor. It is used to discharge the capacitor to decrease the voltage at the inverter's input terminal. The output voltage is used to power the inverter whose input is connected to the first capacitor charging and discharging circuit, and the output of the inverter whose input is connected to the second capacitor charging and discharging circuit is used to output a reset signal.

[0007] In conjunction with the first aspect, in the first embodiment of the first aspect, the main control chip has a first inverter and a second inverter. The input terminal of the first inverter is connected to a first capacitor charging and discharging circuit, and the input terminal of the second inverter and the output terminal of the first inverter are connected through the second capacitor charging and discharging circuit.

[0008] In conjunction with the first embodiment of the first aspect, in the second embodiment of the first aspect, the first capacitor charging and discharging circuit is composed of a first resistor R1, a first capacitor C1 and an output voltage.

[0009] In conjunction with the second embodiment of the first aspect, in the third embodiment of the first aspect, the input terminal of the first inverter is connected to the input voltage through the first resistor R1, the input terminal of the first inverter is grounded through the first capacitor C1, one end of the first resistor R1 is connected to the input voltage, the other end of the first resistor R1 is connected to the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0010] In conjunction with the third embodiment of the first aspect, in the fourth embodiment of the first aspect, when the output terminal outputs a positive level, the first capacitor is charged through the first capacitor charging and discharging circuit, causing the voltage at the input terminal of the first inverter to rise. When the voltage at the input terminal of the first inverter does not rise to the positive input threshold voltage of the first inverter, the output terminal of the first inverter outputs a high level; when the voltage at the input terminal of the first inverter rises to the positive input threshold voltage of the first inverter, the output terminal of the first inverter outputs a low level.

[0011] In conjunction with the first embodiment of the first aspect, in the fifth embodiment of the first aspect, the second capacitor charging and discharging circuit is composed of a second resistor R2 and a second capacitor C2.

[0012] In conjunction with the fifth embodiment of the first aspect, in the sixth embodiment of the first aspect, the output terminal of the first inverter is connected to the input terminal of the second inverter through the second resistor R2, the input terminal of the second inverter is grounded through the second capacitor R2, one end of the second resistor R2 is connected to the output terminal of the first inverter, the other end of the second resistor R2 is connected to the second capacitor C2, and the other end of the second capacitor C2 is grounded.

[0013] In conjunction with the sixth embodiment of the first aspect, in the seventh embodiment of the first aspect, when the voltage at the input terminal of the first inverter has not risen to the switching voltage of the first inverter, the output terminal of the first inverter outputs a high level. This high level charges the second capacitor through the second capacitor charging and discharging circuit, causing the voltage at the input terminal of the second inverter to rise and eventually stabilize at a high level. When the voltage at the input terminal of the first inverter rises to the positive input threshold voltage of the first inverter, the first inverter outputs a low level. This low level discharges the second capacitor through the second capacitor charging and discharging circuit, causing the voltage at the input terminal of the second inverter to gradually decrease. When the voltage at the input terminal of the second inverter has not fallen to the negative input threshold voltage of the second inverter, the output terminal of the second inverter outputs a low level. When the voltage at the input terminal of the second inverter falls to the negative input threshold voltage of the second inverter, the output terminal of the second inverter outputs a high level. In conjunction with the first aspect, in the eighth embodiment of the first aspect, the positive power supply pin of the main control chip is grounded through the third capacitor C3.

[0014] In conjunction with the first embodiment of the first aspect, in the ninth embodiment of the first aspect, the output terminal of the second inverter is grounded through the fourth capacitor C4.

[0015] This invention relates to a delay circuit based on dual Schmitt trigger inverters, designed for a DC-DC product requiring a delayed reset signal for one output signal. Utilizing the characteristics of dual Schmitt trigger inverters, and with a first capacitor charging / discharging circuit connected to the input of one inverter, the two inverters are connected via a second capacitor charging / discharging circuit. The first capacitor charging / discharging circuit consists of a capacitor, a resistor, and an output voltage. It charges the capacitor to increase the input voltage of the inverter. The input of the other inverter is connected to the output of the inverter with the first capacitor charging / discharging circuit connected to its input via the second capacitor charging / discharging circuit. The second capacitor charging / discharging circuit consists of a capacitor and a resistor. It discharges the capacitor to decrease the input voltage of the inverter. By setting the specific values ​​of the resistor and capacitor in the charging / discharging circuit, precise control of the reset signal delay duration is achieved. This circuit has a simple structure, is easy to debug, requires few components, occupies little space, has low power consumption, and the high / low level switching time of the reset signal is short, meeting the needs of actual production. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] in: Figure 1 The circuit diagram of the delay circuit based on the dual Schmitt trigger inverter provided by this utility model is shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0019] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] The reset signal allows the user to determine the system mode state of the circuit system, ensuring that the circuit starts working from the initial state after the user resets the circuit system, thereby improving system reliability.

[0022] However, many current timing control chips have complex peripheral circuit structures, occupy a large PCB space, or have inaccurate delay durations and poor anti-interference capabilities.

[0023] Therefore, how to provide a circuit system with more accurate delay duration is an important issue that the industry urgently needs to address.

[0024] To address the aforementioned problems, this specification provides a delay circuit based on a dual Schmitt trigger inverter. For example... Figure 1 As shown, the circuit includes: In this embodiment, the main control chip employs dual Schmitt trigger inverters. The main control chip has two inverters: a first inverter and a second inverter. Specifically, the main control chip has six pins: 1A, 1Y, GND, 2A, 2Y, and VCC. Pin 1A is the input pin of the first inverter, pin 1Y is the output pin of the first inverter, GND is grounded (0V), pin 2A is the input pin of the second inverter, pin 2Y is the output pin of the second inverter, and VCC is the positive power supply. These two inverters have Schmitt trigger characteristics and are completely independent, containing two threshold voltages (positive and negative input threshold voltages) for input signal shaping and noise suppression, and can be used independently.

[0025] In this embodiment, the input terminal of one inverter is connected to a first capacitor charging and discharging circuit, and the two inverters are connected through a second capacitor charging and discharging circuit. The first capacitor charging and discharging circuit consists of a capacitor, a resistor, and an output voltage. The first capacitor charging and discharging circuit is used to increase the voltage at the input terminal of the inverter by charging the capacitor. Specifically, the first capacitor charging and discharging circuit charges the corresponding capacitor, causing the voltage at the input terminal of the inverter to rise from 0, thereby generating a first delay time. At the same time, the voltage after the capacitor is fully charged will not be higher than the input voltage. The input terminal of the other inverter is connected to the output terminal of the inverter connected to the first capacitor charging and discharging circuit through the second capacitor charging and discharging circuit. The second capacitor charging and discharging circuit consists of a capacitor and a resistor. The second capacitor charging and discharging circuit is used to decrease the voltage at the input terminal of the inverter by discharging the corresponding capacitor. Specifically, the second capacitor charging and discharging circuit discharges the corresponding capacitor, causing the voltage at the input terminal of the inverter to drop, thereby generating a second delay time.

[0026] The output voltage powers the inverter whose input is connected to the first capacitor charging / discharging circuit, and the output of the inverter whose input is connected to the second capacitor charging / discharging circuit is used to output a reset signal. Specifically, the input of the first inverter is connected to a first capacitor charging / discharging circuit. The first resistor R1, the first capacitor C1, and the output voltage constitute this first capacitor charging / discharging circuit. Charging the first capacitor C1 increases the voltage at pin 1A of the main control chip. The input of the second inverter is connected to the output of the first inverter via a second capacitor charging / discharging circuit. The second resistor R2 and the second capacitor C2 constitute this second capacitor charging / discharging circuit. Discharging the second capacitor C2 decreases the voltage at pin 2A of the main control chip.

[0027] In this circuit, the input terminal of the first inverter is connected to the input voltage through a first resistor R1, and the input terminal of the first inverter is grounded through a first capacitor C1. One end of the first resistor R1 is connected to the input voltage, and the other end of the first resistor R1 is connected to the first capacitor C1, with the other end of the first capacitor C1 grounded. The output terminal of the first inverter is connected to the input terminal of the second inverter through a second resistor R2, and the input terminal of the second inverter is grounded through a second capacitor R2. One end of the second resistor R2 is connected to the output terminal of the first inverter, and the other end of the second resistor R2 is connected to the second capacitor C2, with the other end of the second capacitor C2 grounded.

[0028] The output voltage powers the main control chip. When the output terminal outputs a positive level, the first capacitor is charged through the first capacitor charging and discharging circuit, causing the voltage at pin 1A of the main control chip to rise. If the voltage at pin 1A does not rise to the positive input threshold voltage of the main control chip, pin 1Y of the main control chip outputs a high level. If the voltage at pin 1A rises to the positive input threshold voltage of the main control chip, pin 1Y of the main control chip outputs a low level. Similarly, the second resistor R2 and the second capacitor C2 also constitute a capacitor charging and discharging circuit, i.e., the second capacitor charging and discharging circuit. Pin 1Y of the main control chip is also connected to pin 2A of the main control chip through this capacitor charging and discharging circuit. If the voltage at pin 1A of the main control chip does not rise to the positive input threshold voltage of the main control chip, pin 1Y of the main control chip outputs a high level. This high level charges the second capacitor C2 through the capacitor charging and discharging circuit, causing the voltage at the input terminal of the second inverter to rise and eventually stabilize at a high level. When the voltage at pin 1A of the main control chip rises to the positive input threshold voltage of the main control chip, the pin 1Y of the main control chip outputs a low level. This low level discharges the second capacitor C2 through the capacitor charging and discharging circuit, causing the voltage at pin 2A of the main control chip to drop. When the voltage at pin 2A of the main control chip has not dropped to the negative input threshold voltage of the main control chip, the pin 2Y of the main control chip outputs a low level; when the voltage at pin 2A of the main control chip drops to the negative input threshold voltage of the main control chip, the pin 2Y of the main control chip outputs a high level. At this time, the delay duration of the reset signal output by the main control chip is set by adjusting the values ​​of the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2, according to the formula for capacitor charging time. The formula for capacitor charging and discharging time is:

[0029] in, express The capacitor voltage at time 1; Indicates the power supply voltage. Represents the time constant, and .

[0030] In this embodiment, the positive power supply pin of the main control chip is grounded through the third capacitor C3, and the output of the second inverter is grounded through the fourth capacitor C4. The third capacitor C3 and the fourth capacitor C4 filter the output signal and the reset signal, making the signal output from the main control chip more stable.

[0031] This invention relates to a delay circuit based on dual Schmitt trigger inverters, designed for a DC-DC product requiring a delayed reset signal for one output signal. Utilizing the characteristics of dual Schmitt trigger inverters, and with a first capacitor charging / discharging circuit connected to the input of one inverter, the two inverters are connected via a second capacitor charging / discharging circuit. The first capacitor charging / discharging circuit consists of a capacitor, a resistor, and an output voltage. It charges the capacitor to increase the input voltage of the inverter. The input of the other inverter is connected to the output of the inverter with the first capacitor charging / discharging circuit connected to its input via the second capacitor charging / discharging circuit. The second capacitor charging / discharging circuit consists of a capacitor and a resistor. It discharges the capacitor to decrease the input voltage of the inverter. By setting the specific values ​​of the resistor and capacitor in the charging / discharging circuit, precise control of the reset signal delay duration is achieved. This circuit has a simple structure, is easy to debug, requires few components, occupies little space, has low power consumption, and the high / low level switching time of the reset signal is short, meeting the needs of actual production.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A delay circuit based on dual Schmitt trigger inverters, characterized in that, include: The main control chip uses dual Schmitt trigger inverters and has two inverters. One inverter's input terminal is connected to a first capacitor charging / discharging circuit. The two inverters are connected via a second capacitor charging / discharging circuit. The first capacitor charging / discharging circuit consists of a capacitor, a resistor, and an output voltage. It is used to charge the capacitor to increase the voltage at the inverter's input terminal. The input terminal of the other inverter is connected to the output terminal of the inverter connected to the first capacitor charging / discharging circuit via the second capacitor charging / discharging circuit. The second capacitor charging / discharging circuit consists of a capacitor and a resistor. It is used to discharge the capacitor to decrease the voltage at the inverter's input terminal. The output voltage is used to power the inverter whose input is connected to the first capacitor charging and discharging circuit, and the output of the inverter whose input is connected to the second capacitor charging and discharging circuit is used to output a reset signal.

2. The delay circuit based on dual Schmitt trigger inverters according to claim 1, characterized in that, The main control chip has a first inverter and a second inverter. The input terminal of the first inverter is connected to a first capacitor charging and discharging circuit, and the input terminal of the second inverter and the output terminal of the first inverter are connected through the second capacitor charging and discharging circuit.

3. The delay circuit based on dual Schmitt trigger inverters according to claim 2, characterized in that, The first capacitor charging and discharging circuit consists of a first resistor R1, a first capacitor C1, and an output voltage.

4. The delay circuit based on dual Schmitt trigger inverters according to claim 3, characterized in that, The input terminal of the first inverter is connected to the input voltage through the first resistor R1. The input terminal of the first inverter is grounded through the first capacitor C1. One end of the first resistor R1 is connected to the input voltage, and the other end of the first resistor R1 is connected to the first capacitor C1. The other end of the first capacitor C1 is grounded.

5. The delay circuit based on dual Schmitt trigger inverters according to claim 4, characterized in that, When the output terminal outputs a positive level, the first capacitor is charged through the first capacitor charging and discharging circuit, causing the voltage at the input terminal of the first inverter to rise. When the voltage at the input terminal of the first inverter has not risen to the positive input threshold voltage of the first inverter, the output terminal of the first inverter outputs a high level; when the voltage at the input terminal of the first inverter rises to the positive input threshold voltage of the first inverter, the output terminal of the first inverter outputs a low level.

6. The delay circuit based on dual Schmitt trigger inverters according to claim 2, characterized in that, The second capacitor charging and discharging circuit consists of a second resistor R2 and a second capacitor C2.

7. The delay circuit based on dual Schmitt trigger inverters according to claim 6, characterized in that, The output of the first inverter is connected to the input of the second inverter through the second resistor R2. The input of the second inverter is grounded through the second capacitor R2. One end of the second resistor R2 is connected to the output of the first inverter, and the other end of the second resistor R2 is connected to the second capacitor C2. The other end of the second capacitor C2 is grounded.

8. The delay circuit based on dual Schmitt trigger inverters according to claim 7, characterized in that, When the voltage at the input terminal of the first inverter has not risen to the positive input threshold voltage of the first inverter, the output terminal of the first inverter outputs a high level. The high level will charge the second capacitor through the second capacitor charging and discharging circuit, causing the voltage at the input terminal of the second inverter to rise and finally stabilize at a high level. When the voltage at the input terminal of the first inverter rises to the positive input threshold voltage of the first inverter, the first inverter outputs a low level. The low level will discharge the second capacitor through the second capacitor charging and discharging circuit, causing the voltage at the input terminal of the second inverter to gradually decrease. When the voltage at the input terminal of the second inverter has not dropped to the negative input threshold voltage of the second inverter, the output terminal of the second inverter outputs a low level. When the voltage at the input terminal of the second inverter drops to the negative input threshold voltage of the second inverter, the output terminal of the second inverter outputs a high level.

9. The delay circuit based on dual Schmitt trigger inverters according to claim 1, characterized in that, The positive power supply pin of the main control chip is grounded through the third capacitor C3.

10. The delay circuit based on dual Schmitt trigger inverters according to claim 2, characterized in that, The output of the second inverter is grounded through the fourth capacitor C4.

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