A low power consumption circuit
Patent Information
- Application Number
- CN202522288805.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-29
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2035-10-29
AI Technical Summary
然而，此类方案在导通状态下，即便存在续流扰动，供电路径仍保持连接，这使得待机阶段的电流会随功率回路的波动而显著劣化，难以满足超低功耗要求
[0014]本实用新型实施例至少具有如下有益效果：一方面，通过低功耗控制模块中二极管D4与PMOS管Q11的配合，在待机阶段能切断续流扰动的传导路径，避免供电路径因续流连接导致的待机电流波动劣化，大幅降低待机功耗；另一方面，优化了隔离与供电拓扑，摆脱了隔离器件与负载共地的限制，结合三极管Q2对PMOS管栅极的精准控制，可将静态电流压低至纳安级，完全适配物联网传感节点、植入式医疗设备等长续航场景需求。同时，二极管D2与电阻的串联设计还能隔离按键信号干扰，进一步提升供电稳定性。
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Figure CN224804929U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to, but is not limited to, the field of microcontroller and circuit technology, and in particular to a low-power circuit. Background Technology
[0002] Existing low-power isolation circuits often use load switches or PMOS transistors to control power supply switching. However, in the on-state, even with freewheeling disturbances, the power supply path remains connected, causing the standby current to deteriorate significantly with power loop fluctuations, making it difficult to meet ultra-low power requirements. Furthermore, the architecture of existing solutions, where the isolation device shares a ground with the load, makes it difficult to reduce the quiescent current to the nanoamp level, making them unsuitable for long-endurance systems with stringent battery life requirements, such as IoT sensor nodes and implantable medical devices. Utility Model Content
[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims. This invention aims to at least solve one of the technical problems existing in the prior art. To this end, embodiments of this invention provide a low-power circuit capable of blocking freewheeling disturbances to optimize standby current, overcoming ground limitations to achieve nanoampere-level quiescent current, and isolating button interference to improve power supply stability.
[0004] This utility model embodiment provides a low-power circuit, including a key input module, a battery input module, a power conversion module, and a low-power control module. The output terminal of the battery input module is connected to the input terminal of the power conversion module, and the output terminal of the power conversion module is connected to the power input terminals of both the low-power control module and the key input module. The signal output terminal of the key input module is connected to the signal input terminal of the low-power control module. The low-power control module includes a diode D2, a transistor Q2, a PMOS transistor Q11, and a diode D4. The input terminal of diode D2 is connected to the signal output terminal of the key input module, and a resistor R25 is connected in series between the output terminal and the base of transistor Q2. The collector of transistor Q2 is connected to the gate of PMOS transistor Q11, and its emitter is grounded. The source of PMOS transistor Q11 is connected to the output terminal of the low-power control module, and its drain is connected to the input terminal of the power conversion module. The input terminal of diode D4 is connected to the output terminal of the power conversion module.
[0005] According to some embodiments of the present invention, the gate of the PMOS transistor Q11 is connected to the output terminal of the low-power control module through series resistors R24 and R25.
[0006] According to some embodiments of the present invention, a resistor R25 is connected in series between the base of the transistor Q2 and the output terminal of the diode D2, and the resistor R25 is used to limit the current flowing into the base of the transistor Q2.
[0007] According to some embodiments of the present invention, the gate-source on-state voltage of the PMOS transistor Q11 is -0.7V. When the absolute value of the gate-source voltage is greater than 0.7V, the PMOS transistor Q11 is turned on; when the absolute value of the gate-source voltage is less than 0.7V, the PMOS transistor Q11 is turned off.
[0008] According to some embodiments of this utility model, the diode D2 is a unidirectional diode, used to block the signal from the key input module from flowing back into the output terminal of the power conversion module.
[0009] According to some embodiments of this utility model, the diode D4 is a unidirectional diode used to block the reverse flow of current from the power supply terminal into the power conversion module.
[0010] According to some embodiments of the present invention, the low-power control module further includes a control signal access terminal, which is connected to the base of the transistor Q2 through a resistor R32, and is used to receive an externally input low-power switching signal.
[0011] According to some embodiments of this utility model, when the control signal input terminal is low, the transistor Q2 is turned on; when the control signal input terminal is high or in a high impedance state, the gate of the PMOS transistor Q11 is pulled up.
[0012] According to some embodiments of the present invention, the key input module includes a mechanical key. When the mechanical key is pressed, the key input module outputs a high-level trigger signal to the low-power control module. When the mechanical key is released, the trigger signal is interrupted, and the transistor Q2 is turned off.
[0013] According to some embodiments of this utility model, when the mechanical button is pressed for a first time and then released, the transistor Q2 is turned off, the gate voltage of the PMOS transistor Q11 rises, the PMOS transistor Q11 is turned off, and the power supply terminal stops outputting; when the mechanical button is pressed for a second time, an externally input low-power switching signal triggers the PMOS transistor Q11 to lock and conduct.
[0014] This utility model embodiment has at least the following beneficial effects: On the one hand, through the cooperation of diode D4 and PMOS transistor Q11 in the low-power control module, the conduction path of freewheeling disturbance can be cut off during the standby stage, avoiding the degradation of standby current fluctuation caused by freewheeling connection in the power supply path, and significantly reducing standby power consumption; on the other hand, the isolation and power supply topology are optimized, eliminating the limitation of isolation devices and load sharing a common ground. Combined with the precise control of the PMOS transistor gate by transistor Q2, the static current can be reduced to the nanoampere level, fully adapting to the long-endurance requirements of IoT sensor nodes, implantable medical devices, and other scenarios. At the same time, the series design of diode D2 and resistor can also isolate button signal interference, further improving power supply stability.
[0015] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description
[0016] The accompanying drawings are provided to further understand the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain the technical solution of this utility model, and do not constitute a limitation on the technical solution of this utility model.
[0017] Figure 1 This is a schematic diagram of a key input module circuit provided in one embodiment of the present invention; Figure 2 This is a schematic diagram of a battery input module circuit provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of a power conversion module circuit provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of a low-power control module circuit provided in one embodiment of the present invention. Detailed Implementation
[0018] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.
[0019] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0020] In the description of this utility model, the use of "first" and "second" is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features or the order of the technical features.
[0021] In the description of this utility model, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.
[0022] The embodiments of this utility model will be further described below with reference to the accompanying drawings.
[0023] See Figure 1-4 The circuit comprises a keypad input module, a battery input module, a power conversion module, and a low-power control module. The specific connections between the modules are as follows: the output terminal of the battery input module (BAT-I, voltage range 3.7 to 4.2V) is connected to the input terminal of the power conversion module; the output terminal of the power conversion module outputs 3.3V (VCC_3.3V), which is connected to the power input terminals of both the low-power control module and the keypad input module; the signal output terminal of the keypad input module is connected to the signal input terminal of the low-power control module.
[0024] The low-power control module includes diode D2, transistor Q2, PMOS transistor Q11, and diode D4. The input terminal of diode D2 is connected to the signal output terminal of the key input module, and a resistor R25 is connected in series between the output terminal and the base of transistor Q2. The collector of transistor Q2 is connected to the gate of PMOS transistor Q11, and the emitter is grounded. The source of PMOS transistor Q11 is connected to the output terminal (BAT-O) of the low-power control module, and the drain is connected to the input terminal (BAT-O) of the power conversion module. The input terminal of diode D4 is connected to the output terminal (3.3V) of the power conversion module.
[0025] In one feasible embodiment, the gate of PMOS transistor Q11 is connected to the output terminal (BAT-O) of the low-power control module through series resistors R24 and R25, which are used to pull up the gate voltage of PMOS transistor Q11 to the BAT-O voltage.
[0026] In one feasible embodiment, a resistor R25 is connected in series between the base of transistor Q2 and the output terminal of diode D2. The resistor R25 is used to limit the current flowing into the base of transistor Q2.
[0027] In one feasible embodiment, the gate-source on-state voltage Vgs(th) of the PMOS transistor Q11 is -0.7V (typical value). When the absolute value of the gate-source voltage Vgs is greater than 0.7V, the PMOS transistor Q11 is turned on; when the absolute value of the gate-source voltage Vgs is less than 0.7V, the PMOS transistor Q11 is turned off.
[0028] In one feasible embodiment, diode D2 is a unidirectional diode used to block the reverse flow of signals from the key input module into the output of the power conversion module, and to isolate the voltage spikes generated by key operation from interfering with the 3.3V main power supply.
[0029] In one feasible embodiment, diode D4 is a unidirectional diode used to block the reverse flow of current from the power supply terminal into the power conversion module, thereby cutting off the reverse backflow path from the main power supply to the low-power control module.
[0030] In one feasible embodiment, the low-power control module further includes a control signal input terminal (low-power switching terminal), which is connected to the base of transistor Q2 through resistor R32 and is used to receive an externally input low-power switching signal.
[0031] In one feasible embodiment, when the control signal input terminal is low, transistor Q2 is turned on, thereby pulling the gate of PMOS transistor Q11 low; when the control signal input terminal is high or in a high impedance state, the gate of PMOS transistor Q11 is pulled up to the BAT-O voltage by resistors R24 and R25.
[0032] In one feasible embodiment, the key input module includes a mechanical key. When the mechanical key is pressed, the key input module outputs a high-level trigger signal to the low-power control module. When the mechanical key is released, the trigger signal is interrupted, and the transistor Q2 is turned off.
[0033] In one feasible embodiment, when the mechanical button is pressed for a first time (less than 3 seconds) and then released, transistor Q2 is turned off, the gate voltage of PMOS transistor Q11 rises, PMOS transistor Q11 is turned off, and the power supply terminal (VCC_3.3V) stops outputting. When the mechanical button is pressed for a second time (lasting 3 seconds), the externally input low-power switching signal triggers PMOS transistor Q11 to lock on. At this time, even if the button is released, PMOS transistor Q11 remains on because its gate remains low, and it continues to receive 3.3V power. If the button is pressed again for 3 seconds while locked, the externally input low-power switching signal becomes high (or high impedance), the gate of PMOS transistor Q11 is pulled up to the BAT-O voltage, the gate-source voltage Vgs≈0, PMOS transistor Q11 is turned off, and the power supply terminal (VCC_3.3V) stops outputting.
[0034] The above is a detailed description of the preferred embodiments of the present utility model. However, the present utility model is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present utility model. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present utility model.
Claims
1. A low-power circuit, characterized in that, The system includes a button input module, a battery input module, a power conversion module, and a low-power control module. The output terminal of the battery input module is connected to the input terminal of the power conversion module, and the output terminal of the power conversion module is connected to the power input terminals of both the low-power control module and the button input module. The signal output terminal of the button input module is connected to the signal input terminal of the low-power control module. The low-power control module includes a diode D2, a transistor Q2, a PMOS transistor Q11, and a diode D4. The input terminal of diode D2 is connected to the signal output terminal of the button input module, and a resistor R25 is connected in series between the output terminal and the base of transistor Q2. The collector of transistor Q2 is connected to the gate of PMOS transistor Q11, and its emitter is grounded. The source of PMOS transistor Q11 is connected to the output terminal of the low-power control module, and its drain is connected to the input terminal of the power conversion module. The input terminal of diode D4 is connected to the output terminal of the power conversion module.
2. The circuit according to claim 1, characterized in that, The gate of the PMOS transistor Q11 is connected to the output of the low-power control module through series resistors R24 and R25.
3. The circuit according to claim 1, characterized in that, A resistor R25 is connected in series between the base of transistor Q2 and the output terminal of diode D2. The resistor R25 is used to limit the current flowing into the base of transistor Q2.
4. The circuit according to claim 1, characterized in that, The gate-source on-state voltage of the PMOS transistor Q11 is -0.7V. When the absolute value of the gate-source voltage is greater than 0.7V, the PMOS transistor Q11 is turned on; when the absolute value of the gate-source voltage is less than 0.7V, the PMOS transistor Q11 is turned off.
5. The circuit according to claim 1, characterized in that, The diode D2 is a unidirectional diode, used to block the signal from the key input module from flowing back into the output terminal of the power conversion module.
6. The circuit according to claim 1, characterized in that, The diode D4 is a unidirectional diode, used to block the reverse flow of current from the power supply terminal into the power conversion module.
7. The circuit according to claim 1, characterized in that, The low-power control module also includes a control signal input terminal, which is connected to the base of the transistor Q2 through a resistor R32, and is used to receive externally input low-power switching signals.
8. The circuit according to claim 7, characterized in that, When the control signal input terminal is low, the transistor Q2 is turned on; when the control signal input terminal is high or in a high impedance state, the gate of the PMOS transistor Q11 is pulled up.
9. The circuit according to claim 1, characterized in that, The key input module includes a mechanical key. When the mechanical key is pressed, the key input module outputs a high-level trigger signal to the low-power control module. When the mechanical key is released, the trigger signal is interrupted, and the transistor Q2 is turned off.
10. The circuit according to claim 9, characterized in that, When the mechanical button is pressed for a first time and then released, the transistor Q2 is turned off, the gate voltage of the PMOS transistor Q11 rises back, the PMOS transistor Q11 is turned off, and the power supply stops outputting; when the mechanical button is pressed for a second time, the externally input low-power switching signal triggers the PMOS transistor Q11 to lock and conduct.