A digital-to-analog converter resolution enhancement circuit

Abstract

The utility model discloses a kind of DAC resolution enhancement circuits.It includes buffer, for receiving reference voltage signal;Trapezoidal resistance network, with buffer connection, for the reference voltage signal after buffering is gradually voltage division;Digital-to-analog converter, with the last stage output end of trapezoidal resistance network connection, for receiving last stage voltage signal;I / V converter, with the output end of each stage of trapezoidal resistance network and digital-to-analog converter respectively connection, for the current signal of the output of each stage of trapezoidal resistance network with the current signal of the output of digital-to-analog converter is synthesized, and is converted into voltage signal output.The utility model utilizes trapezoidal resistance network to scale reference voltage signal, and adopts I / V converter to carry out current synthesis, to select discrete high-precision resistor, while enhancing the stability and noise performance of output voltage signal of DAC resolution, and its linearity and accuracy are promoted by further calibration operation.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically a resolution enhancement circuit for a digital-to-analog converter. Background Technology

[0002] Digital-to-analog converters (DACs) are key interface circuits connecting the digital and analog domains. With the continuous advancement of semiconductor technology, various electronic systems have placed higher demands on the performance indicators of DACs, such as resolution, in order to achieve lower quantization noise, higher signal-to-noise ratio, and more refined signal output capabilities.

[0003] The main approaches to achieving high-resolution DACs include: First, directly adopting a high-resolution design, such as by selecting a higher bit-count DAC device. However, due to limitations in integrated circuit manufacturing processes, mismatches in the parameters of key components within the chip can introduce static errors such as nonlinearity. Therefore, the resolution of integrated DAC devices is generally limited to no more than 20 bits. Second, employing dual DACs and a proportional adder technique, scaling the output of one of the DACs and then using an adder to synthesize the results to obtain high resolution. This technique can achieve a resolution improvement at a low cost. Its drawback is that the static performance of the main DAC (including nonlinearity, stability, and noise) determines and limits most of the performance of the synthesized signal, making it difficult to improve performance beyond resolution.

[0004] Therefore, while enhancing DAC resolution, how to further improve its overall accuracy indicators, including nonlinearity, stability, and noise performance, has become a key issue that urgently needs to be addressed. Utility Model Content

[0005] This invention addresses the shortcomings of existing technologies by proposing a resolution enhancement circuit for digital-to-analog converters.

[0006] This utility model includes:

[0007] A buffer is used to receive a reference voltage signal and output a buffered reference voltage signal.

[0008] A trapezoidal resistor network, connected to the buffer, is used to divide the buffered reference voltage signal step by step to generate a multi-stage progressively decreasing voltage signal.

[0009] A digital-to-analog converter is connected to the final output of the trapezoidal resistor network to receive the final voltage signal and output a corresponding analog voltage signal.

[0010] An I / V converter is connected to the output terminals of each stage of the trapezoidal resistor network and the output terminal of the digital-to-analog converter, respectively, and is used to combine the current signals output from each stage of the trapezoidal resistor network and the current signals output from the digital-to-analog converter, and convert them into voltage signals for output.

[0011] The trapezoidal resistor network adopts an R-2R structure, and each stage of the network has the same structure. The number of stages of the trapezoidal resistor network is determined according to the required resolution improvement factor, so as to enhance the resolution of the digital-to-analog converter.

[0012] Furthermore, the buffer is a unity-gain amplifier with high input impedance and low output impedance, used to isolate the load effect of the trapezoidal resistor network on the reference voltage signal.

[0013] Furthermore, except for the final stage, each stage of the trapezoidal resistor network contains a pair of resistors with a resistance ratio of 1:2, forming an R-2R structure to achieve binary weighted voltage division.

[0014] Furthermore, in each stage, the resistor with a relatively smaller resistance value is connected in series to the next stage resistor network, while the resistor with a relatively larger resistance value is connected to the input terminal of the resistor network of that stage and connected to the input terminal of the I / V converter or to common ground through a single-pole double-throw switch.

[0015] Furthermore, the single-pole double-throw switch is a single-pole double-throw magnetic latching relay.

[0016] Furthermore, the number of stages n in the trapezoidal resistor network is related to the resolution enhancement factor 2. n Correspondingly, n is a positive integer.

[0017] Furthermore, the digital-to-analog converter is an m-bit multiplication type digital-to-analog converter, and its reference voltage input terminal is connected to the final output node of the trapezoidal resistor network.

[0018] Furthermore, the I / V converter consists of an operational amplifier and a feedback resistor, used to superimpose the currents at each stage with binary weights and convert them into a single-ended voltage output.

[0019] Furthermore, the inverting input of the operational amplifier in the I / V converter serves as the input of the I / V converter and is connected to the ladder resistor network and the first resistor at the output of the digital-to-analog converter; the non-inverting input of the operational amplifier is connected to common ground; and a feedback resistor is connected between the inverting input and the output of the operational amplifier.

[0020] Furthermore, the resistors in the trapezoidal resistor network are low-temperature drift, high-precision metal foil resistors.

[0021] The beneficial effects of this invention are as follows: This invention uses a trapezoidal resistor network composed of resistors to scale the reference voltage signal and uses an I / V converter to synthesize the current, thereby allowing the selection of discrete high-precision resistors. This enhances the DAC resolution while improving the stability and noise performance of the output voltage signal, and further improves its linearity and accuracy through calibration. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a resolution enhancement circuit for a digital-to-analog converter.

[0023] Figure 2 This is a schematic diagram of an implementation of a resolution enhancement circuit for a digital-to-analog converter. Detailed Implementation

[0024] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0025] like Figure 1 As shown, the digital-to-analog converter resolution enhancement circuit provided in this embodiment includes a buffer, a ladder resistor network, a digital-to-analog converter, an I / V converter, and a control unit.

[0026] The input terminal of the buffer is connected to a reference voltage signal, and the output terminal is connected to the input terminal of a trapezoidal resistor network.

[0027] The voltage divider node at the end of the trapezoidal resistor network is connected to the reference input terminal of the digital-to-analog converter, and each shunt branch of the trapezoidal resistor network is connected to the input terminal of the I / V converter or to a common ground via a single-pole double-throw switch.

[0028] The output terminal of the digital-to-analog converter is connected in series with a first resistor and then connected to the input terminal of the I / V converter.

[0029] The controller is connected to the control terminal of the single-pole double-throw switch in the trapezoidal resistor network via a digital bus, and the controller is also connected to the control terminal of the digital-to-analog converter via a digital bus.

[0030] The I / V converter outputs an analog voltage signal.

[0031] The input and output interfaces of this circuit are similar to those of a conventional integrated DAC chip. The reference voltage signal enters a ladder resistor network via a buffer. This buffer is a unity-gain amplifier with high input impedance and low output impedance to prevent the subsequent resistor network from generating a load effect on the reference voltage signal, thereby affecting the accuracy of the reference voltage signal.

[0032] Furthermore, in the ladder resistor network, except for the final stage, the circuit structure of each stage is the same, which is an R-2R structure, specifically including:

[0033] A resistor connected in series to the next stage resistor network and configured with the first resistance value;

[0034] A resistor shunt branch, configured to be twice the value of the first resistance, is connected to the input of the resistor network at this stage. This resistor shunt branch is connected to the input of the I / V converter or to a common ground via a single-pole double-throw switch.

[0035] In a preferred embodiment, the final stage of the trapezoidal resistor network is connected to a second resistor, the resistance value of which is configured to be the first resistance value.

[0036] In a preferred embodiment, the single-pole double-throw switch in the trapezoidal resistor network can specifically be a single-pole double-throw magnetic latching relay or an analog switch.

[0037] In a preferred embodiment, the resistance value of the first resistor connected in series at the output terminal of the digital-to-analog converter is configured as a first resistance value.

[0038] The number of stages in the trapezoidal resistor network used in this circuit can be determined based on the required resolution improvement factor. If the number of binary bits to be improved is n, then the required number of stages in the trapezoidal resistor network is n (excluding the last stage).

[0039] For example, if you need to increase the resolution by 2 3 =8 times, then it is necessary to Figure 2 The three-stage trapezoidal resistor network shown has an output reference voltage signal amplitude of V. R Then, in the i-th level network, the output node voltage V connected to the next level network is... i for

[0040]

[0041] but Figure 2 The voltage value output from stage 3 to the digital-to-analog converter is:

[0042]

[0043] Figure 2 In the illustrated embodiment, the digital-to-analog converter used is an m-bit multiplication digital-to-analog converter (MDAC), so its output voltage resolution is...

[0044]

[0045] It can be seen that the resolution of the output voltage signal of this circuit is improved by approximately 2 compared to the original MDAC. 3 =8 times.

[0046] The voltage output range of this embodiment will now be described.

[0047] In a trapezoidal resistive network, the current value of the shunt branch in the i-th stage of the network is...

[0048]

[0049] Therefore, the three-stage ladder resistor network can inject current values ​​into the I / V converter respectively. , , .

[0050] In the MDAC, the output voltage corresponding to the most significant bit is formed across the second resistor, while the current injected by the I / V converter is... It can be seen that the current generated by the MDAC and the preceding ladder resistor network strictly follows a binary relationship, that is, the current at each stage proceeds in 2... i The weight allocation. In this circuit structure, the network resistor values ​​in the MDAC do not need to match the resistor values ​​in the external ladder resistor network, thus demonstrating the strong applicability of this embodiment. Furthermore, Figure 1 The digital-to-analog converter shown does not have to be an MDAC; it can also be other types of DACs with a matching reference voltage input range.

[0051] exist Figure 2 In the illustrated embodiment, an operational amplifier and a feedback resistor (third resistor) are selected to construct an I / V converter. The inverting input terminal of the operational amplifier serves as the input terminal of the I / V converter and is connected to the ladder resistor network and the first resistor. The non-inverting input terminal of the operational amplifier is connected to a common ground. A third resistor is connected between the inverting input terminal and the output terminal of the operational amplifier. Therefore, the maximum voltage that can be output at the I / V converter output terminal is:

[0052]

[0053] This output range is consistent with the output range of the MDAC driven directly using VR as the reference voltage.

[0054] exist Figure 2 In the circuit shown, the accuracy metrics (such as nonlinearity, temperature drift, and noise) of the original digital-to-analog converter (MDAC) are attenuated by a factor of 8 in the total output. If all resistors with values ​​of R and 2R in the circuit were made of low-temperature-drift, high-precision metal foil resistors, then the main static performance metrics of the circuit would be determined by the performance of these resistors. Generally speaking, the performance of these resistors can improve the accuracy metrics (such as nonlinearity, temperature drift, and noise) of the DAC by more than an order of magnitude.

[0055] The specific embodiments described herein are merely illustrative examples illustrating the spirit of this utility model. Those skilled in the art to which this utility model pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of this utility model or exceeding the scope defined by the appended claims.

Claims

1. A resolution enhancement circuit for a digital-to-analog converter, characterized in that, include: A buffer is used to receive a reference voltage signal and output a buffered reference voltage signal. A trapezoidal resistor network, connected to the buffer, is used to divide the buffered reference voltage signal step by step to generate a multi-stage progressively decreasing voltage signal. A digital-to-analog converter is connected to the final output of the trapezoidal resistor network to receive the final voltage signal and output the corresponding analog voltage signal. An I / V converter is connected to the output terminals of each stage of the trapezoidal resistor network and the output terminal of the digital-to-analog converter, respectively, and is used to combine the current signals output from each stage of the trapezoidal resistor network and the current signals output from the digital-to-analog converter, and convert them into voltage signals for output. The trapezoidal resistor network adopts an R-2R structure, and each stage of the network has the same structure. The number of stages of the trapezoidal resistor network is determined according to the required resolution improvement factor, so as to enhance the resolution of the digital-to-analog converter.

2. The digital-to-analog converter resolution enhancement circuit according to claim 1, characterized in that, The buffer is a unity-gain amplifier with high input impedance and low output impedance, used to isolate the load effect of the trapezoidal resistor network on the reference voltage signal.

3. A digital-to-analog converter resolution enhancement circuit according to claim 1 or 2, characterized in that, Except for the final stage, each stage of the trapezoidal resistor network contains a pair of resistors with a resistance ratio of 1:2, forming an R-2R structure to achieve binary weighted voltage division.

4. The digital-to-analog converter resolution enhancement circuit according to claim 3, characterized in that, The resistors with relatively smaller resistance values ​​in each stage are connected in series to the next stage resistor network, while the resistors with relatively larger resistance values ​​are connected to the input terminal of the resistor network at that stage and connected to the input terminal of the I / V converter or to common ground through a single-pole double-throw switch.

5. The digital-to-analog converter resolution enhancement circuit according to claim 4, characterized in that, The single-pole double-throw switch is a single-pole double-throw magnetic latching relay.

6. The digital-to-analog converter resolution enhancement circuit according to claim 3, characterized in that, The number of stages n in the trapezoidal resistor network and the resolution improvement factor 2 n Correspondingly, n is a positive integer.

7. The digital-to-analog converter resolution enhancement circuit according to claim 1, characterized in that, The digital-to-analog converter is an m-bit multiplication type digital-to-analog converter, and its reference voltage input terminal is connected to the final output node of the trapezoidal resistor network.

8. A digital-to-analog converter resolution enhancement circuit according to claim 1 or 7, characterized in that, The I / V converter consists of an operational amplifier and a feedback resistor, and is used to superimpose the currents at each stage according to binary weights and convert them into a single-ended voltage output.

9. A digital-to-analog converter resolution enhancement circuit according to claim 8, characterized in that, The inverting input of the operational amplifier in the I / V converter serves as the input of the I / V converter and is connected to the trapezoidal resistor network and the first resistor at the output of the digital-to-analog converter; the non-inverting input of the operational amplifier is connected to the common ground; and a feedback resistor is connected between the inverting input and the output of the operational amplifier.

10. A digital-to-analog converter resolution enhancement circuit according to claim 1, characterized in that, The resistors in the trapezoidal resistor network are low-temperature drift, high-precision metal foil resistors.

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