Node device and communication system

Abstract

The application discloses a node device and a communication system. The node device is applied to a multi-node communication system and comprises a data recovery circuit, a cache circuit, a read instruction generation circuit and a data processing circuit. The data recovery circuit is used for receiving input data provided by an upstream node and recovering the input data into frame data and a write instruction. The cache circuit is connected with the data recovery circuit and is used for caching the frame data according to a valid write instruction and outputting the frame data according to a valid read instruction. The read instruction generation circuit is connected between the data recovery circuit and the cache circuit and is used for providing the read instruction. The data processing circuit is connected with the cache circuit and is used for providing output data to a downstream node according to the read frame data. The read instruction generation circuit provides the valid read instruction when the write instruction is received and a first count value of a local clock reaches a reference value. The delay fluctuation of each node can be eliminated, and the step-by-step accumulation of the delay can be avoided.

Description

Technical Field

[0001] This utility model relates to the field of information technology, and in particular to a node device and a communication system. Background Technology

[0002] In serial communication systems, such as 100 Mbps time-division duplex systems for high-speed wired media transmission in vehicles and daisy-chain networking systems, there are usually master nodes and multiple slave nodes cascaded in sequence with the master node.

[0003] Figure 1 The diagram illustrates the transmission of downlink frames in a communication system, and... Figure 1 The example uses nodes 1 through n as slave nodes. The master node is controlled by a host computer and sends initial downlink frames to downstream slave nodes at a fixed clock frequency in the system clock domain. Each slave node receives downlink frames (i.e., input data of its own level) from its upstream node and provides processed downlink frames (i.e., output data of its own level) to its downstream nodes. Specifically, after receiving the synchronization field of the downlink frame, the synchronization header position is restored to synchronize the local clock domain and the system clock domain; after receiving the data field of the downlink frame, data processing is performed, and after a processing delay, the processed downlink frames are sent to downstream nodes. This process continues until the last slave node is reached.

[0004] However, the processing delays of different slave nodes are not the same, and the fluctuations in processing delay accumulate at each slave node. For example, suppose the processing delay of node 1 is Td, and the processing delays of nodes 2 through n are all Td + Δt. Then node 3 will have a processing delay fluctuation of 2Δt, and so on, with node n having a processing delay fluctuation of n-1 times Δt. As the number of cascaded nodes increases, the accumulated processing delay fluctuations also increase. Ultimately, this leads to the slave nodes being unable to achieve clock synchronization, affecting the stability and reliability of the communication system. In existing technologies, the above phenomenon is avoided by reducing the number of cascaded slave nodes, but this limits the application scenarios of the communication system. Utility Model Content

[0005] In view of the above problems, the purpose of this application is to provide a node device and a communication system that can improve the fluctuation of processing latency of each node device, thereby improving the stability and reliability of the communication system.

[0006] According to one aspect of this application, a node device is provided, characterized in that the node device is applied to a multi-node communication system, the node device comprising: a data recovery circuit for receiving input data from the local node device and recovering it into frame data and a write instruction; a buffer circuit connected to the data recovery circuit for buffering the frame data according to a valid write instruction and outputting the frame data according to a valid read instruction; a read instruction generation circuit connected between the data recovery circuit and the buffer circuit for providing the read instruction; and a data processing circuit connected to the buffer circuit for processing the read frame data and providing output data from the local node device, wherein the read instruction generation circuit provides the valid read instruction when it receives the write instruction and a first count value of the local clock reaches a reference value.

[0007] Optionally, the read instruction generation circuit includes: a first instruction generation unit, wherein a valid write instruction enables the first instruction generation unit to generate a first instruction based on the first count value of the local clock; a second instruction generation unit, configured to synchronize the write instruction from the system clock domain to the local clock domain to generate a second instruction; and a selector, configured to output the first instruction as the read instruction based on a first-level selection signal, or output the second instruction as the read instruction based on a second-level selection signal.

[0008] Optionally, the first instruction generation unit includes: a first counter for acquiring the first count value of the local clock, the first count value being reset according to a valid write instruction; and a first comparator for comparing the first count value with the reference value, and providing a valid first instruction when the first count value is greater than or equal to the reference value.

[0009] Optionally, the first instruction generation unit further includes a reference value generation module for providing the reference value. The reference value generation module includes: a second counter for acquiring a second count value from a local clock, the second count value representing the time interval between a valid write instruction and a valid second instruction; a storage submodule connected to the second counter for storing the second count value; and a data processing submodule for detecting the second count value stored in the storage submodule, and providing the reference value when the storage submodule continuously stores a first number of second count values, and the first number of second count values ​​all fall within a first range, the reference value being the maximum / minimum / mean / mode / median of the first number of second count values.

[0010] Optionally, the data processing submodule is further configured to provide an end signal when providing the reference value, and the read instruction generation circuit further includes a selection signal generation unit for generating the selection signal, wherein the selection signal jumps to the first level when the signal generation unit receives the end signal.

[0011] Optionally, the read instruction generation circuit further includes a selection signal generation unit for generating the selection signal. The selection signal generation unit includes: a phase comparison module, which compares the second instruction and the first instruction corresponding to each of the input data for a plurality of consecutive input data and provides the phase difference between them; and a statistics module, which counts the phase differences of the plurality of consecutive input data and provides the selection signal based on the statistical results of the phase differences. The statistics module provides a first level of the selection signal when it continuously receives a second number of phase differences and all of the second number of phase differences fall within a second range, and otherwise provides a second level of the selection signal.

[0012] Optionally, the phase comparison module includes: a first edge detection submodule, for detecting the effective edge of the second instruction and the effective edge of the first instruction for each input data; and a third counter, for acquiring a third count value of the local clock, the third count value representing the phase difference between the effective edge of the first instruction and the effective edge of the second instruction.

[0013] Optionally, the phase comparison module further includes a position comparison submodule, configured to provide a first comparison result when the valid edge of the first instruction comes first, and otherwise provide a second comparison result.

[0014] Optionally, the statistics module includes: a second comparator for providing a comparison result between the third count value and the second range; and a fourth counter for providing a fourth count value; a third comparator for comparing the fourth count value and the second quantity to provide a first level of the selection signal when the fourth count value is greater than or equal to the second quantity, and otherwise providing a second level of the selection signal, wherein the data processing submodule is further configured to provide an end signal when providing the reference value, the end signal controlling the fourth counter to start counting, the count value of the fourth counter incrementing when the third count value falls into the second range, and otherwise resetting the fourth counter to 0.

[0015] Optionally, the statistics module further includes: a second edge detection submodule, used to detect the selection signal, and to provide a start signal when the selection signal transitions from the first level to the second level, the start signal being used to reset the storage submodule and restore the storage of the second count value.

[0016] Optionally, the read instruction generation circuit includes: a first instruction generation unit, configured to generate a first instruction as the read instruction, the first instruction generation unit including: a first counter, configured to acquire the first count value of the local clock, the first count value being reset according to a valid write instruction; and a first comparator, configured to compare the clock count value and the reference value, and to provide a valid first instruction when the first count value is greater than or equal to the reference value.

[0017] According to another aspect of this application, a communication system is provided, characterized in that it includes: a master node for providing an initial downlink frame at a set frequency in the system clock domain; and a plurality of slave nodes sequentially cascaded with the master node, each slave node receiving and processing the downlink frame provided by an upstream node to achieve instruction response and clock synchronization, each slave node also sending a processed downlink frame to a downstream node, wherein at least some of the slave nodes include the node device as described in any of the preceding claims.

[0018] According to the node device and communication system provided in this application, each node device reads frame data from the buffer circuit when the first count value of its local clock reaches the reference value, so that the frame data arrives at the data processing circuit at a fixed frequency, thereby avoiding large fluctuations in the processing delay of the node device. This improves the stability and reliability of the communication system.

[0019] Furthermore, the reference value generation module adaptively provides reference values ​​and / or calibrates reference values ​​based on the actual time it takes for frame data in the current node device to arrive at the data processing circuit, which improves the noise immunity of the communication system and makes it more conducive to enhancing the environmental adaptability of the communication system. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 This diagram illustrates the transmission of downlink frames in a communication system.

[0022] Figure 2a A schematic structural diagram of a node device in the prior art is shown;

[0023] Figure 2b This diagram illustrates the data transmission timing of a node device in the prior art.

[0024] Figure 3 This diagram shows a schematic structural block diagram of the node device in an embodiment of this application;

[0025] Figure 4A schematic structural diagram of the read instruction generation circuit according to an embodiment of this application is shown;

[0026] Figure 5 Show Figure 4 A schematic structural diagram of the first instruction generation unit;

[0027] Figure 6 Show Figure 4 A schematic structural diagram of the selected signal generation unit;

[0028] Figure 7 Show Figure 6 A schematic structural diagram of the phase comparison module;

[0029] Figure 8 Show Figure 6 A schematic diagram of the structure of the statistics module in the middle;

[0030] Figure 9 This diagram illustrates the transmission timing of a node device according to an embodiment of this application. Detailed Implementation

[0031] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0032] Furthermore, certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0033] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0034] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0035] Figure 2a A schematic structural diagram of a node device in the prior art is shown. In the prior art, each slave node's node device 10 includes a data recovery circuit 11, a buffer circuit 12, a cross-clock domain circuit 14, and a data processing circuit 13. The data recovery circuit 11 receives input data from the local node device and recovers it into frame data and write commands. The cross-clock domain circuit 14 synchronizes write commands from the system clock domain to the local clock domain to provide read commands. The buffer circuit 12 buffers frame data according to valid write commands and reads the buffered frame data according to valid read commands. The data processing circuit 13 processes the read frame data and provides output data to the local node device.

[0036] Figure 2b This diagram illustrates the data transmission timing of a node device in the prior art. (Combined with...) Figure 2a and Figure 2b At time t1, the data recovery circuit 11 receives the input data from the local node device and recovers the input data. At time t2, the data recovery circuit 11 outputs the recovered frame data. Ideally, the data recovery circuit 11 provides a write instruction to the buffer circuit 12 simultaneously with the frame data, so that the buffer circuit 12 synchronously starts buffering the frame data, thereby ensuring the integrity of the frame data. However, in actual operation, due to circuit delays and other reasons, the write instruction may lag slightly behind the frame data. At time t3, the cross-clock domain circuit 14 provides a valid read instruction to read the frame data buffered in the buffer circuit 12.

[0037] Based on the data transmission timing above, the processing delay of each node device includes the time interval between times t1 and t3. The time interval T1 between t1 and t2 is the recovery time required by the data recovery circuit 11, and this time interval T1 is usually fixed. The time interval T2 between t2 and t3 is the delay time introduced by factors such as clock synchronization or interface circuits, and this time interval T2 is usually uncertain. In other words, the fluctuation of the above processing delay is mainly determined by the time interval T2.

[0038] Therefore, this application provides a node device that improves the fluctuation of processing delay by limiting the aforementioned time interval T2, thereby enhancing the stability and reliability of the communication system.

[0039] Figure 3 A schematic structural block diagram of the node device in an embodiment of this application is shown. (Reference) Figure 3 The node device 20 provided in this application embodiment includes a data recovery circuit 11, a cache circuit 12, a data processing circuit 13, and a read instruction generation circuit 100.

[0040] Specifically, the data recovery circuit 11 receives input data from the local node device and recovers it into frame data and write commands. The buffer circuit 12 is connected to the data recovery circuit 11 and buffers the frame data according to valid write commands. The read command generation circuit 100 is connected between the data recovery circuit 11 and the buffer circuit 12 and provides read commands to the buffer circuit. The data processing circuit 13 is connected to the buffer circuit and processes the read frame data and provides output data to the local node device. The read command generation circuit 100 provides a valid read command when it receives a write command and the first count value of the local clock reaches a reference value.

[0041] According to the node device provided in the embodiments of this application, the read instruction generation circuit 100 provides a valid level for the read instruction after receiving the write instruction and after a first count value of local clock cycles, thereby fixing the aforementioned time interval T2 and thus fixing the aforementioned processing delay of the node device. Therefore, fluctuations in processing delay can be avoided, and the reliability of the communication system can be improved.

[0042] Figure 4 This is a schematic structural diagram of the read instruction generation circuit according to an embodiment of this application. Figure 5 Show Figure 4 A schematic structural diagram of the first instruction generation unit; Figure 6 Show Figure 4 A schematic structural diagram of the selected signal generation unit; Figure 7 Show Figure 6 A schematic structural diagram of the phase comparison module; Figure 8 Show Figure 6 A schematic diagram of the statistical module's structure. The following section will illustrate this. Figures 4 to 8 The above-mentioned read instruction generation circuit 100 will be further explained.

[0043] In some embodiments, the aforementioned reference value is a fixed value that is manually set and pre-stored in the read instruction generation circuit 100. Accordingly, the read instruction generation circuit 100 includes a first instruction generation unit 110, and a valid write instruction enables the first instruction generation unit 110 to generate a first instruction based on a first count value of the local clock. The first instruction has a valid level when the first count value is greater than or equal to the reference value. The read instruction generation circuit 100 outputs this first instruction as a read instruction.

[0044] More specifically, the first instruction generation unit 110 includes a first counter 111 and a first comparator 112. The first counter 111 is used to provide a first count value of the local clock. Enabling the first instruction generation unit 110 with a valid write instruction can mean that the first counter 111 is reset upon receiving a valid write instruction. That is, the first counter 111 starts counting clock cycles of the local clock to obtain the aforementioned first count value upon receiving a valid write instruction. The first comparator 112 is used to compare the first count value with a reference value, and provides a valid first instruction when the first count value is greater than or equal to the reference value.

[0045] In a preferred embodiment, the aforementioned reference value is an adaptive value generated by the reference value generation module 113 in the first instruction generation unit 110. Correspondingly, the read instruction generation circuit 100 also includes a second instruction generation unit 120 and a selector 130. The second instruction generation unit 120 is used to synchronize a write instruction from the system clock domain to the local clock domain to generate a second instruction. This second instruction generation unit 120 can be implemented, for example, by a cross-clock domain circuit 14 in the prior art, which will not be elaborated here. The selector 130 is used to output a first instruction as a read instruction based on a first-level selection signal, or to output a second instruction as a read instruction based on a second-level selection signal.

[0046] The reference value generation module 113 may include a second counter 113a, a storage submodule 113b, and a data processing submodule 113c. The second counter 113a is used to acquire a second count value from the local clock, which represents the time interval between a valid write instruction and a valid second instruction. That is, the second counter 113a starts counting local clock cycles when a valid write instruction is received, stops counting when a valid second instruction is received, and provides the second count value. The storage submodule 113b is connected to the second counter 113a and is used to store the second count value. It should be noted that the reference value generation module 113 needs to generate a reference value based on the second count values ​​corresponding to multiple input data. Therefore, the storage submodule 113b should include multiple storage units. The data processing submodule 113c is used to detect and process the second count value stored in the storage submodule 113b to provide the aforementioned reference value. Specifically, the data processing submodule 113c continuously stores a first number of second count values, and when all of the first number of second count values ​​fall within a first range, it processes the first number of second count values ​​to provide their corresponding maximum / minimum / mean / mode / median as reference values.

[0047] It should be noted that, in some embodiments, the confirmation of the first quantity and the first range described above can be implemented using circuit structures such as comparators and counters, and the processing of the second count value to output a reference value can be implemented using circuit structures such as comparators and dividers. In yet other embodiments, the data processing submodule 113c can also be implemented using any processor chip, field-programmable gate array (FPGA), microcontroller (MCU), or application-specific integrated circuit (ASIC) in the prior art. This application does not impose specific limitations in this regard.

[0048] The read instruction generation circuit 100 also includes a selection signal generation unit 140 to generate the selection signal described above.

[0049] In some embodiments, the selection signal generated by the selection signal generation unit 140 remains at a second level before generating the reference value and remains at a first level after generating the reference value. That is, before generating the reference value, the read instruction generation circuit 100 provides a read signal according to a second instruction; after generating the reference value, the read instruction generation circuit 100 provides a read signal according to a first instruction. Correspondingly, the data processing submodule provides an end signal when providing the reference value. The selection signal jumps to the first level when the selection signal generation unit 140 receives the end signal.

[0050] In some other embodiments, the read instruction generation circuit described above can also implement adaptive updates of the reference value. Accordingly:

[0051] The selection signal generation unit 140 includes a phase comparison module 141 and a statistics module 142. For multiple consecutive input data, the phase comparison module 141 compares the second instruction corresponding to each input data with the first instruction provided according to a reference value, and provides the phase difference between the two. The statistics module 142 calculates the phase differences corresponding to multiple consecutive input data and provides a selection signal based on the statistical results. Specifically, the statistics module 142 provides a first level of the selection signal when a second number of phase differences are received and all of these phase differences fall within a second range; otherwise, it provides a second level of the selection signal. This further ensures that the level of the selection signal is switched when the reference value is reliable.

[0052] like Figure 7 As shown, the phase comparison module 141 includes a first edge detection submodule 141a and a third counter 141c. The first edge detection submodule 141a detects the effective edges of the second and first instructions for each input data. The third counter 141c provides a third count value from the local clock, representing the phase difference between the effective edges of the first and second instructions. That is, one of the effective edges of the first and second instructions controls the third counter 141c to start counting, and the other controls it to stop counting and output the third count value. In some embodiments, the third counter 141c may also be reset when counting begins or when the third count value is output. In other embodiments, the phase comparison module 141 further includes a position comparison submodule 141b, which provides a first comparison result when the effective edge of the first instruction precedes the second comparison result. The position comparison submodule can be implemented, for example, using a latch. The first and second comparison results can provide the offset direction of the third count value.

[0053] The statistics module 142 includes a second comparator 142a, a third comparator 142c, and a fourth counter 142b. The second comparator 142a provides a comparison result between a third count value and a second range. The fourth counter 142b provides a fourth count value, wherein the fourth count value increments when the third count value falls within the second range, and resets otherwise. The third comparator 142c compares the fourth count value with the second quantity. Specifically, the third comparator 142c provides a first level of a selection signal when the fourth count value is greater than or equal to the second quantity, and provides a second level of a selection signal otherwise.

[0054] It should be understood that the selection signal should remain at the second level at least before the reference value generation module 113 outputs the reference value. Therefore, the data processing submodule 113c may output a stop signal while still outputting the reference value. This stop signal is used to enable the fourth counter 142b to start counting.

[0055] Furthermore, the statistics module 142 also includes a second edge detection module 142d. The second edge detection module 142d is used to detect the transition edge of the selection signal. When the aforementioned fourth count value is reset, the selection signal transitions from the first level to the second level, and the second edge detection module 142d provides a start signal. The start signal is used to reset the storage submodule 113b and restore the storage of the second count value. That is, the reference value generation module 113 generates a new reference value based on the start signal, thereby achieving adaptive correction of the reference value.

[0056] Figure 9 This diagram illustrates the transmission timing of a node device according to an embodiment of this application. (Reference) Figure 9 According to the node device provided in this application, at time t1, the data recovery circuit 11 receives the input data from the node device at this level and recovers the input data. At time t2, the data recovery circuit 11 outputs the recovered frame data. Ideally, the data recovery circuit 11 provides a valid write instruction to the buffer circuit 12 while providing the frame data, so that the buffer circuit 12 synchronously starts buffering the frame data, thereby ensuring the integrity of the frame data. In actual operation, such as... Figure 9 As shown, due to circuit delays and other factors, a valid write instruction may lag slightly behind the frame data. If the selection signal is at the second level, then at time t3, the buffer circuit 12 reads the buffered frame data according to the valid second instruction. If the selection signal is at the first level, then at time t4, the buffer circuit 12 reads the buffered frame data according to the valid first instruction.

[0057] In other words, when the selected signal is the second level, the processing delay of the node device can be fixed as the sum of time intervals T1 and T3. This avoids fluctuations in processing delay and improves the stability and reliability of the communication system. Furthermore, as... Figure 9 As shown, the reference value can be selected so that time t4 is earlier than time t3, which helps to shorten the processing delay of each node device.

[0058] This application also provides a communication system. This communication system can be a chained communication system, particularly a daisy-chain communication system. This communication system can be applied to a 100Mbps time-division duplex system for high-speed wired media transmission in vehicles. The communication system includes: a master node, used to provide initial downlink frames at a set frequency in the system clock domain; and multiple slave nodes cascaded sequentially with the master node. Each slave node receives and processes the downlink frames provided by the upstream node to achieve command response and clock synchronization. Each slave node also sends processed downlink frames to downstream nodes. At least some of the slave nodes include the node devices provided in the embodiments of this application.

[0059] According to the node device and communication system provided in this application, each node device reads frame data from the buffer circuit when the first count value of its local clock reaches the reference value, so that the frame data arrives at the data processing circuit at a fixed frequency, thereby avoiding large fluctuations in the processing delay of the node device. This improves the stability and reliability of the communication system.

[0060] Furthermore, the reference value generation module adaptively provides reference values ​​and / or calibrates reference values ​​based on the actual time it takes for frame data in the current node device to arrive at the data processing circuit, which improves the noise immunity of the communication system and makes it more conducive to enhancing the environmental adaptability of the communication system.

[0061] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit this application to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A node device, characterized in that, The node device is used in a multi-node communication system, and the node device includes: The data recovery circuit is used to receive input data from the local node device and recover it into frame data and write instructions; A buffer circuit, connected to the data recovery circuit, is used to buffer the frame data according to a valid write instruction and output the frame data according to a valid read instruction; A read instruction generation circuit, connected between the data recovery circuit and the cache circuit, is used to provide the read instruction; and The data processing circuit, connected to the buffer circuit, is used to process the read frame data and provide output data for the local node device. The read instruction generation circuit provides the valid read instruction when it receives the write instruction and the first count value of the local clock reaches the reference value.

2. The node device according to claim 1, characterized in that, The read instruction generation circuit includes: The first instruction generation unit is enabled by the valid write instruction to generate a first instruction based on the first count value of the local clock. A second instruction generation unit is configured to synchronize the write instruction from the system clock domain to the local clock domain to generate a second instruction; and A selector is configured to output the first instruction as the read instruction based on a first-level selection signal, or to output the second instruction as the read instruction based on a second-level selection signal.

3. The node device according to claim 2, characterized in that, The first instruction generation unit includes: A first counter is configured to acquire the first count value of the local clock, the first count value being reset according to a valid write instruction; and A first comparator is configured to compare the first count value with the reference value, and to provide a valid first instruction when the first count value is greater than or equal to the reference value.

4. The node device according to claim 3, characterized in that, The first instruction generation unit further includes a reference value generation module for providing the reference value. The reference value generation module includes: A second counter is used to acquire a second count value of the local clock, the second count value representing the time interval between a valid write instruction and a valid second instruction; A storage submodule, connected to the second counter, is used to store the second count value; and The data processing submodule is used to detect the second count value stored in the storage submodule, and to provide the reference value when the storage submodule continuously stores a first number of the second count values ​​and all of the first number of the second count values ​​fall within a first range. The reference value is the maximum / minimum / mean / mode / median of the first number of the second count values.

5. The node device according to claim 4, characterized in that, The data processing submodule is also configured to provide an end signal when providing the reference value. The read instruction generation circuit also includes a selection signal generation unit for generating the selection signal. The selection signal changes to the first level when the signal generation unit receives the end signal.

6. The node device according to claim 4, characterized in that, The read instruction generation circuit also includes a selection signal generation unit for generating the selection signal. The selection signal generation unit includes: A phase comparison module, for a plurality of consecutive input data, compares the second instruction and the first instruction corresponding to each input data, and provides the phase difference between the two; and The statistics module is used to calculate the phase difference of multiple consecutive input data sets and provide the selection signal based on the statistical results of the phase differences. The statistical module provides a first level of the selection signal when it continuously receives a second number of phase differences, and all of the second number of phase differences fall within a second range; otherwise, it provides a second level of the selection signal.

7. The node device according to claim 6, characterized in that, The phase comparison module includes: The first edge detection submodule, for each of the input data, is used to detect the valid edge of the second instruction and the valid edge of the first instruction; and A third counter is used to acquire a third count value of the local clock, the third count value representing the phase difference between the effective edge of the first instruction and the effective edge of the second instruction.

8. The node device according to claim 7, characterized in that, The phase comparison module further includes: The position comparison submodule is used to provide a first comparison result when the valid edge of the first instruction comes first, and a second comparison result otherwise.

9. The node device according to claim 7 or 8, characterized in that, The statistics module includes: A second comparator is used to provide a comparison result between the third count value and the second range; and The fourth counter is used to provide the fourth count value; A third comparator is used to compare the fourth count value and the second quantity to provide a first level of the selection signal when the fourth count value is greater than or equal to the second quantity, and otherwise to provide a second level of the selection signal. The data processing submodule is further configured to provide an end signal when the reference value is provided. The end signal controls the fourth counter to start counting. When the third count value falls into the second range, the count value of the fourth counter increments; otherwise, the fourth counter is reset to 0.

10. The node device according to claim 9, characterized in that, The statistics module also includes: The second edge detection submodule is used to detect the selection signal and provide a start signal when the selection signal transitions from the first level to the second level. The start signal is used to reset the storage submodule and restore the storage of the second count value.

11. The node device according to claim 1, characterized in that, The read instruction generation circuit includes: A first instruction generation unit is configured to generate a first instruction as the read instruction, the first instruction generation unit comprising: A first counter is configured to acquire the first count value of the local clock, the first count value being reset according to a valid write instruction; and A first comparator is configured to compare the clock count value with the reference value, and to provide a valid first instruction when the first count value is greater than or equal to the reference value.

12. A communication system, characterized in that, include: The master node is used to provide the initial downlink frames in the system clock domain at a set frequency; as well as Multiple slave nodes are sequentially cascaded with the master node. Each slave node receives and processes downlink frames provided by the upstream node to achieve command response and clock synchronization. Each slave node also sends the processed downlink frames to the downstream node. Wherein, at least a portion of the slave nodes include the node device as described in any one of claims 1-11.

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