A multi-channel digital serial voice test equipment

Abstract

The utility model relates to the testing technical field of voice communication equipment, disclose a kind of multi-channel digital serial port voice test equipment, comprising: the interface module of equipment under test, FPGA module, analog audio interface module and host computer;The interface module of equipment under test is connected with multiple equipment under test, and host computer, the interface module of equipment under test, analog audio interface module and FPGA module are connected;Host computer is used to play audio data, audio data is converted into digital after analog audio interface module, and is transmitted to FPGA module, is transmitted to equipment under test by the interface module of equipment under test, equipment under test receives digital conversion after audio data and is transmitted to FPGA module by the interface module of equipment under test, digital conversion after audio data after being handled by FPGA module is converted into analog after analog audio interface module, and output is exported.This application simultaneously accesses multiple digital serial port voice communication headsets by the interface module of equipment under test, and simultaneously carries out decoding and mix sound to multiple digital voice signals by FPGA module.

Description

Technical Field

[0001] This utility model relates to the field of testing technology for voice communication equipment, and in particular to a multi-channel digital serial port voice testing device. Background Technology

[0002] Voice communication is a common method in many communication scenarios and an important tool for maintaining communication with staff. Voice communication headsets are one type of wearable voice transmission product, and as the source of the voice communication link, their quality is fundamental to the overall voice communication quality. To confirm the quality of voice communication headsets before delivery to users, relevant functional and performance tests must be conducted. Voice testing equipment is the equipment used to conduct these tests. Existing voice communication headsets are based on analog electrical signals, and the corresponding testing equipment also collects and processes multiple analog level signals, with mixing methods also based on analog audio signals. Because analog signals are susceptible to interference, a type of voice communication headset based on digital signals has emerged. Existing voice testing equipment is no longer sufficient for testing this type of headset. Therefore, it is necessary to find a testing device capable of performing voice tests on digital signal-based voice communication headsets. Utility Model Content

[0003] Therefore, this utility model provides a multi-channel digital serial port voice testing device.

[0004] Specifically, the following technical solutions are included: This application provides a multi-channel digital serial port voice testing device, including: The device under test (DUT) consists of an interface module, an FPGA module, an analog audio interface module, and a host computer. The device under test (DUT) interface module is connected to the DUT; the host computer, the DUT interface module, the analog audio interface module, and the FPGA module are connected; the DUT interface module is connected to the FPGA module; and the FPGA module is connected to the analog audio interface module. The host computer is used to play audio data. The audio data is converted from analog to digital by the analog audio interface module and then transmitted to the FPGA module. It is then transmitted to the device under test (DUT) via the DUT interface module. The DUT receives the converted audio data and transmits it to the FPGA module via the DUT interface module. After being processed by the FPGA module, the converted audio data is then converted from digital to analog by the analog audio interface module and output.

[0005] For example, the device under test interface module includes multiple serial communication interfaces, and the device under test is configured with multiple serial communication interfaces, with each serial communication interface connected to a corresponding device under test. Multiple devices under test receive the audio data and simultaneously transmit it to the FPGA module via the device under test interface module.

[0006] For example, the analog audio interface module includes an analog-to-digital converter chip and multiple digital-to-analog converter chips; The audio data is converted by the analog-to-digital converter chip and then input to the FPGA module. The processed audio data is converted by the digital-to-analog converter chip and then output.

[0007] For example, the digital-to-analog converter chip is connected to a dedicated output interface, a monitoring output interface, or a recording output interface.

[0008] For example, the FPGA module includes an FPGA chip, a clock submodule, an RS422 submodule, an audio communication submodule, an audio processing submodule, and a mixing submodule, wherein the clock submodule, the RS422 submodule, the audio communication submodule, the audio processing submodule, and the mixing submodule are respectively connected to the FPGA chip; The interface module of the device under test and the RS422 submodule are connected; The analog audio interface module and the audio communication submodule are connected; The host computer and the RS422 submodule are connected for communication. The audio communication submodule is connected to the audio integrated processing submodule, the audio integrated processing submodule is connected to the mixing submodule, and the mixing submodule is connected to the audio communication submodule.

[0009] For example, the voice testing equipment includes a power supply module, and the FPGA module and the analog audio interface module are respectively connected to the power supply module.

[0010] For example, the FPGA module includes a power supply chip and an FPGA chip, which are connected to each other.

[0011] For example, the analog ground and digital ground in the FPGA module are powered by the same power.

[0012] For example, the voice testing equipment includes a background signal-to-noise ratio (SNR) test state and a device SNR test state; Under the aforementioned background signal-to-noise ratio test conditions, the interface module of the device under test and the electrical loopback connector are connected; In the signal-to-noise ratio test state of the voice test equipment, the interface module of the device under test is connected to the device under test.

[0013] For example, the voice testing equipment includes a background distortion test state and a device distortion test state; Under the aforementioned background distortion test conditions, the interface module of the device under test and the loopback connector are connected; In the distortion test state of the voice test equipment, the interface module of the device under test is connected to the device under test.

[0014] The beneficial effects of the technical solution provided by this utility model include at least the following: This application simulates a front-end voice receiving and processing device in an application scenario. It connects to a digital serial port voice communication headset through the interface module of the device under test, performs digital-to-analog conversion and analog-to-digital conversion through the analog audio interface module, and simultaneously decodes and mixes multiple digital voice signals through the FPGA module, thus realizing the testing of a voice communication headset based on digital signals. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the principle of a multi-channel digital serial port voice testing device in one embodiment of the present invention; Figure 2 This is a schematic diagram of the internal module connections of the FPGA module in one embodiment of the present invention.

[0017] The accompanying drawings have illustrated specific embodiments of the present invention, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present invention in any way, but rather to illustrate the concept of the present invention to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0019] Before further describing the embodiments of this utility model in detail, the directional terms involved in the embodiments of this utility model, such as "upper part," "lower part," and "side part," are used to refer to... Figure 1 The orientation shown is a reference and does not limit the scope of protection of this utility model.

[0020] To make the technical solution and advantages of this utility model clearer, the embodiments of this utility model will be described in further detail below with reference to the accompanying drawings.

[0021] like Figure 1 As shown, this application provides a multi-channel digital serial port voice testing device, including: a device under test (DUT) interface module, an FPGA module, an analog audio interface module, and a host computer; the DUT interface module is connected to the DUT, and the host computer, the DUT interface module, the analog audio interface module, and the FPGA module are connected. The host computer is used to play audio data. The audio data is converted from analog to digital by the analog audio interface module and then transmitted to the FPGA module, and then transmitted to the DUT via the DUT interface module. The DUT receives the converted audio data and transmits it to the FPGA module via the DUT interface module. After being processed by the FPGA module and converted from analog to digital, the audio data is converted from digital to analog by the analog audio interface module and then output.

[0022] Specifically, the device under test (DUT) is a digital serial voice communication headset. An analog audio interface module is used for voice-to-analog (DAC) and voice-to-analog (DAC) conversion. An FPGA module performs decoding and mixing. A host computer plays the test audio data and sends configuration and control commands to the FPGA module via its software. This application simulates a front-end voice receiving and processing device in an application scenario. The DUT interface module connects to the digital serial voice communication headset, the analog audio interface module performs DAC and DAC conversion, and the FPGA module decodes and mixes the digital voice signal, thus enabling testing of a digital-signal-based voice communication headset.

[0023] Specifically, such as Figure 1 As shown, the device under test (DUT) interface module includes multiple serial communication interfaces, and multiple DUTs are configured. Each serial communication interface is connected to a corresponding DUT. Multiple DUTs receive the audio data and simultaneously transmit it to the FPGA module via the DUT interface module. This application provides a voice communication interface consistent with the application scenario for simulating internal and external uplink voice, downlink voice, and internal voice communication between staff, thereby enabling functional and performance testing of the voice communication headset under near-realistic working conditions.

[0024] Table 1. Connector node definitions for each serial communication interface.

[0025] Specifically, the device under test (DUT) interface module has multiple parallel serial communication interfaces, allowing simultaneous connection to multiple voice communication headsets. Each interface employs a serial communication chip with isolation capabilities, achieving signal ground isolation between the external voice communication headset and the internal signal processing module of the test equipment. It also supports hot-swapping of the voice communication headset to simulate real-world operating conditions.

[0026] Specifically, the device under test (DUT) interface module is mainly used to connect five channels of the voice communication headset under test. The core of the DUT interface module consists of five serial communication chips. To accommodate the hot-swapping requirements of the voice communication headset, the serial communication interfaces in the DUT interface module use chips with isolation capabilities. In this embodiment, each serial communication interface uses a DB-15 connector compatible with the connectors of the voice communication headset under test, and the node definitions are shown in Table 1.

[0027] The parameter settings of the serial communication chip, such as voice bit synchronization (rising or falling edge corresponding to high or low bit), voice code synchronization (i.e., clock frequency), and voice code data (involving the sampling rate and quantization bits of the analog sound signal), as described in Table 1, should match the parameter settings of the voice communication headset under test.

[0028] Specifically, such as Figure 1 As shown, the interface module of the device under test is connected to the FPGA module through a level conversion chip. The level conversion chip is an indispensable component in electronic systems. Its core function is to convert signals between different levels, ensuring that signals can be smoothly transmitted between circuits or devices with different voltage levels, and solving the signal mismatch problem.

[0029] Specifically, the analog audio interface module includes an analog-to-digital converter (ADC) chip and multiple digital-to-analog converter (DAC) chips. The audio data is converted by the ADC chip and then input to the FPGA module; the processed audio data is converted by the DAC chip and then output. The ADC chip and multiple DAC chips are arranged in parallel.

[0030] Specifically, such as Figure 1As shown, the analog audio interface module includes four 3.5-inch audio jacks. One audio jack contains an analog-to-digital (AD) converter chip for uplink voice input; the other three audio jacks each contain a digital-to-analog (DA) converter chip, respectively for downlink voice output, monitoring output, and recording output to the host computer. This analog audio interface module enables the transmission of four analog audio signals. Specifically, the uplink voice input analog audio signal is sent to the central FPGA unit for processing after passing through the AD converter chip. The digital audio signal processed by the central FPGA unit is then converted to a DA converter and sent to the corresponding analog audio interface output. This application uses the analog audio interface module to convert analog signals into digital signals, providing the basis for the digital uplink voice signal of the device under test (DUT). The digital downlink voice signal generated by the DUT is subsequently converted back to analog signals through the analog audio interface module, providing a foundation for subsequent performance evaluation.

[0031] Specifically, the digital-to-analog converter chip is connected to a dedicated output interface, a monitoring output interface, or a recording output interface. Specifically, as shown... Figure 1 As shown, the downlink voice output implemented by the digital-to-analog converter chip is connected to a dedicated output interface, the monitoring output is connected to a monitoring output interface, and the recording output is connected to a recording output interface. The recording output interface is connected to the host computer to realize the storage of recordings.

[0032] Specifically, such as Figure 2 As shown, the FPGA module includes an FPGA chip, a clock submodule, an RS422 submodule, an audio communication submodule, an audio processing submodule, and a mixing submodule. The clock submodule, RS422 submodule, audio communication submodule, audio processing submodule, and mixing submodule are all connected to the FPGA chip. The device under test (DUT) interface module is connected to the RS422 submodule, the analog audio interface module is connected to the audio communication submodule, and the host computer is communicatively connected to the RS422 submodule. The audio communication submodule is connected to the audio processing submodule, the audio processing submodule is connected to the mixing submodule, and the mixing submodule is connected to the audio communication submodule.

[0033] Specifically, the FPGA module, with an FPGA chip at its core, realizes parallel processing and mixing of multiple digital voice signals. The FPGA module uses a high-performance, high-capacity FPGA chip, enabling gain control and parameter monitoring of each voice signal. Simultaneously, the FPGA module performs digital mixing of multiple voice signals. To simulate real-world conditions, the mixing strategy is as follows: multiple downlink voice signals from the voice communication headset and one uplink voice signal from the analog audio interface module's AD conversion input are mixed. Each voice communication headset can listen to the other mixes (but not its own downlink voice signal). For example, as... Figure 1 As shown, the FPGA module performs mixing processing on 5 downlink voice channels and 1 uplink voice channel. Each voice communication headset can listen to the other 5 mixed channels (but not its own downlink voice channel).

[0034] Specifically, the FPGA module needs to perform simultaneous multi-channel mixing calculations and complete complex and repetitive data processing tasks with high real-time requirements. Therefore, it requires a large number of DSP processing modules, and simultaneous operation requires significant memory resources for caching. When selecting an FPGA chip, a model that can meet the above performance requirements should be considered. For example... Figure 1 As shown, memory resource caching is implemented by setting up a FLASH memory connected to the FPGA module.

[0035] The FPGA chip needs to be programmed with corresponding control software to realize the core control and data processing of the system. The FPGA module mainly implements the following functions: configuring the audio CODEC chip in the analog audio interface module; receiving uplink audio signals from the analog audio interface module; sending downlink audio signals to the analog audio interface module; receiving audio data from each serial communication interface of the device under test (DUT) interface module; sending audio data from each serial communication interface of the DUT interface module; receiving volume adjustment commands from the host computer; sending volume telemetry signals to the DUT interface module and the analog audio interface module; sending telemetry signals for audio data from each channel to the DUT interface module and the analog audio interface module; and performing real-time mixing processing. To meet these functional requirements, the FPGA module is mainly designed with the following modular components: The clock submodule generates the system clock for the FPGA's core logic and interfaces using an external free-running clock (such as a crystal oscillator, PLL chip, or external clock source). The system clock frequency needs to be determined based on the audio signal clock requirements of the voice communication headset. These shared system clocks are used to generate the reset and release timings for the core processing logic and interfaces. The clock submodule connects to the FPGA chip's global clock input pins via a differential clock interface (such as LVDS) or a single-ended clock interface (such as LVCMOS). It provides a stable reference clock signal (such as 25MHz or 50MHz). Internally, the FPGA chip uses a PLL (phase-locked loop) to multiply, divide, or phase-shift the reference clock to generate the operating clocks required by each module (such as the 48kHz sampling clock for the audio module and the baud rate clock for RS422). The clock submodule ensures timing synchronization between internal and external modules within the FPGA, avoiding metastability issues during data transmission.

[0036] The RS422 submodule, written in Verilog HDL, instantiates a FIFO IP and supports the Axi4-Lite on-chip interconnect bus, facilitating system integration. The RS422 submodule supports configurable serial rates, allowing for multiple transmission speeds to accommodate various digital voice communication headsets. It connects to the GPIO pins of the FPGA chip via a UART interface (TXD, RXD). The FPGA chip internally instantiates a UART controller FIFO IP core (or uses custom UART logic) for protocol parsing. The FPGA chip sends control commands (such as configuring the analog audio interface module) or status data (such as audio signal levels and module operating status) through the RS422 submodule. The FPGA chip also receives control commands (such as volume adjustment and channel switching) or configuration parameters from external devices (such as a host computer) through the RS422 submodule.

[0037] The audio communication submodule is primarily responsible for communication with the programmable audio CODEC chip in the analog audio interface module, including configuring the audio CODEC chip via a three-wire SPI and communicating via I... 2 The S-bus enables audio signal communication with the audio CODEC chip. The audio communication submodule uses an audio interface protocol (such as I...) 2 The S, PCM, and TDM pins are connected to the GPIO pins of the FPGA chip, and the audio controller IP core (such as I) is instantiated inside the FPGA chip. 2 S Controller).

[0038] The audio processing submodule implements functions such as audio data caching, format processing, test status recording, and signal source generation. It includes a transmit direction and a receive direction, corresponding to the audio ADC input and audio DAC output, respectively, with each direction processing the left and right channels independently. The audio processing submodule communicates with the mixing submodule via a FIFO interface. The audio processing submodule is typically implemented internally within the FPGA chip using logic resources (rather than as an independent peripheral), directly connecting to the FPGA chip's internal data bus or RAM module. The audio processing submodule receives raw audio data from the audio communication submodule, performs filtering (such as low-pass and high-pass filtering), echo cancellation, noise suppression, equalizer (EQ) adjustment, and volume control, outputting the optimized audio stream to the mixing submodule.

[0039] The mixing submodule handles the mixing operations for each voice channel. The mixing strategy simulates a common call environment, specifically mixing five downlink voice channels (voices sent from the headset to the downstream output device via the interface module of the device under test) and one uplink voice channel (input via AD conversion from the analog audio interface module, simulating input to the headset via a microphone). Each headset can listen to the other five mixed channels (but not its own downlink voice). The mixing submodule is also implemented within the FPGA chip, connected to the audio processing submodule and audio communication module via an internal FIFO (First-In-First-Out buffer) or RAM. The FPGA chip receives control commands from the host computer via the RS422 submodule, dynamically adjusting mixing parameters (such as channel volume weights and mixing mode switching), and coordinating the timing between the mixing submodule and the audio processing submodule through an internal state machine.

[0040] The FPGA module forms an "input-processing-mixing-output" audio signal chain through an audio communication module → audio integrated processing module → mixing module → audio communication module. All data is transmitted through the FPGA chip's internal bus, eliminating the need for external physical connections. External control commands and signals are transmitted to the FPGA chip via the RS422 submodule. After parsing, the FPGA chip configures audio processing parameters (such as filter coefficients) or mixing logic (such as channel enable) through its internal registers. The FPGA chip distributes the reference clock from the clock submodule to the RS422 submodule (UART baud rate clock), the audio communication submodule (sampling clock), and the mixing submodule (operation clock), achieving system-wide timing synchronization.

[0041] The clock submodule provides the timing foundation, the RS422 submodule enables external interaction, the audio communication submodule is responsible for signal input and output, and the audio comprehensive processing submodule and mixing module complete the core algorithm processing inside the FPGA, ultimately forming a complete audio signal acquisition, processing, mixing, and transmission system. The connections and data transmission of each module revolve around the FPGA, reflecting the core value of the FPGA as a "programmable control center" in embedded systems.

[0042] Specifically, the host computer communicates with the FPGA module in the testing equipment via a network port and network cable. The host computer includes host computer software, which uses the FPGA module to control the volume of each voice channel; implements mixing control strategies for multiple voice channels by enabling and disabling each voice channel; and monitors and displays the status of each voice channel, including its enable / disable status, volume gain, input clock status, input clock frequency and rate, and peak-to-peak value of the input signal. The host computer software also has the function of storing and playing back the mixed analog audio, the mixed digital audio source code, and each pre-mixed digital audio source code via the FPGA module.

[0043] Specifically, the voice testing equipment includes a power supply module, and the FPGA module and the analog audio interface module are respectively connected to the power supply module. Figure 1 As shown, the power supply module realizes the conversion function of 220V AC to ±12V and +5V DC, and is composed of a switching power supply.

[0044] Specifically, the FPGA module includes a power supply chip and an FPGA chip, which are connected to each other. The power supply chip, belonging to the power supply module, generates the different voltages required by the FPGA chip. The digital ground and analog ground of this part share a common ground, meaning the analog ground and digital ground in the FPGA module are powered together to improve the AD / DA conversion accuracy.

[0045] Specifically, through Figure 1 and Figure 2 The following is a description of the voice signal transmission link: 1) The host computer plays audio data, which is converted from analog to digital by the AD conversion chip in the analog audio interface module; 2) Digital audio data is transmitted to the audio communication submodule of the FPGA module, and then transmitted to the device under test (DUT) via the FPGA chip, RS422 submodule, and DUT interface module. The digital audio data consists of uplink voice from multiple DUT devices. Simultaneously, the digital audio data transmitted to the audio communication submodule is transmitted to the audio integrated processing submodule, and then to the mixing submodule. 3) The digital audio data flowing through the device under test is transmitted to the RS422 submodule of the FPGA module via the interface module of the device under test, and then through the FPGA chip, audio communication submodule, audio integrated processing submodule, and finally transmitted to the mixing submodule; 4) The uplink voice transmitted to the mixing submodule in step 2) and the downlink voice generated by the multiple devices under test in step 3) are mixed in the mixing submodule to obtain processed digital audio data; 5) The processed digital audio data is transmitted to the analog audio interface module via the audio communication submodule, and then converted from digital to analog by the DA converter chip to obtain the processed analog audio data; 6) The processed analog audio data is transmitted to the host computer.

[0046] The uplink and downlink voice signals are analyzed by the host computer to analyze the performance of the equipment under test.

[0047] Specifically, the voice testing equipment includes a background signal-to-noise ratio (SNR) test state and a device SNR test state. In the background SNR test state, the device under test (DUT) interface module and the electrical loopback connector are connected; in the voice testing equipment SNR test state, the DUT interface module and the DUT are connected. Specifically, in the background SNR test state, the SNR of the voice testing equipment itself is tested; in the device SNR test state, the system SNR of both the voice testing equipment and the DUT is tested.

[0048] The specific test steps for the background signal-to-noise ratio (SNR) test and the equipment SNR test are as follows: The first step involves connecting the device under test (DUT) interface module to the voice test equipment using an electrical loopback connector. This allows the uplink voice signal to loop back to the downlink voice output via the loopback connector. At this stage, the voice test equipment is not connected to the DUT headset. A high signal-to-noise ratio (SNR) test audio data (uplink voice) stored on the hard drive is played using the host computer software. Based on steps 1) to 6), this test audio data signal is looped back as downlink voice via the loopback connector. This downlink voice is recorded, stored, and transmitted to the host computer in real-time by the voice test equipment. After real-time recording and storage, the host computer software compares and analyzes the time-frequency curves of the uplink and downlink voice. Since the time-frequency curve of the uplink voice is known (reference signal), the background SNR of the voice test equipment can be determined by calculating the average power of the signal and noise in the downlink voice.

[0049] The second step involves unplugging the loopback connector and connecting the voice communication headset under test (DUT) to the DUT interface module on the voice test equipment. Simultaneously, the microphone of the DUT is placed close to its headset. At this point, the uplink voice signal will be output from the headset's headset, and the voice output from the headset will be received by the headset's microphone and output as downlink voice (loopback mode). Using the host computer software, the same test audio data used in the first step is played back. Based on steps 1) to 6), the uplink voice signal is looped back by the voice communication headset as downlink voice, which is then recorded, stored, and transmitted to the host computer in real time by the voice test equipment. After the voice test equipment records and stores the audio in real time, the host computer software compares and analyzes the time-frequency curves of the uplink and downlink voice to obtain the system signal-to-noise ratio (SNR) of both the test equipment and the device under test. After removing the background SNR of the voice test equipment obtained in the first step from the system SNR, the overall SNR of the voice communication headset under test can be obtained (before calculating the overall SNR, the average power of the device's background noise is removed from the average power of the total noise). The overall SNR refers to the combined SNR of the input (earpiece) and output (microphone) paths of the voice communication headset.

[0050] Specifically, the voice testing equipment includes a background distortion test state and a device distortion test state. In the background distortion test state, the device under test (DUT) interface module and the electrical loopback connector are connected. In the voice testing equipment distortion test state, the DUT interface module and the DUT are connected. Specifically, in the background distortion test state, the distortion of the voice testing equipment itself is tested; in the device distortion test state, the system distortion of both the voice testing equipment and the DUT is tested.

[0051] The specific test steps for background distortion test and equipment distortion test are as follows: The first step involves connecting the device under test (DUT) interface module to the voice test equipment using an electrical loopback connector. A high-quality human voice audio signal (uplink audio) stored on the hard drive is then played using the host computer software. This audio signal covers the typical frequency range of human voice. Based on steps 1) to 6), the audio signal is looped back as downlink audio using the electrical loopback connector. This downlink audio is recorded, stored, and transmitted to the host computer in real-time by the voice test equipment. After real-time recording and storage, the host computer software compares and analyzes the time-frequency curves of the uplink and downlink audio to assess the inherent distortion of the voice test equipment when transmitting human voice signals. The distortion is calculated using the STOI scoring method. First, the speech segments in the signal are marked, and then a short-time Fourier transform is performed on each speech segment. The STOI score is obtained by calculating the spectral correlation between the downlink and uplink audio. A higher score indicates lower distortion.

[0052] The second step involves unplugging the loopback connector and connecting the voice communication headset under test (DUT) to the DUT interface module on the voice test equipment. Simultaneously, the headset's microphone is placed close to its earpiece. The uplink voice signal will then be output from the headset's earpiece, and the audio output from the earpiece will be received by the headset's microphone and output as downlink voice (loopback mode). Using the host computer software, the same human voice audio signal used in the first step is played. Based on steps 1) to 6), this human voice audio signal is looped back by the voice communication headset as downlink voice. This downlink voice is recorded, stored, and transmitted to the host computer in real time by the voice test equipment. After real-time recording and storage, the host computer software compares and analyzes the time-frequency curves of the uplink and downlink voice signals to obtain the system distortion of both the voice test equipment and the DUT. After removing the influence of the voice test equipment's inherent distortion from the system distortion, the overall distortion of the DUT's voice communication headset when transmitting human voice signals can be obtained.

[0053] The voice testing equipment in this application can achieve high integration and lower cost. One voice testing equipment can simultaneously complete the functional testing, signal-to-noise ratio evaluation, and voice transmission quality evaluation of multiple voice communication headsets.

[0054] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0055] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0056] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A multi-channel digital serial port voice testing device, characterized in that, include: The device under test (DUT) consists of an interface module, an FPGA module, an analog audio interface module, and a host computer. The device under test (DUT) interface module is connected to the DUT, and the host computer, the DUT interface module, the analog audio interface module, and the FPGA module are connected. The host computer is used to play audio data. The audio data is converted from analog to digital by the analog audio interface module and then transmitted to the FPGA module. It is then transmitted to the device under test (DUT) via the DUT interface module. The DUT receives the converted audio data and transmits it to the FPGA module via the DUT interface module. After being processed by the FPGA module, the converted audio data is then converted from digital to analog by the analog audio interface module and output.

2. The multi-channel digital serial port voice testing device according to claim 1, characterized in that, The device under test interface module includes multiple serial communication interfaces, and multiple devices under test are configured. The serial communication interfaces are connected to the devices under test in a one-to-one correspondence. Multiple devices under test receive the audio data and simultaneously transmit it to the FPGA module via the device under test interface module.

3. The multi-channel digital serial port voice testing device according to claim 1, characterized in that, The analog audio interface module includes an analog-to-digital converter chip and multiple digital-to-analog converter chips; The audio data is converted by the analog-to-digital converter chip and then input to the FPGA module. The processed audio data is converted by the digital-to-analog converter chip and then output.

4. The multi-channel digital serial port voice testing device according to claim 3, characterized in that, The digital-to-analog converter chip is connected to a dedicated output interface, a monitoring output interface, or a recording output interface.

5. The multi-channel digital serial port voice testing device according to claim 1, characterized in that, The FPGA module includes an FPGA chip, a clock submodule, an RS422 submodule, an audio communication submodule, an audio processing submodule, and a mixing submodule. The clock submodule, the RS422 submodule, the audio communication submodule, the audio processing submodule, and the mixing submodule are respectively connected to the FPGA chip. The interface module of the device under test and the RS422 submodule are connected; The analog audio interface module and the audio communication submodule are connected; The host computer and the RS422 submodule are connected for communication. The audio communication submodule is connected to the audio integrated processing submodule, the audio integrated processing submodule is connected to the mixing submodule, and the mixing submodule is connected to the audio communication submodule.

6. The multi-channel digital serial port voice testing device according to claim 1, characterized in that, The voice testing equipment includes a power supply module, and the FPGA module and the analog audio interface module are respectively connected to the power supply module.

7. The multi-channel digital serial port voice testing device according to claim 1, characterized in that, The FPGA module includes a power supply chip and an FPGA chip, which are connected to each other.

8. A multi-channel digital serial port voice testing device according to any one of claims 5 or 7, characterized in that, The analog ground and digital ground in the FPGA module share the same power.

9. A multi-channel digital serial port voice testing device according to claim 1, characterized in that, The voice testing equipment includes a background signal-to-noise ratio (SNR) test state and an equipment SNR test state; Under the aforementioned background signal-to-noise ratio test conditions, the interface module of the device under test and the electrical loopback connector are connected; In the signal-to-noise ratio test state of the voice test equipment, the interface module of the device under test is connected to the device under test.

10. A multi-channel digital serial port voice testing device according to claim 1, characterized in that, The voice testing equipment includes a background distortion test state and an equipment distortion test state; Under the aforementioned background distortion test conditions, the interface module of the device under test and the loopback connector are connected; In the distortion test state of the voice test equipment, the interface module of the device under test is connected to the device under test.

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