A wiring structure of a printed circuit board, a board card and an electronic device

Abstract

The application provides a wiring structure of a printed circuit board, a board card and an electronic device. The wiring structure comprises a PCB, a plurality of first areas on the PCB, and a second area between the plurality of first areas. The first area is provided with a plurality of vias, a plurality of conductive units and a first signal line, and the second area is provided with a second signal line. The line width of the second signal line is greater than that of the first signal line. One end of the first signal line is electrically connected to one via of the first area, the other end avoids other vias, and the first signal line extends to the second area through the conductive unit and is electrically connected to one end of the second signal line extending to the first area. When the first signal lines of different first areas communicate with each other through the second signal line of the second area, the conductive unit can locally enlarge the line width of the first signal line, so that the impedance of the first signal line and the second signal line is matched with each other, thereby improving the return loss and crosstalk and improving the transmission quality of the high-speed signal.

Description

Technical Field

[0001] This application relates to the field of printed circuit board design technology, and in particular to a printed circuit board wiring structure, board card, and electronic device. Background Technology

[0002] Printed circuit boards (PCBs) are an indispensable core component in modern electronic products. They not only provide physical support for electronic components, but also connect the components electrically through metal wires, thereby building a complete circuit system.

[0003] Ball Grid Array (BGA) packaging is a common packaging form for high-speed printed circuit boards (PCBs), offering advantages such as small size, numerous pins, excellent signal integrity, and good heat dissipation. With the increasing complexity of circuit systems and the growing integration of digital chips, high-speed PCBs are evolving towards greater integration and higher speeds, resulting in increasingly higher pad densities for the pins of BGA-packaged chips. Therefore, considering the area and thickness limitations of high-speed PCBs, current technology uses different line widths for signal lines in BGA and non-BGA packaged areas. However, as signal transmission rates continue to increase, the requirements for signal integrity also become more stringent. The different trace widths in BGA and non-BGA packaged areas lead to impedance abrupt changes and discontinuities, thus affecting the integrity of signal transmission.

[0004] Therefore, how to provide a printed circuit board routing structure that can meet the high-speed signal integrity transmission requirements of existing BGA and non-BGA areas has become one of the technical problems that urgently need to be solved by those in the field. Utility Model Content

[0005] This application aims to at least partially address one of the technical problems in the related art.

[0006] Therefore, the first objective of this application is to propose a printed circuit board routing structure, board card, and electronic device that can improve the problems of impedance abrupt changes and increased crosstalk that occur in existing signal lines during high-speed signal transmission, thereby improving the transmission quality of high-speed signals.

[0007] To achieve the above objectives, a first aspect of this application provides a trace structure for a printed circuit board, including a printed circuit board having a plurality of spaced first regions and a second region located between the plurality of first regions: wherein, The first region is provided with a plurality of vias arranged in an array, a plurality of conductive units spaced apart from the vias, and a first signal line; the second region is provided with a second signal line, the line width of the second signal line being greater than that of the first signal line; One end of the first signal line is electrically connected to one of the vias, and the other end avoids the other vias and extends through the conductive unit into the second region, and is electrically connected to one end of the second signal line extending into the first region.

[0008] Optionally, the first region is a chip packaging region, on which a packaging chip is provided, and the packaging chip is packaged in the chip packaging region using ball-shaped lead grid array packaging technology.

[0009] Optionally, the packaged chip includes at least one CPU chip and multiple DDR chips, and each packaged chip corresponds one-to-one with each chip packaging area.

[0010] Optionally, the CPU chip and the DDR chip transmit electrical signals sequentially through corresponding first signal lines and second signal lines.

[0011] Optionally, the electrical signal is a single-ended signal.

[0012] Optionally, the conductive unit is a symmetrical regular shape, including one of the following: circle, ellipse, triangle, quadrilateral, trapezoid, and a symmetrical combination of regular polygons, straight lines and arcs.

[0013] Optionally, the conductive unit has the same material and thickness as the first signal line.

[0014] Optionally, the first signal line is a NECK trace, and the second signal line is a normal trace.

[0015] To achieve the above objectives, a second aspect of this application provides a circuit board, which includes the wiring structure described in any one of the above claims.

[0016] To achieve the above objectives, a third aspect of this application provides an electronic device, which includes the board. The printed circuit board routing structure, board, and electronic equipment provided in this application have at least the following beneficial effects: This application provides a trace structure for a printed circuit board, a board card, and an electronic device, including a PCB. The PCB includes multiple spaced first regions and a second region located between the multiple first regions. Each first region has multiple vias, multiple conductive units spaced apart from the vias, and first signal lines. The second region has second signal lines, and the linewidth of the second signal lines is greater than that of the first signal lines. By electrically connecting one end of the first signal line to a via in the first region, and avoiding other vias, extending through the conductive units into the second region, and electrically connecting it to one end of the second signal line extending into the first region, when the first signal lines from different first regions communicate at high speed via the second signal lines in the second region, the conductive units can locally amplify the linewidth of the first signal lines, matching the impedances of the first and second signal lines to improve return loss and crosstalk, ensuring the integrity of high-speed signal transmission, and improving the transmission quality of high-speed signals.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a PCB trace structure according to an embodiment of this application.

[0019] Figure 2 for Figure 1 A magnified schematic diagram of the structure of a portion of region A in the middle.

[0020] 100 PCB; 110 First area; 111 First signal line; 112 Via; 113 Conductive unit; 120 Second area; 121 Second signal line. Detailed Implementation

[0021] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0022] In recent years, the bandwidth of communication server systems has been increasing, and the signal rate on PCBs has been rising. To address the loss issues caused by this increased signal rate, PCB material grades have evolved to M8 and even M9 levels to keep up with the demands of high speed and high bandwidth, resulting in a significant increase in PCB costs. Since the transmission quality of high-speed signals is directly related to factors such as signal insertion loss, return loss, crosstalk, and radiation, upgrading PCB materials can reduce signal insertion loss, but it offers little improvement in other aspects. To address the cost issues arising from material upgrades, it is necessary to consider improving signal quality by reducing crosstalk and improving return loss, thereby reducing dependence on materials and insertion loss, and ultimately lowering the material cost of PCB materials.

[0023] BGA (Block Surface Mount Technology) is a high-density surface mount packaging technology. On the bottom of the package, the leads are spherical and arranged in a grid-like pattern. BGA packaging provides more pins than other packages such as Dual In-line Package (DIP) or Quad Flat Package (Quad Flat Package), allowing the entire bottom surface of the device to be used as pins, rather than just the perimeter. It also offers shorter average conductor lengths compared to perimeter-limited package types, resulting in better high-speed performance. Typically, a large number of vias are placed within the BGA package area. The main function of vias includes connecting the chip to the PCB; for high-speed signal transmission, proper via placement can reduce the distance between vias and signal pins, reducing crosstalk and latency.

[0024] Due to the influence of gold fingers and PCB thickness, the large number of vias in the BGA package area will also lead to an increase in the number of signal lines required in the corresponding area, an increase in trace density, and an increase in the difficulty of trace routing. In order to ensure the normal transmission of signals, the existing technology usually adjusts the trace width of the BGA package area, thus giving up the control of signal line impedance and signal line spacing. However, this kind of trace structure will affect the integrity and signal transmission quality of high-speed signal transmission.

[0025] Based on the above problems, this application provides a trace structure for a printed circuit board. By adding conductive units 113 in the gap between adjacent vias, the local width of the traces in the BGA package area is increased by the conductive units 113, thereby reducing impedance and crosstalk, improving the transmission quality of high-speed signals, and ensuring product performance.

[0026] According to one aspect of this application, a wiring structure for a printed circuit board is provided, such as... Figure 1 and Figure 2As shown, the routing structure includes a PCB 100, which includes multiple spaced first regions 110 and second regions 120 located between the multiple first regions 110. Each first region 110 has multiple arrayed vias 112, multiple conductive units 113 spaced apart from the vias 112, and first signal lines 111. The second region 120 has second signal lines 121, and the line width of the second signal lines 121 is greater than that of the first signal lines 111. One end of the first signal line 111 is electrically connected to one via 112 of the first region 110, while the other end avoids other vias 112 and extends through the conductive units 113 into the second region 120, where it is electrically connected to one end of the second signal line 121 extending into the first region 110.

[0027] Understandably, by setting the line width of the first signal line 111 to be smaller than that of the second signal line 121, the problem of difficult routing design and manufacturing caused by the small gap between vias 112 in the first region 110 can be solved. For example, the first signal line 111 is a NECK mode trace, i.e., a NECK trace, while the second signal line 121 is a normal trace.

[0028] When the first signal line 111 of different first regions 110 is electrically connected to the second signal line 121 of the second region 120 for high-speed signal transmission, the two different line widths of the first signal line 111 and the second signal line 121 will cause signal impedance discontinuity, thereby deviating from the characteristic impedance requirements of signal transmission and affecting the transmission quality and signal integrity of high-speed signals.

[0029] Therefore, by placing conductive units 113 between multiple vias 112, and maintaining a distance between each conductive unit 113 and each via 112, this application ensures that when one end of the first signal line 111 is electrically connected to one via 112 and the other end extends into the second region 120 while avoiding other vias 112, it inevitably passes through the conductive units 113 located between the vias 112. This allows different conductive units 113 to be connected in series by the first signal line 111, which is equivalent to locally enlarging the linewidth of the first signal line 111 at the corresponding position of the conductive unit 113. This avoids long-distance single-width routing of the first signal line 111 within the first region 110, thereby reducing the impact of impedance inconsistency on the high-speed signal transmission quality when the first signal line 111 and the second signal line 121 are transmitting signals at high speed.

[0030] Meanwhile, the conductive units 113 connected in series between the first signal lines 111 reduce the characteristic impedance of the first signal lines 111, thereby matching the impedances of the first signal lines 111 and the second signal line 121, which can also improve return loss. Furthermore, the conductive units 113 connected in series between adjacent first signal lines 111 can further improve edge coupling between adjacent first signal lines 111, thereby reducing crosstalk and further improving the transmission quality of high-speed signals.

[0031] It should be noted that the specific shape of the conductive unit 113 can be a regular shape with symmetry, such as a circle, ellipse, triangle, quadrilateral, trapezoid, or other regular polygons, as well as a combination of straight lines and arcs with symmetry. This application does not make specific limitations here, as long as the reflection problem caused by the impedance change between the first signal line 111 and the second signal line 112 can be reduced.

[0032] Meanwhile, the specific material used for the conductive unit 113 can be a metal material with excellent conductivity, such as gold, silver, or copper, and this application does not impose specific limitations on this. To reduce manufacturing costs or manufacturing process difficulty, the material and thickness of the first signal line 111 and the conductive unit 113 can be matched. That is, the first signal line 111 and the conductive unit 113 can be copper layers of the same thickness, disposed on the same layer and integrally connected.

[0033] Furthermore, the plurality of vias 112 in the first region 110 may be conductive vias electrically connected to the copper layer in the PCB 100, or they may be ground vias connected to the ground plane layer of the PCB 100. In other words, this application may not specifically limit the specific type of via 112 here.

[0034] In some embodiments, the first region 110 is a chip packaging region, and the second region 120 is an open area between the chip packaging regions. The chip packaging regions are provided with packaging chips, and the packaging chips are packaged in the chip packaging regions using BGA packaging technology.

[0035] The packaged chips in the chip packaging area include at least one CPU chip and multiple DDR chips, such as DRAM chips, and each packaged chip corresponds one-to-one with each chip packaging area.

[0036] The CPU chip and any DDR chip are connected one-to-one through the first signal line 111 in the first region 110 corresponding to the CPU chip, the first region 110 corresponding to the DDR chip, and the second signal line 121 in the second region 120 between the two first regions 110, so that high-speed signals can be transmitted between the CPU chip and the DDR chip.

[0037] Since DDR chips are parallel interfaces, most of the high-speed signals transmitted between the CPU chip and the DDR chip are single-ended signals. For differential signals, it is necessary to calculate the spacing of a set of narrow lines of the first signal line 111 that is close to the target impedance so that the impedance meets the requirements as much as possible.

[0038] It should be noted that this application does not specifically limit the location of the connection point between the first signal line 111 and the second signal line 121. For example, the connection point between the first signal line 111 and the second signal line 121 can be located in the first region 110 or in the second region 120.

[0039] According to a second aspect of this application, a circuit board is also provided, which includes the wiring structure described in any of the above embodiments.

[0040] According to a third aspect of this application, an electronic device is also provided, which includes the board described in the above embodiments.

[0041] In summary, this application provides a printed circuit board routing structure, board card, and electronic device, including a PCB 100. The PCB 100 includes a plurality of spaced first regions 110 and a second region 120 located between the plurality of first regions 110. The first regions 110 are provided with a plurality of vias 112, a plurality of conductive units 113 spaced apart from the vias 112, and a first signal line 111. The second region 120 is provided with a second signal line 121, and the line width of the second signal line 121 is greater than that of the first signal line 111. By electrically connecting one end of the first signal line 111 to a via 112 in the first region 110, and avoiding other vias 112, extending through the conductive unit 113 into the second region 120, and electrically connecting it to one end of the second signal line 121 extending into the first region 110, when the first signal lines 111 in different first regions 110 communicate at high speed through the second signal line 121 in the second region 120, the conductive unit 113 can locally enlarge the linewidth of the first signal line 111, so that the impedances of the first signal line 111 and the second signal line 121 are matched, thereby improving return loss and crosstalk, ensuring the integrity of high-speed signal transmission, and improving the transmission quality of high-speed signals.

[0042] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A trace structure for a printed circuit board, characterized in that, The circuit board includes a printed circuit board having multiple spaced-apart first regions and second regions located between the multiple first regions: wherein, The first region is provided with a plurality of vias arranged in an array, a plurality of conductive units spaced apart from the vias, and a first signal line; the second region is provided with a second signal line, the line width of the second signal line being greater than that of the first signal line; One end of the first signal line is electrically connected to one of the vias, and the other end avoids the other vias and extends through the conductive unit into the second region, and is electrically connected to one end of the second signal line extending into the first region.

2. The wiring structure according to claim 1, characterized in that, The first region is a chip packaging region, on which a packaging chip is provided. The packaging chip is packaged in the chip packaging region using ball-shaped lead grid array packaging technology.

3. The wiring structure according to claim 2, characterized in that, The packaged chip includes at least one CPU chip and multiple DDR chips, and each packaged chip corresponds one-to-one with each chip packaging area.

4. The wiring structure according to claim 3, characterized in that, The CPU chip and the DDR chip transmit electrical signals sequentially through the corresponding first signal line and second signal line.

5. The wiring structure according to claim 4, characterized in that, The electrical signal is a single-ended signal.

6. The wiring structure according to claim 1, characterized in that, The conductive unit is a symmetrical regular graphic, including one of the following: circle, ellipse, triangle, quadrilateral, trapezoid, regular polygon, or a symmetrical combination of straight lines and arcs.

7. The wiring structure according to claim 1, characterized in that, The conductive unit has the same material and thickness as the first signal line.

8. The wiring structure according to claim 1, characterized in that, The first signal line is a NECK trace, and the second signal line is a normal trace.

9. A circuit board, characterized in that, Includes the wiring structure described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the board as described in claim 9.

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