Circuit board

Abstract

The application discloses a circuit board, comprising a first plate surface and a second plate surface arranged oppositely, wherein a solder pad is arranged on the first plate surface; a via hole is arranged on the second plate surface, the via hole penetrates through the second plate surface, the first plate surface and the solder pad, and a filling layer is inserted into the via hole, the hole depth of the via hole along a first direction is greater than the thickness of the filling layer along the first direction, and the first direction is perpendicular to the first plate surface and the second plate surface. The embodiment is beneficial to realizing efficient heat dissipation of the circuit board and reducing the risk of tin leakage in the reflow soldering process.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and more particularly to a circuit board. Background Technology

[0002] As production standards for printed circuit boards (PCBs) in consumer electronics become increasingly stringent, improper handling of thermal pads can easily lead to solder leakage, resulting in reduced solder coverage and uneven solder distribution, thus affecting the PCB's surface mount yield. Simultaneously, the heat generated by power devices mounted on the pads during operation can cause a rapid rise in internal temperature. If this heat is not dissipated promptly, the devices will continue to overheat, impacting the reliability of electronic devices and potentially reducing the PCB's lifespan. However, in current technologies, it is difficult to simultaneously achieve both high surface mount yield and effective heat dissipation on PCB pads. Utility Model Content

[0003] This application provides a circuit board that facilitates efficient heat dissipation while reducing the risk of solder leakage during reflow soldering.

[0004] This application provides a circuit board, including: First board surface, the first board surface is provided with solder pads; The second board surface is disposed opposite to the first board surface. A via is formed on the second board surface. The via penetrates the second board surface, the first board surface, and the pad. A filler layer is inserted into the via. The depth of the via along a first direction is greater than the thickness of the filler layer along the first direction. The first direction is perpendicular to the first board surface and the second board surface.

[0005] In some embodiments of this application, the filling layer has a first end and a second end disposed opposite to each other along the first direction, the first end being spaced apart from the first plate surface, and the second end being flush with the second plate surface.

[0006] In some embodiments of this application, the hole depth of the via along the first direction is h1, and the thickness of the filling layer along the first direction is h2, where 1 / 4*h1≤h2≤1 / 2*h1.

[0007] In some embodiments of this application, a copper foil layer and a protective layer are stacked sequentially on the second board surface. The protective layer has a first opening window. The portion of the copper foil layer located in the first opening window is exposed through the first opening window. The protective layer includes a first covering portion located within the first opening window. The via is located on the first covering portion and sequentially penetrates the first covering portion, the copper foil layer, the second board surface, the first board surface, and the solder pad.

[0008] In some embodiments of this application, the first covering portion is circular, and the first covering portion is coaxially disposed with the through hole.

[0009] In some embodiments of this application, the diameter of the first covering portion is d1, and the diameter of the through hole is d2, where d1 > d2.

[0010] In some embodiments of this application, the diameter d1 of the first covering portion satisfies 0.5mm≤d1≤0.9mm; the aperture d2 of the through hole satisfies 0.3mm≤d2≤0.4mm.

[0011] In some embodiments of this application, an electrical connection line is provided on the second plate surface. The electrical connection line is spaced apart from the first opening window, and the minimum distance between the electrical connection line and the first opening window is d3, where d3 satisfies d3≥0.5mm.

[0012] In some embodiments of this application, a plurality of first covering portions are provided, the plurality of first covering portions are arranged at intervals, and at least one of the aforementioned through holes is provided on each first covering portion.

[0013] In some embodiments of this application, the protective layer includes a plurality of first covering groups and a plurality of second covering groups. The first covering group includes a plurality of first covering portions arranged at intervals along a second direction, and the second covering group includes a plurality of first covering portions arranged at intervals along a third direction, wherein the second direction is perpendicular to the third direction. Among them, a plurality of first coverage groups are arranged at intervals along the third direction, and a plurality of second coverage groups are arranged at intervals along the second direction.

[0014] In some embodiments of this application, the center distance between two adjacent vias in the first cover group is the same; the center distance between two adjacent vias in the second cover group is the same.

[0015] In some embodiments of this application, the center distance between two adjacent vias along the second direction and the third direction is d4, where d4 satisfies 0.6mm≤d4≤1mm.

[0016] In some embodiments of this application, the orthographic projection of the pad on the second board surface is located within the area where the first opening window is located.

[0017] In some embodiments of this application, the filler layer includes an ink layer.

[0018] Based on the circuit board in this embodiment, this embodiment establishes a more efficient heat conduction path by creating vias in the pad area and extending the vias through the circuit board. This allows the heat generated by the power devices during operation to be quickly transferred from the pad surface to the inner layer or second surface of the circuit board for heat dissipation, thus improving heat dissipation efficiency. Simultaneously, a filler layer is provided within the vias to partially plug them, leaving some unfilled hollow structures. This not only improves heat dissipation efficiency in the pad area of ​​the circuit board, but the filler layer also prevents solder paste leakage, preventing solder paste from seeping from the first surface to the second surface during reflow soldering, thus avoiding short circuits or cold solder joints caused by solder leakage. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the first board surface structure of a circuit board in one embodiment of this application; Figure 2 This is a schematic diagram of the second board surface structure of the circuit board in one embodiment of this application; Figure 3 This is a cross-sectional view of a portion of the circuit board in another embodiment of this application; Figure 4 This is a cross-sectional view of a portion of the circuit board in another embodiment of this application; Figure 5 for Figure 2 Enlarged structural diagram at point A; Figure 6 This is a schematic diagram of the structure within the first open window on the second plate surface in one embodiment of this application.

[0021] Figure label: 100. Circuit board; 10. First board surface; 11. Solder pads; 20. Second panel; 21. Copper foil layer; 22. Protective layer; 221. First opening; 222. First covering part; 223. First covering group; 224. Second covering group; 30. Via; 40. Filler layer; 41. First end; 42. Second end; L1, first direction; L2, second direction; L3, third direction. Detailed Implementation

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, a clear and complete description will be provided below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] Improper handling of thermal pads can easily lead to solder leakage, affecting the surface mount yield of the circuit board. Simultaneously, the heat generated by power devices mounted on the pads during operation can cause a rapid rise in internal temperature. If this heat is not dissipated in time, the devices will continue to heat up, affecting the reliability of electronic equipment and reducing the lifespan of the circuit board. Furthermore, during reflow soldering, the pads are prone to uneven temperatures, with higher temperatures in the center and lower temperatures at the edges, increasing the risk of cold solder joints. Therefore, it is difficult to simultaneously achieve surface mount yield, heat dissipation, and prevention of solder leakage on circuit board pads.

[0024] For the above situation, please refer to Figures 1-3 This application proposes a circuit board 100, including a first board surface 10 and a second board surface 20 disposed opposite to each other. The first board surface 10 is provided with a pad 11. The second board surface 20 is provided with a via 30, which penetrates the second board surface 20, the first board surface 10 and the pad 11. A filler layer 40 is inserted into the via 30. The depth of the via 30 along a first direction L1 is greater than the thickness of the filler layer 40 along the first direction L1. The first direction L1 is perpendicular to the first board surface 10 and the second board surface 20.

[0025] Specifically, pad 11 is used to mount power devices. Solder paste is applied to pad 11, and the power devices are soldered to the surface of pad 11 using solder paste. Via 30 penetrates pad 11 and extends to the second board surface 20. A fill layer 40 is located within the via 30 to partially fill the via 30. This prevents solder paste on pad 11 from leaking from the first board surface 10 to the second board surface 20 during the surface mount reflow process, thus avoiding short circuits or cold solder joints caused by solder leakage. The size of pad 11, the number of vias 30, and the arrangement of vias 30 can be matched according to actual needs, and no specific restrictions are imposed here.

[0026] It should be noted that the circuit board 100 is generally filled with insulating materials such as glass fiber epoxy resin. This material has a very low thermal conductivity, making it difficult for heat from the surface of the pads 11 to be effectively conducted through the material within the circuit board 100. The slow heat dissipation of the pads 11 creates significant thermal resistance, causing heat to accumulate at the pads 11 and affecting the normal operation of the power devices. In this embodiment, vias 30 are formed in the pad 11 area, penetrating the circuit board 100, to establish a more efficient heat conduction path. This allows the heat generated during the operation of the power devices to be quickly transferred from the surface of the pads 11 to the inner layer or the second surface 20 of the circuit board 100 for heat dissipation. In other words, the vias 30 in the pad 11 area are equivalent to heat-conducting pillars on the circuit board 100, directly conducting heat from the first surface 10 to the second surface 20, significantly reducing the thermal resistance on the pads 11 and improving heat dissipation efficiency. When the circuit board 100 is reflow soldered, the vias 30 help to make the temperature on the pads 11 uniformly distributed and the solder paste on the pads 11 melts synchronously, thereby reducing soldering defects and improving the surface mount yield.

[0027] For example, the thermal conductivity of the inner layer material of the circuit board 100, such as glass fiber epoxy resin, is approximately 0.3~0.4 W / (m·K). If the via 30 is not provided on the pad 11, the heat on the pad 11 will be conducted to the second board surface 20 through the glass fiber epoxy resin. At this time, the thermal resistance is extremely high (greater than 100℃ / W), which will cause the temperature of the power device on the pad 11 to rise rapidly, seriously affecting the reliability of the power device and even causing thermal failure. However, in this embodiment, by providing a through via 30, the thermal conductivity at the via 30 can be increased to more than 1000 times that of glass fiber epoxy resin. For example, the thermal conductivity at the via 30 is approximately 398 W / (m·K), which is beneficial for efficiently and quickly dissipating the heat on the pad 11.

[0028] Meanwhile, to prevent solder paste on pad 11 from overflowing into the second board surface 20 through via 30 during reflow soldering, causing solder leakage, a filler layer 40 is provided inside the via 30. This allows the via 30 to achieve efficient heat conduction, and the filler layer 40 also blocks solder leakage from pad 11, preventing solder paste from penetrating from the first board surface 10 to the second board surface 20 through via 30 during reflow soldering, thus avoiding short circuits or cold solder joints caused by solder leakage. Understandably, since the filler layer 40 also reduces the thermal conductivity of the via 30, the thickness of the filler layer 40 is less than the depth of the via 30, to perform a partial plugging operation on the via 30, leaving a portion of the via 30 with unfilled hollow structure. This allows the area of ​​pad 11 on the circuit board 100 to not only improve heat dissipation efficiency, but also for the filler layer 40 to prevent solder leakage from pad 11. Therefore, in this embodiment, the circuit board 100 can reduce the risk of solder leakage during the reflow soldering process by providing partially filled vias 30 in the area of ​​the pad 11.

[0029] The filler layer 40 can be made of a non-conductive material with better thermal conductivity than glass fiber epoxy resin. This not only provides electrical isolation but also offers higher thermal conductivity compared to the inner layer material of the circuit board 100 (such as glass fiber epoxy resin). For example, the filler layer 40 can be a resin material, which has good thermal conductivity, thus improving overall heat dissipation efficiency while maintaining good insulation performance. Alternatively, in some embodiments, the filler layer 40 includes an ink layer, as ink is low in cost and easy to process, thus reducing the manufacturing cost of the circuit board 100.

[0030] In some embodiments of this application, such as Figure 3 As shown, the hole depth of via 30 along the first direction L1 is h1, and the thickness of fill layer 40 along the first direction L1 is h2. The thickness h2 of fill layer 40 in via 30 satisfies 1 / 4*h1≤h2≤1 / 2*h1. This thickness range can effectively block solder paste penetration and retain sufficient hollow structure to maintain the high thermal conductivity at via 30, ensuring that heat is quickly transferred from the surface of pad 11 along via 30 to the heat dissipation structure of the second board surface 20.

[0031] Please see Figure 3 In some embodiments of this application, the filling layer 40 has a first end 41 and a second end 42 disposed opposite to each other along a first direction L1. The first end 41 is spaced apart from the first plate surface 10, and the second end 42 is flush with the second plate surface 20.

[0032] Specifically, the filler layer 40 fills from the second board surface 20 toward the first board surface 10, and its first end 41 does not extend to the first board surface 10. This creates a hollow structure on the side of the via 30 near the first board surface 10, ensuring that the thermal conductivity from the first board surface 10 to the first end 41 of the filler layer 40 is not affected by the filler material, maintaining high thermal conductivity. Meanwhile, the second end 42 is flush with the second board surface 20, ensuring that solder paste cannot continue to penetrate downwards during reflow soldering, effectively preventing solder leakage.

[0033] Please see Figure 2 and Figure 4 In some embodiments of this application, a copper foil layer 21 and a protective layer 22 are stacked sequentially on the second board surface 20. The protective layer 22 has a first opening window 221. The portion of the copper foil layer 21 located in the first opening window 221 is exposed through the first opening window 221. The protective layer 22 includes a first covering portion 222 located within the first opening window 221. A via 30 is located on the first covering portion 222. The via 30 sequentially penetrates the first covering portion 222, the copper foil layer 21, the second board surface 20, the first board surface 10, and the solder pad 11.

[0034] Specifically, Figure 2 The area covered by the grid lines is the protective layer 22 area, the blank area is the copper foil layer 21 area, and the black circular area is the via 30. The protective layer 22 is an insulating layer used for insulation and to protect the copper foil layer 21 from oxidation by air. A first opening 221 is added to the protective layer 22 on the second board surface 20, exposing the copper foil layer 21 at the first opening 221, thereby increasing the heat dissipation area of ​​the second board surface 20 and further improving the heat dissipation efficiency of the circuit board 100. Meanwhile, a protective layer 22, namely a first cover 222, is provided in the area of ​​the first opening window 221. The via 30 is located on the first cover 222 and penetrates the first cover 222. That is to say, on the second board surface 20, the periphery of the via 30 is surrounded by the first cover 222. Since a filling layer 40 needs to be provided in the via 30, if the periphery of the via 30 is not surrounded by the first cover 222, the filling layer 40 will easily block the copper foil layer 21 next to the via 30. Therefore, the first cover 222 can form an effective physical barrier between the edge of the via 30 and the copper foil layer 21, thereby improving the insulation reliability of the circuit board 100.

[0035] It should be noted that, as Figure 4As shown, the second end 42 of the filler layer 40 is flush with the first cover portion 222. That is, on the first board surface 10 away from the circuit board 100, the second end 42 of the filler layer 40 and the first cover portion 222 together form a flat surface, which facilitates the implementation of subsequent soldering processes. At the same time, this structural design can prevent the filler material of the filler layer 40 from overflowing into the copper foil layer 21 and causing a short circuit risk, and can also ensure that the bottom of the via 30 is completely sealed, effectively preventing solder paste from penetrating through the via 30 during reflow soldering.

[0036] Furthermore, such as Figure 2 As shown, the orthographic projection of pad 11 onto the second board surface 20 is located within the area of ​​the first opening window 221. Wherein, Figure 2 The dashed box in the diagram represents the orthographic projection of pad 11 onto the second board surface 20. Since the copper foil layer 21 is exposed in the area of ​​the first opening window 221, the orthographic projection of pad 11 falls completely into the exposed area. This allows the exposed copper foil layer 21 on the second board surface 20 to effectively participate in heat dissipation while the heat on pad 11 is being dissipated, thereby enhancing the continuity of the heat dissipation path and significantly improving the overall heat dissipation capacity of the circuit board 100.

[0037] Please see Figure 5 In some embodiments of this application, the first cover portion 222 is circular, and the first cover portion 222 is coaxially arranged with the via 30. That is, the circular first cover portion 222 is coaxially arranged with the via 30, which can ensure that the insulation area around the edge of the via 30 is evenly distributed, thereby improving the structural symmetry and reliability.

[0038] Furthermore, the diameter of the first cover portion 222 is d1, and the aperture of the via 30 is d2, where d1 > d2, so that the first cover portion 222 forms a complete insulating surrounding area around the via 30, and ensures that sufficient insulating spacing is maintained between the edge of the via 30 and the copper foil layer 21, thereby effectively improving the insulation reliability of the circuit board 100.

[0039] Furthermore, the diameter d1 of the first cover 222 satisfies 0.5mm≤d1≤0.9mm, and the aperture d2 of the through hole 30 satisfies 0.3mm≤d2≤0.4mm, to ensure sufficient insulation width around the through hole 30 while also considering processing accuracy and heat dissipation requirements. For example, the diameter d1 of the first cover 222 is 0.5mm, the aperture d2 of the through hole 30 is 0.3mm, and the through hole 30 is coaxially arranged with the first cover 222. In this case, the first cover 222 forms a continuous insulating ring with a width of 0.1mm around the through hole 30 to ensure insulation reliability.

[0040] In some embodiments of this application, an electrical connection line (not shown in the figure) is provided on the second board surface 20. The electrical connection line is spaced apart from the first opening window 221, and the minimum distance between the electrical connection line and the first opening window 221 is d3, where d3 ≥ 0.5 mm. It can be understood that the minimum distance d3 ≥ 0.5 mm between the electrical connection line and the first opening window 221 can prevent the risk of short circuit caused by the electrical connection line being too close to the exposed copper foil layer 21 of the first opening window 221, while ensuring the electrical safety of the circuit board 100 in high-density wiring scenarios.

[0041] like Figure 6 As shown, multiple first covering portions 222 are provided, and the multiple first covering portions 222 are arranged at intervals, and each first covering portion 222 is provided with at least one through hole 30.

[0042] Specifically, taking a first cover portion 222 with one via 30 as an example, multiple vias 30 can be provided on the same pad 11 to improve heat dissipation efficiency. In this case, multiple vias 30 are correspondingly provided on multiple first cover portions 222, and each via 30 is coaxially arranged with the corresponding first cover portion 222, thereby ensuring that each via 30 has a continuous and uniform insulating ring around it. Alternatively, in some embodiments, a first cover portion 222 is provided with multiple vias 30 arranged at intervals.

[0043] In some embodiments of this application, such as Figure 6 As shown, the protective layer 22 includes a plurality of first covering groups 223 and a plurality of second covering groups 224. The first covering group 223 includes a plurality of first covering portions 222 spaced apart along the second direction L2, and the second covering group 224 includes a plurality of first covering portions 222 spaced apart along the third direction L3. The second direction L2 is perpendicular to the third direction L3. The plurality of first covering groups 223 are spaced apart along the third direction L3, and the plurality of second covering groups 224 are spaced apart along the second direction L2. Figure 6 The dashed box extending along the second direction L2 in the middle is schematically the first coverage group 223. Figure 6 The dashed box extending from the third side to L3 is indicated as the second coverage group 224.

[0044] It is understandable that the second direction L2 and the third direction L3 are both parallel to the second plate surface 20, and the second direction L2 and the third direction L3 are perpendicular to each other. Taking the second direction L2 as the horizontal direction and the third direction L3 as the vertical direction as an example, multiple first covering groups 223 and multiple second covering groups 224 form a checkerboard-like staggered array structure, thereby optimizing the uniformity of heat dissipation path distribution while ensuring insulation reliability.

[0045] Furthermore, such as Figure 6As shown, the center distance between two adjacent vias 30 in the first covering group 223 is the same; the center distance between two adjacent vias 30 in the second covering group 224 is the same. That is to say, the array of vias 30 in the first opening window 221 region is uniformly and equally distributed in both the horizontal and vertical directions, making the distribution of vias 30 more balanced, which is conducive to efficient longitudinal conduction and lateral dissipation of heat.

[0046] Furthermore, along the second direction L2 and the third direction L3, the center distance between two adjacent vias 30 is d4, where d4 satisfies 0.6mm≤d4≤1mm, to ensure that there is an appropriate gap between two adjacent vias 30, and to avoid insulation layer breakage or thermal stress concentration due to excessive distance.

[0047] For example, the pad 11 is square and has a size of 2.5mm × 4mm. Multiple vias 30 are arranged in a square array in the pad 11. The diameter d2 of the vias 30 is 0.3mm, the diameter d1 of the first cover portion 222 is 0.5mm, and the center distance d4 between two adjacent vias 30 is 0.6mm.

[0048] In summary, during the manufacturing process of the circuit board 100 in this embodiment, vias 30 are first opened on the pads 11 of the circuit board 100, and then a portion of the protective layer 22 on the second board surface 20 is removed to form a first opening window 221 opposite to the position of the pads 11, exposing the copper foil layer 21 in the first opening window 221. Then, an insulating material is coated around the vias 30 in the first opening window 221 to form a first covering portion 222, thereby ensuring reliable electrical isolation between the vias 30 and the exposed copper foil layer 21, and facilitating the filling of ink material into the vias 30 to form an ink semi-plug structure in the vias 30.

[0049] In this process, under vacuum conditions, ink material is filled into the via 30, and the ink material is pre-baked at a preset temperature (e.g., 85°C) for a certain period of time (e.g., pre-baking for 15 minutes), and then left to stand for a period of time to remove air bubbles (e.g., standing for 30 minutes). Then, a leveling film is used to scrape off the excess ink material overflowing from the opening of the via 30. Subsequently, it is baked again to completely cure the ink material to form an ink layer.

[0050] In the accompanying drawings of this embodiment, the same or similar reference numerals correspond to the same or similar components. In the description of this application, it should be understood that if terms such as "upper," "lower," "left," and "right" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting this application. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0051] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A circuit board, characterized in that, The circuit board includes: First board surface, the first board surface is provided with solder pads; The second board surface is disposed opposite to the first board surface. A via is formed on the second board surface. The via penetrates the second board surface, the first board surface, and the pad. A filler layer is inserted into the via. The depth of the via along a first direction is greater than the thickness of the filler layer along the first direction. The first direction is perpendicular to the first board surface and the second board surface.

2. The circuit board according to claim 1, characterized in that, The filling layer has a first end and a second end disposed opposite to each other along the first direction, the first end being spaced apart from the first plate surface, and the second end being flush with the second plate surface.

3. The circuit board according to claim 1, characterized in that, The depth of the via along the first direction is h1, and the thickness of the filling layer along the first direction is h2, where 1 / 4*h1≤h2≤1 / 2*h1.

4. The circuit board according to claim 1, characterized in that, A copper foil layer and a protective layer are stacked sequentially on the second board surface. The protective layer has a first opening window. The portion of the copper foil layer located in the first opening window is exposed through the first opening window. The protective layer includes a first covering portion located within the first opening window. The via is located on the first covering portion and sequentially penetrates the first covering portion, the copper foil layer, the second board surface, the first board surface, and the solder pad.

5. The circuit board according to claim 4, characterized in that, The first covering portion is circular, and the first covering portion is coaxially arranged with the through hole.

6. The circuit board according to claim 5, characterized in that, The diameter of the first covering part is d1, and the diameter of the through hole is d2, where d1 > d2.

7. The circuit board according to claim 6, characterized in that, The diameter d1 of the first covering part satisfies 0.5mm ≤ d1 ≤ 0.9mm; The diameter d2 of the via satisfies 0.3mm≤d2≤0.4mm.

8. The circuit board according to claim 4, characterized in that, An electrical connection line is provided on the second plate surface. The electrical connection line is spaced apart from the first opening window, and the minimum distance between the electrical connection line and the first opening window is d3, where d3 satisfies d3≥0.5mm.

9. The circuit board according to claim 4, characterized in that, Multiple first covering portions are provided, and the multiple first covering portions are arranged at intervals, and each first covering portion is provided with at least one of the aforementioned through holes.

10. The circuit board according to claim 4, characterized in that, The protective layer includes a plurality of first covering groups and a plurality of second covering groups. The first covering group includes a plurality of first covering portions arranged at intervals along a second direction. The second covering group includes a plurality of first covering portions arranged at intervals along a third direction. The second direction is perpendicular to the third direction. Among them, a plurality of first coverage groups are arranged at intervals along the third direction, and a plurality of second coverage groups are arranged at intervals along the second direction.

11. The circuit board according to claim 10, characterized in that, The center distance between two adjacent vias in the first cover group is the same; the center distance between two adjacent vias in the second cover group is the same.

12. The circuit board according to claim 11, characterized in that, Along the second direction and the third direction, the center distance between two adjacent vias is d4, where d4 satisfies 0.6mm≤d4≤1mm.

13. The circuit board according to claim 4, characterized in that, The orthographic projection of the pad on the second board surface is located within the area of ​​the first opening window.

14. The circuit board according to claim 1, characterized in that, The filler layer includes an ink layer.

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