A stacked package device of memory chips

Abstract

The utility model discloses a kind of stacked packaging devices of memory chip, including wire carrier plate, the upper surface of wire carrier plate is equipped with shell, the upper surface of wire carrier plate is located inside the shell and is equipped with chip main body, the shell includes shell, heat-absorbing plate, heat-conducting plate, the side surface of shell is embedded and installed with heat-conducting plate, the side surface of heat-conducting plate is located inside shell and is embedded and installed with heat-absorbing plate, the heat-absorbing plate is multiple, the wire carrier plate includes plate body, metal ball, the lower surface of plate body is fixedly installed with metal ball, the metal ball is multiple, the shell is located above plate body, the chip main body includes first chip, bump, gold wire, second chip, the first chip is three groups.The stacked packaging device of memory chip of the utility model can stack and install chip, which is beneficial to reduce the occupied space and facilitate rapid heat dissipation.

Description

Technical Field

[0001] This utility model relates to the field of chip stacking and packaging, and in particular to a stacking and packaging device for memory chips. Background Technology

[0002] Stacked packaging devices for memory chips are the core technology for achieving high-density storage. By vertically stacking multiple chips and optimizing the interconnect structure, storage capacity and performance can be significantly improved in a limited space. Through continuous innovation in stacked packaging technology, memory chips are transforming from "capacity-driven" to "energy efficiency-driven". In the future, they will be deeply integrated into AI chips, autonomous driving and other scenarios, becoming the core infrastructure of the digital economy.

[0003] In order to improve the practicality of memory chips, more chips are needed during use. However, packaging multiple sets of chips results in large packaged chips that are inconvenient to use. During operation, memory chips generate heat, which accumulates inside the casing and can easily cause damage. Therefore, we propose a stacking packaging device for memory chips. Utility Model Content

[0004] The main objective of this invention is to provide a stacking and packaging device for memory chips, which can effectively solve the problems in the background art.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0006] A stacked packaging device for memory chips includes a wire carrier board, the upper surface of which is provided with a housing, and the upper surface of the wire carrier board is provided with a chip body inside the housing.

[0007] Furthermore, the outer shell includes a shell, a heat-absorbing plate, and a heat-conducting plate. A heat-conducting plate is embedded on one side surface of the shell, and a heat-absorbing plate is embedded on one side surface of the heat-conducting plate inside the shell. There are multiple sets of heat-absorbing plates.

[0008] Furthermore, the conductor carrier plate includes a plate body and metal balls, with multiple sets of metal balls fixedly installed on the lower surface of the plate body.

[0009] Furthermore, the housing is located above the plate.

[0010] Furthermore, the chip body includes a first chip, bumps, gold wires, and a second chip. The first chip consists of three groups. The first chip and the second chip, as well as the first chip and the first chip, can be connected by gold wires. The first chips are stacked on top of the second chips. The lower surface of the second chip is fixedly equipped with bumps, and there are multiple groups of bumps.

[0011] Furthermore, the protrusion is provided on the upper surface of the plate and located inside the shell.

[0012] In summary, due to the adoption of the above technical solution, the beneficial effects of this application are:

[0013] 1. The heat absorption plate and heat conduction plate can absorb heat from inside the shell, facilitating heat dissipation;

[0014] 2. By using gold wires, multiple chips can be stacked and assembled, which helps to reduce the area occupied. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall structure of this utility model;

[0016] Figure 2 This is a schematic diagram of the interior of the casing of this utility model;

[0017] Figure 3 This is a detailed drawing of the chip body of this utility model;

[0018] Figure 4 For the present utility model Figure 2 A magnified view of the details at point A.

[0019] In the diagram: 1. Outer shell; 101. Shell; 102. Heat absorber plate; 103. Heat conductor plate; 2. Wire carrier plate; 201. Plate body; 202. Metal ball; 3. Chip body; 301. First chip; 302. Bump; 303. Gold wire; 304. Second chip. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] Reference Figure 1-4 A stacked packaging device for memory chips includes a wire carrier board 2, a housing 1 on the upper surface of the wire carrier board 2, and a chip body 3 located inside the housing 1 on the upper surface of the wire carrier board 2.

[0022] Specifically, the chip body 3 is placed above the wire carrier board 2 and encapsulated inside the housing 1, with the housing 1 dissipating heat from the chip body 3.

[0023] In a preferred embodiment, the outer shell 1 includes a shell 101, a heat-absorbing plate 102, and a heat-conducting plate 103. The heat-conducting plate 103 is embedded and installed on one side surface of the shell 101, and the heat-absorbing plate 102 is embedded and installed on one side surface of the heat-conducting plate 103 inside the shell 101. There are multiple sets of heat-absorbing plates 102.

[0024] Specifically, heat is absorbed by the heat-absorbing plate 102 and conducted to the heat-conducting plate 103, where heat is dissipated. The housing 101 encloses the wire carrier plate 2, and multiple sets of heat-absorbing plates 102 absorb the heat inside the housing 101 and conduct it to the heat-conducting plate 103. Since the heat-conducting plate 103 is in contact with the outside, the heat absorber can achieve rapid heat dissipation. The main body that directly absorbs heat must have a high absorptivity and a low emissivity.

[0025] In a preferred embodiment, the conductor carrier 2 includes a plate 201 and metal balls 202. The metal balls 202 are fixedly installed on the lower surface of the plate 201, and there are multiple sets of metal balls 202.

[0026] Specifically, the metal ball 202 is connected to the board 201, the circuit of the board 201 is directly perforated to the other side, and then the metal ball 202 is implanted. The chip body 3 is connected to the outside through the metal ball 202.

[0027] In a preferred embodiment, the housing 101 is located above the plate 201;

[0028] Specifically, the shell 101 is fixed above the plate 201, so that the plate 201 is enclosed.

[0029] In a preferred embodiment, the chip body 3 includes a first chip 301, bumps 302, gold wires 303, and a second chip 304. There are three sets of first chips 301. The first chips 301 and the second chips 304, as well as the first chips 301 and the first chips 304, can be connected by gold wires 303. The first chips 301 are stacked on top of the second chips 304. The lower surface of the second chips 304 is fixedly equipped with bumps 302, and there are multiple sets of bumps 302.

[0030] Specifically, by placing the second chip 304 and the first chip 301 face down and connecting them to the bump 302, by having multiple sets of first chips 301 and second chips 304 communicate with each other, and by stacking the first chips 301 and the gold wire 303 together for encapsulation, space can be greatly saved. The first chip 301 and the second chip 304 are connected by the gold wire 303, thereby achieving communication.

[0031] In a preferred embodiment, the protrusion 302 is provided on the upper surface of the plate 201 and is located inside the housing 101;

[0032] Specifically, the circuit is connected by connecting the bump 302 to the board 201.

[0033] It should be noted that during use, the second chip 304 is first mounted on the board 201 via the bump 302, and the first chip 301 and the second chip 304, as well as the first chip 301 and the first chip 304, are connected by stacking, and the circuit is connected by gold wire 303. Electrical connections are pre-made in the board 201. In this way, the first chip 301 and the second chip 304 can be connected to the printed circuit board through the board 201. However, the stacked structure is more likely to accumulate heat. The heat generated is absorbed by the heat absorption plate 102 and transferred to the heat conduction plate 103 for heat dissipation.

[0034] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A stacking packaging device for memory chips, characterized in that: The device includes a wire carrier board (2), and a housing (1) is provided on the upper surface of the wire carrier board (2). A chip body (3) is provided inside the housing (1) on the upper surface of the wire carrier board (2). The housing (1) includes a shell (101), a heat absorber plate (102), and a heat conduction plate (103). A heat conduction plate (103) is embedded on one side surface of the shell (101). A heat absorber plate (102) is embedded on one side surface of the heat conduction plate (103) inside the shell (101). There are multiple sets of heat absorber plates (102).

2. The memory chip stacking and packaging device according to claim 1, characterized in that: The conductor carrier plate (2) includes a plate body (201) and metal balls (202). The metal balls (202) are fixedly installed on the lower surface of the plate body (201), and there are multiple sets of metal balls (202).

3. The memory chip stacking and packaging device according to claim 2, characterized in that: The housing (101) is located above the plate (201).

4. The memory chip stacking and packaging device according to claim 3, characterized in that: The chip body (3) includes a first chip (301), bumps (302), gold wires (303), and a second chip (304). The first chip (301) consists of three groups. The first chip (301) and the second chip (304) can be connected to each other and to each other through gold wires (303). The first chip (301) is stacked on top of the second chip (304). The lower surface of the second chip (304) is fixedly equipped with bumps (302), and there are multiple groups of bumps (302).

5. The memory chip stacking and packaging apparatus according to claim 4, characterized in that: The protrusion (302) is provided on the upper surface of the plate (201) and located inside the shell (101).

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