Hybrid interconnect memory chip package structure
Patent Information
- Application Number
- CN202522286915.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-29
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2035-10-29
AI Technical Summary
[0003]然而，现有的存储器，尤其是厚度＜50μm的超薄芯片的存储器，受限于键合区面积和水平互连引线长度，长引线导致的寄生电感（L）和电阻（R）在高频（≥6400Mbps LPDDR5/6）下引发严重信号振铃、延迟及串扰
[0016]与现有技术相比，本实用新型的封装结构中具有多个封装单元，每一封装单元中均具有一个重布线层，芯片的电极引脚和重布线层之间通过垂直引线或者导电柱电连接，有效缩短了信号的传递距离，且一个封装单元内相邻芯片同类型的电极引脚之间通过弧形键合线实现电连接，将垂直互联（垂直引线或第一导电柱）和水平互联（通过弧形键合线以及重布线层进行电连接）混合在一起，有效减少高频工作状态下信号的串扰和衰减，且弧形键合线可分散热机械应力，且有效降低了成本，提高了封装的良品率。另一方面，本实用新型在存储芯片封装结构的芯片堆叠层数过多或者高度过大时，通过重布线层和第二导电柱将存储芯片封装结构分隔为多个封装单元，使得每一封装单元中第一导电柱或垂直打线的长度可控，确保信号稳定，且使用重布线层和第二导电柱实现互联，相比于传统多个TSV技术实现互联工艺简单、厚度薄、成本低，具有良好的热膨胀系数，不会因为传统TSV技术中的硅中介层热膨胀系数（CTE）失配导致升温工况下时序漂移。
Smart Images
Figure CN224805330U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the semiconductor field, and more particularly to the packaging of memory chips. Background Technology
[0002] The demand for high-bandwidth, high-capacity, and miniaturized memory in mobile devices, HPC, and AI fields continues to rise, and LPDDR has become the mainstream solution due to its advantages of low power consumption and high performance.
[0003] However, existing memory, especially memory for ultra-thin chips with a thickness of <50μm, is limited by the bonding area and the length of horizontal interconnect leads. The parasitic inductance (L) and resistance (R) caused by long leads lead to serious signal ringing, delay and crosstalk at high frequencies (≥6400Mbps LPDDR5 / 6).
[0004] Therefore, there is an urgent need for a memory chip packaging structure that can solve the above problems. Utility Model Content
[0005] The purpose of this invention is to provide a hybrid interconnect memory chip packaging structure. By directly connecting vertical leads or conductive pillars to the redistribution layer and combining them with arc-shaped bonding lines between chips, high-density lead-out of all electrode pins is achieved, effectively shortening the signal transmission path, reducing signal crosstalk and attenuation, and dispersing thermomechanical stress.
[0006] To achieve the above objectives, this utility model provides a hybrid interconnect memory chip packaging structure, including multiple packaging units. Each packaging unit includes a redistribution layer, one or more chip stacking units, electrical connection components, and a packaging layer. Each chip stacking unit consists of multiple chips stacked sequentially and staggered on one side of the redistribution layer, and the multiple chips include multiple memory chips. The electrical connection components include arc-shaped bonding wires soldered between electrode pins of the same type between adjacent chips, and vertical leads or first conductive pillars soldered between the electrode pins of the chips and the redistribution layer. The packaging layer encapsulates the chip stacking units and electrical connection components on the redistribution layer. The multiple packaging units are stacked sequentially, and a second conductive pillar is provided between the redistribution layers of adjacent packaging units to achieve electrical connection between adjacent packaging units.
[0007] Preferably, one of the packaging units further includes a logic chip located above the redistribution layer and electrically connected to the redistribution layer of the packaging unit in which it is located.
[0008] Specifically, in each of the packaging units, the redistribution layer is located on the lower side of the packaging unit; the logic chip is located in the bottommost packaging unit, so that the signals of the logic chip can be transmitted quickly.
[0009] Preferably, the logic chip and the redistribution layer are electrically connected via a first metal microbump. This technology uses a first metal microbump to achieve metal interconnection between the logic chip and the redistribution layer, significantly reducing high-frequency impedance fluctuations of the logic chip.
[0010] Preferably, in the chip stacking unit, the chip closest to the redistribution layer of its own packaging unit is electrically connected to the redistribution layer via a second metal microbump on its electrode pin or by vertical wire bonding. This technology uses metal microbumps to achieve metal interconnection between the nearest chip and the redistribution layer, reducing the thickness of the packaging unit, improving signal propagation stability between the chip and the redistribution layer, and reducing high-frequency impedance fluctuations.
[0011] Preferably, each of the packaging units has a plurality of chip stacking units, and the plurality of chip stacking units are disposed above the redistribution layer at intervals between each other.
[0012] More preferably, one of the packaging units further includes a logic chip located above the redistribution layer and electrically connected to the redistribution layer of the packaging unit in which it is located, and each packaging unit has an even number of chip stacking units, and the even number of chip stacking units are symmetrically arranged relative to the logic chip.
[0013] Preferably, in each of the packaging units, the redistribution layer is located on the lower side of the packaging unit; the outer side of the redistribution layer of the lowest layer of the memory chip packaging structure is provided with an external solder joint that is electrically connected to the internal circuitry of the redistribution layer. This external solder joint is a solder ball (e.g., a solder ball) or an electrical connection bump.
[0014] Preferably, each of the chip stacking units has 4-8 layers of stacked chips.
[0015] Preferably, both the first and second conductive pillars are made of copper. However, the materials for both the first and second conductive pillars can be other metals, not limited to copper.
[0016] Compared with the prior art, the packaging structure of this utility model has multiple packaging units, each of which has a redistribution layer. The electrode pins of the chip and the redistribution layer are electrically connected through vertical leads or conductive pillars, which effectively shortens the signal transmission distance. Furthermore, the electrode pins of the same type of adjacent chips within a packaging unit are electrically connected through arc-shaped bonding wires. This combines vertical interconnection (vertical leads or first conductive pillars) and horizontal interconnection (electrically connected through arc-shaped bonding wires and redistribution layers), effectively reducing crosstalk and attenuation of signals under high-frequency operating conditions. The arc-shaped bonding wires can also disperse thermomechanical stress, effectively reducing costs and improving the packaging yield. On the other hand, when the number of chip stacking layers in the memory chip packaging structure is too large or the height is too large, this utility model divides the memory chip packaging structure into multiple packaging units by using a redistribution layer and a second conductive pillar. This makes the length of the first conductive pillar or vertical bonding wire in each packaging unit controllable, ensuring signal stability. Furthermore, the interconnection is achieved using a redistribution layer and a second conductive pillar. Compared with the traditional interconnection process using multiple TSV technologies, this method is simpler, thinner, and lower in cost. It also has a good coefficient of thermal expansion and will not cause timing drift under heating conditions due to the mismatch of the coefficient of thermal expansion (CTE) of the silicon interposer in the traditional TSV technology. Attached Figure Description
[0017] Figure 1 This is a diagram of the hybrid interconnect memory chip packaging structure of this utility model.
[0018] Figure label: The memory chip packaging structure 100 includes a packaging unit 10, a carrier board 11, a chip stacking unit 20, a chip 21, a logic chip 22, an electrical connection component 30, a vertical lead 31, an arc bonding wire 32, a second metal microbump 33, a second conductive post 34, a first metal microbump 35, a packaging layer 40, a redistribution layer 50, and solder balls 60. Detailed Implementation
[0019] To explain in detail the technical content, structural features, objectives and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0020] refer to Figure 1 This utility model discloses a hybrid interconnect memory chip packaging structure 100. The memory chip packaging structure 100 includes multiple packaging units 10. In this embodiment, there are four packaging units 10. Of course, unlike this embodiment, the number of packaging units 10 can also be two, three, five, etc.
[0021] refer to Figure 1Each packaging unit 10 includes a redistribution layer 50, a chip stacking unit 20, an electrical connection component 30, and a packaging layer 40. The chip stacking unit 20 is located on one side of the redistribution layer 50 and is electrically connected to the redistribution layer 50 through the electrical connection component 30. The packaging layer 40 wraps the chip stacking unit 20 and the electrical connection component 30 around the redistribution layer 50.
[0022] refer to Figure 1 The chip stacking unit 20 consists of multiple chips 21 stacked sequentially and staggered on one side of the redistribution layer 50, and the multiple chips 21 include at least multiple memory chips. The chip 21 has electrode pins, including a data signal pin (DQ), a command / address signal pin (CA), a clock signal pin (CK), a power supply pin (VDD / VDDQ), and a ground pin (VSS / VSSQ).
[0023] In this embodiment, chip 21 is a thinned chip, formed by thinning and dicing a wafer. In this embodiment, the chip stacking unit 20 is formed by stacking multiple memory chips in a staggered manner. In contrast, in another embodiment, the chip stacking unit 20 can also be formed by stacking multiple memory chips and a management chip in a staggered manner.
[0024] refer to Figure 1 The electrical connection assembly 30 includes an arc-shaped bonding wire 32 soldered between electrode pins of the same type of adjacent chips 21 within the same package unit 10, and a vertical lead 31 soldered between the electrode pins of the chip 21 and the redistribution layer 50.
[0025] In this embodiment, the arc-shaped bonding wire 32 is a metal wire such as copper or gold, and the vertical lead 31 is a lead perpendicular to the surface where the electrode pins of the chip 21 are located, fabricated using a vertical wire bonding process. Of course, the vertical lead 31 can be replaced by a conductive post, for example, by electrically connecting the electrode pins of the chip 21 and the redistribution layer 50 together through a first conductive post. This first conductive post can be fabricated using an electroplating process, or it can be directly vertically soldered onto a metal post or metal wire, or adhered to the electrode pin using conductive adhesive. A copper post is preferred for this first conductive post.
[0026] Preferably, in the chip stack unit 20, the chip 21 closest to its own redistribution layer 50 is electrically connected to the redistribution layer 50 via a second metal microbump 33 (made by gold ball bump technology) on its electrode pin. Of course, the chip 21 closest to the redistribution layer 50 can also be electrically connected to the redistribution layer 50 via vertical wire bonding.
[0027] Preferably, each packaging unit 10 has multiple chip stacking units 20, and the multiple chip stacking units 20 are symmetrically arranged. Of course, the multiple chip stacking units 20 are not limited to a symmetrical arrangement. In this embodiment, each packaging unit 10 has two chip stacking units 20, and each chip stacking unit 20 stacks eight layers of chips 21. Of course, the number of layers of chips stacked in the chip stacking unit 20 is not limited to eight layers, and can be two layers, three layers, etc., with four to eight layers being preferred.
[0028] Continue to refer to Figure 1 Multiple packaging units 10 are stacked sequentially, and second conductive pillars 34 are provided between the redistribution layers 50 of adjacent packaging units 10 to achieve electrical connection between adjacent packaging units 10. Each packaging unit 10 that is directly physically connected to the redistribution layer 50 of another packaging unit 10 is provided with multiple second conductive pillars 34, thereby guiding signals to the redistribution layer 50 located on the surface of the entire memory chip packaging structure 100 through the second conductive pillars 34 penetrating each packaging unit 10. In this embodiment, the second conductive pillars 34 are copper pillars; however, other metals can also be used.
[0029] Preferably, one of the packaging units 10 further includes a logic chip 22, wherein the logic chip 22 is spaced from the chip stack unit 20 of the packaging unit 10 to one side of the redistribution layer 50, and is electrically connected to the redistribution layer 50 through a first metal microbump 35 on the electrode pin of the logic chip 22.
[0030] Each of the packaging units 10 has an even number of chip stacking units 20 (e.g., two chip stacking units 20), and the even number of chip stacking units 20 are symmetrically arranged relative to the logic chip 22 to ensure that the horizontal distance from the logic chip 22 to the same level chip 21 in different chip stacking units 20 is consistent, thereby reducing signal delay and optimizing the synchronization of signal transmission between different chip stacking units 20 and the logic chip 22.
[0031] refer to Figure 1 The redistribution layer 50 is located below the packaging layer 40, and the redistribution layer 50 below the bottommost packaging unit 10 is formed on the lower surface of the memory chip packaging structure 100. The outer side of the redistribution layer 50 of the bottommost packaging unit 10 has an external solder portion 60 that is electrically connected to the circuitry within the redistribution layer 50. This external solder portion 60 is a solder ball (e.g., a solder ball).
[0032] In this embodiment, the packaging unit 10 with the logic chip 22 is the bottommost packaging unit 10. The logic chip 22 is electrically connected to the bottommost redistribution layer 50 through the first metal microbump 35 (made by gold ball bump technology), thereby quickly transmitting the signals of the logic chip 22 according to the redistribution layer 50 on the surface of the memory chip packaging structure 100. Of course, the packaging unit 10 with the logic chip 22 can be other packaging units 10, such as the middle packaging unit 10 or the topmost packaging unit 10.
[0033] Of course, the logic chip 22 can also be located outside the chip package structure 100, and then interconnected with the logic chip 22 after the chip package structure 100 is manufactured.
[0034] Compared with the prior art, the packaging structure of this utility model has one or more packaging units 10, and each packaging unit 10 has a redistribution layer 50. The electrode pins of the chip 21 and the redistribution layer 50 are electrically connected through vertical leads 31 or first conductive pillars, which effectively shortens the signal transmission distance. In addition, the electrode pins of the same type of adjacent chips in a packaging unit 10 are electrically connected through arc-shaped bonding wires 32, which combines vertical interconnection (vertical leads 31 or first conductive pillars) and horizontal interconnection (electrically connected through arc-shaped bonding wires 32 and redistribution layer 50), effectively reducing crosstalk and attenuation of signals under high-frequency operating conditions. The arc-shaped bonding wires 32 can disperse thermomechanical stress. On the other hand, when the number of chip stacking layers in the memory chip packaging structure 100 is too large or the height is too large, the present invention divides the memory chip packaging structure 100 into multiple packaging units 10 by using the redistribution layer 50 and the second conductive pillar 34. This makes the length of the vertical lead 31 or the first conductive pillar in each packaging unit 10 controllable, ensuring signal stability. Furthermore, the interconnection is achieved using the redistribution layer 50 and the second conductive pillar 34. Compared with the traditional multiple TSV technology interconnection process, this method is simple, thin, and low-cost, and has a good coefficient of thermal expansion. It will not cause timing drift under heating conditions due to the mismatch of the coefficient of thermal expansion (CTE) of the silicon interposer in the traditional TSV technology.
[0035] In this invention, "up" and "down" are relative positions, not absolute positions.
[0036] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the scope of the present utility model shall still fall within the scope of the present utility model.
Claims
1. A hybrid interconnect memory chip packaging structure, characterized in that: It includes multiple packaging units, each of which includes: Rewire layer; One or more chip stacking units, wherein multiple chips are stacked sequentially and staggered on one side of the redistribution layer, and the multiple chips include multiple memory chips; Electrical connection components include arc-shaped bonding wires soldered between electrode pins of the same type adjacent to the chip, and vertical leads or first conductive posts soldered between the electrode pins of the chip and the redistribution layer. An encapsulation layer encapsulates the chip stacking unit and electrical connection components on the redistribution layer; Multiple packaging units are stacked sequentially, and a second conductive post is provided between the redistribution layers of adjacent packaging units to achieve electrical connection between adjacent packaging units.
2. The hybrid interconnect memory chip packaging structure as described in claim 1, characterized in that: One of the packaging units further includes a logic chip, which is electrically connected to the redistribution layer of the packaging unit in which it resides.
3. The hybrid interconnect memory chip packaging structure as described in claim 2, characterized in that: In each of the packaging units, the redistribution layer is located on the lower side of the packaging unit; the logic chip is located in the bottommost packaging unit.
4. The hybrid interconnect memory chip packaging structure as described in claim 2, characterized in that: The logic chip and the redistribution layer are electrically connected via a first metal microbump.
5. The hybrid interconnect memory chip packaging structure as described in claim 1, characterized in that: In the chip stacking unit, the chip closest to the redistribution layer of its own packaging unit is electrically connected to the redistribution layer through a second metal microbump on the electrode pin or by vertical wire bonding.
6. The hybrid interconnect memory chip packaging structure as described in claim 1, characterized in that: Each of the packaging units has multiple chip stacking units, and the multiple chip stacking units are disposed above the redistribution layer at intervals.
7. The hybrid interconnect memory chip packaging structure as described in claim 6, characterized in that: One of the packaging units further includes a logic chip, which is located above the redistribution layer and electrically connected to the redistribution layer of the packaging unit. Each packaging unit has an even number of chip stacking units, and the even number of chip stacking units are symmetrically arranged relative to the logic chip.
8. The hybrid interconnect memory chip packaging structure as described in claim 1, characterized in that: In each of the aforementioned packaging units, the redistribution layer is located on the lower side of the packaging unit; the outer side of the redistribution layer of the lowest layer of the memory chip packaging structure is provided with an external solder joint that is electrically connected to the internal circuitry of the redistribution layer.
9. The hybrid interconnect memory chip packaging structure as described in claim 1, characterized in that: Each of the chip stacking units contains 4-8 layers of stacked chips.
10. The hybrid interconnect memory chip packaging structure as described in claim 1, characterized in that: The first conductive post is a copper post, and the second conductive post is a copper post.