Trench-type silicon carbide transistor

CN224805331UActive Publication Date: 2026-09-25REASUNOS SEMICON TECH CO LTD
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Patent Information

Application Number
CN202522143963.3
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-10-10
Publication Date
2026-09-25
Estimated Expiration
2035-10-10

AI Technical Summary

Technical Problem

[0002]沟槽型碳化硅晶体管是一种基于碳化硅材料的半导体器件,沟槽是指在半导体衬底上刻蚀出深沟槽,并在沟槽内形成晶体管的源极、栅极和漏极,沟槽结构可以显著提高晶体管的单位面积电流密度,从而实现更高的功率密度,现有技术中:授权公布号CN218123412 U的专利公开了涉及一种沟槽型碳化硅晶体管,包括第一掺杂类型的碳化硅衬底,碳化硅衬底包括第一表面,第一表面上设置有第一掺杂类型的外延层;设置在外延层内的第二掺杂类型的阱区;设置在阱区内的栅极沟槽结构,栅极沟槽结构包括覆盖于栅极沟槽结构的表面的栅极氧化层,以及位于栅极沟槽结构的底部的栅极氧化层之上的栅极和PN结结构,该器件的沟槽形状为矩形,矩形沟槽的角部和边缘会导致电场集中,增加电场应力,降低器件的耐压能力,电场集中则会导致器件局部击穿和局部过热,降低器件的可靠性和寿命,为此,我们提出沟槽型碳化硅晶体管

Benefits of technology

[0012]与现有技术相比,本实用新型的有益效果是:本沟槽型碳化硅晶体管,具有以下好处:

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Abstract

The utility model discloses a trench type silicon carbide transistor, including the pipe body still includes the conductive mechanism, the conductive mechanism: it includes epitaxial layer, V type trench, insulating layer, grid and doping layer no.
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Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to trench silicon carbide transistors. Background Technology

[0002] A trench silicon carbide transistor (SCT) is a semiconductor device based on silicon carbide. A trench refers to a deep trench etched into a semiconductor substrate, within which the source, gate, and drain of the transistor are formed. The trench structure can significantly increase the current density per unit area of ​​the transistor, thereby achieving higher power density. (Prior art: Authorization publication number CN218123412) U's patent discloses a trench-type silicon carbide transistor, including a silicon carbide substrate of a first doping type, the silicon carbide substrate including a first surface, an epitaxial layer of the first doping type disposed on the first surface; a well region of the second doping type disposed within the epitaxial layer; a gate trench structure disposed within the well region, the gate trench structure including a gate oxide layer covering the surface of the gate trench structure, and a gate and PN junction structure above the gate oxide layer at the bottom of the gate trench structure. The trench shape of the device is rectangular. The corners and edges of the rectangular trench will cause electric field concentration, increase electric field stress, and reduce the breakdown voltage of the device. Electric field concentration will lead to local breakdown and local overheating of the device, reducing the reliability and lifespan of the device. Therefore, we propose a trench-type silicon carbide transistor. Utility Model Content

[0003] The technical problem to be solved by this utility model is to overcome the existing defects and provide a trench silicon carbide transistor. By combining V-shaped trenches and multiple sets of doped layers, the current path in the transistor can be optimized using the doped layers, making the electric field more uniform. The V-shaped trenches can also more effectively disperse the electric field. The uniform electric field distribution can reduce electric field stress and reduce electric field concentration. This solves the problem of local breakdown and local overheating of trench silicon carbide transistors caused by electric field concentration, improves the reliability and lifespan of the device, and can effectively solve the problems in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a trench silicon carbide transistor, including a transistor body and a conductive mechanism;

[0005] Conductive structure: It includes an epitaxial layer, V-grooves, an insulating layer, a gate, and a first doped layer. The epitaxial layer is disposed inside the tube body. V-grooves are respectively disposed on the upper side of the epitaxial layer. An insulating layer is disposed inside each of the two sets of V-grooves. A gate is disposed inside each of the two sets of insulating layers. The first doped layer is disposed on the upper end of the epitaxial layer. The first doped layer is located between the front and rear sides of the tube body and the end of the two V-grooves near the center of the tube body. Through the combination of V-grooves and multiple sets of doped layers, the current path inside the tube body can be optimized by using the doped layers to make the electric field more uniform. The V-grooves can also more effectively disperse the electric field. The uniform electric field distribution can reduce electric field stress and reduce electric field concentration. It solves the problem of local breakdown and local overheating of trench silicon carbide transistors caused by electric field concentration, and improves the reliability and lifespan of the device.

[0006] Furthermore, the conductive mechanism also includes a source electrode, which is disposed at the upper end of the tube body. The upper ends of the two insulating layers are in contact with the lower end of the source electrode. The source electrode serves as the input end of the current, providing electron injection into the V-groove.

[0007] Furthermore, the conductive mechanism also includes a drain electrode, which is disposed on the lower side inside the tube body. The drain electrode serves as the output terminal of the current and collects electrons flowing out from the V-shaped trench.

[0008] Furthermore, the conductive mechanism also includes a second doped layer, which is disposed at the lower end of the epitaxial layer to smooth the electric field transition and prevent sudden changes in the electric field between the epitaxial layer and the substrate.

[0009] Furthermore, the conductive mechanism also includes a third doped layer, which is disposed at the upper end of the drain electrode. This third doped layer can disperse the electric field, reduce electric field concentration, and prevent local breakdown.

[0010] Furthermore, a substrate is disposed between the lower end of the second doped layer and the upper end of the third doped layer. The substrate provides mechanical support and electrical foundation to ensure the stability and performance of the device.

[0011] Furthermore, each of the V-shaped grooves is provided with an anti-oxidation layer, and the inner surface of the anti-oxidation layer is fixedly connected to the outer surface of the vertically adjacent insulating layer. The anti-oxidation layer can prevent the insulating layer from being corroded.

[0012] Compared with the prior art, the beneficial effects of this utility model are as follows: This trench-type silicon carbide transistor has the following advantages:

[0013] By combining V-grooves and multiple sets of doped layers, the current path within the transistor can be optimized using the doped layers, making the electric field more uniform. The V-grooves can also more effectively disperse the electric field. The uniform electric field distribution can reduce electric field stress and reduce electric field concentration, solving the problem of local breakdown and local overheating in trench silicon carbide transistors caused by electric field concentration, thereby improving the reliability and lifespan of the device. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of this utility model;

[0015] Figure 2 This is a schematic cross-sectional view of the right side of this utility model;

[0016] Figure 3 This is a schematic diagram of the conductive mechanism of this utility model;

[0017] Figure 4 This is a schematic diagram of the cross-sectional planar structure on the right side of this utility model;

[0018] Figure 5 This is an enlarged structural diagram of point A in this utility model.

[0019] In the figure: 1 tube body, 2 conductive mechanism, 21 epitaxial layer, 22 V-groove, 23 insulating layer, 24 gate, 25 source, 26 drain, 27 doped layer one, 28 doped layer two, 29 doped layer three, 3 substrate, 4 anti-oxidation layer. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] Please see Figure 1-5 This embodiment provides a technical solution: a trench silicon carbide transistor, including a transistor body 1 and a conductive mechanism 2;

[0022] Conductive mechanism 2 includes an epitaxial layer 21, V-grooves 22, an insulating layer 23, a gate 24, and a doped layer 271. The epitaxial layer 21 is disposed inside the tube body 1. V-grooves 22 are respectively disposed on the upper side of the epitaxial layer 21. An insulating layer 23 is disposed inside each of the two sets of V-grooves 22. A gate 24 is disposed inside each of the two sets of insulating layers 23. The doped layer 271 is disposed on the upper end of the epitaxial layer 21. The doped layer 271 is located between the front and rear sides of the tube body 1 and the end of the two V-grooves 22 near the center of the tube body 1. Conductive mechanism 2 also includes a source electrode 25, which is disposed at the upper end of the tube body 1. The upper ends of the two insulating layers 23 are in contact with the lower ends of the source electrode 25. Conductive mechanism 2 also includes... The transistor includes a drain 26, which is located on the lower side inside the transistor body 1. The conductive mechanism 2 also includes a second doped layer 28, located at the lower end of the epitaxial layer 21, and a third doped layer 29, located at the upper end of the drain 26. The epitaxial layer 21 is primarily made of silicon carbide and serves as the active region of the transistor, providing pathways for electron and hole transport. The insulating layer 23 is primarily made of silicon nitride and isolates the gate 24 from the V-groove 22, preventing leakage current and ensuring high switching speed and low leakage current. The gate 24 is primarily made of polysilicon and controls the conductivity of the V-groove 22 by applying voltage, thus enabling the transistor's switching function. The source 25... The primary materials are aluminum or titanium. The source electrode 25 serves as the current input terminal, providing electrons for injection into the V-groove 22. The drain electrode 26 is also primarily made of aluminum or titanium, serving as the current output terminal and collecting electrons flowing out of the V-groove 22. Doped layers 27, 28, and 29 are formed by doping silicon carbide with impurities. When donor impurities are doped, they (such as phosphorus or arsenic) provide additional free electrons to the silicon carbide, increasing the electron concentration. These free electrons can move under the influence of an electric field, thus affecting the electric field distribution. When acceptor impurities are doped, they (such as boron) capture electrons from the semiconductor material, generating holes and increasing the hole concentration. These holes can also move under the influence of an electric field. The movement of doped layers affects the electric field distribution. In semiconductor devices, the electric field is mainly determined by the distribution of charge carriers (electrons and holes). Doped layers 1-27, 2-28, and 3-29 can change the charge distribution by altering the charge carrier concentration, thus affecting the formation of the electric field. High doping concentration results in a high charge carrier concentration, allowing for a rapid response to external electric fields and improving the dynamic performance of the device. Low doping concentration results in a low charge carrier concentration and a more uniform electric field distribution, which can effectively improve the breakdown voltage of the device. Doped layer 1-27 has a high doping concentration (high doping concentration usually refers to 10 to 10 to 121 impurity atoms per cubic centimeter), which allows for a rapid response to external electric fields and provides low-resistance electrical contacts.This design ensures efficient current transmission and optimizes the electric field distribution through cooperation with the low-doped layer. The second doped layer 28 has a medium doping concentration (typically 10^16 to 10^18 impurity atoms per cubic centimeter), which smooths the electric field transition and prevents sudden changes in the electric field between the epitaxial layer 21 and the substrate 3. The third doped layer 29 has a low doping concentration (meaning 10^15 to 10^17 impurity atoms per cubic centimeter), which disperses the electric field, reduces electric field concentration, prevents local breakdown, improves the device's withstand voltage, and makes the electric field more uniform. The V-groove 22 can also disperse the electric field more effectively. The uniform electric field distribution reduces electric field stress and electric field concentration, solving the problem of local breakdown and overheating in trench silicon carbide transistors caused by electric field concentration, thus improving the device's reliability and lifespan.

[0023] Among them, a substrate 3 is disposed between the lower end of the second doped layer 28 and the upper end of the third doped layer 29. The substrate 3 provides mechanical support and electrical foundation to ensure the stability and performance of the device and has good electrical and thermal properties.

[0024] Among them, the interior of the V-shaped groove 22 is provided with an anti-oxidation layer 4. The inner surface of the anti-oxidation layer 4 is fixedly connected to the outer surface of the vertically adjacent insulating layer 23. The main material of the anti-oxidation layer 4 is silicon dioxide. The anti-oxidation layer 4 can prevent the insulating layer 23 from being corroded.

[0025] The working principle of the trench silicon carbide transistor provided by this utility model is as follows: The main material of the epitaxial layer 21 is silicon carbide, which provides a channel for the transport of electrons and holes. The main material of the insulating layer 23 is silicon nitride, which isolates the gate 24 and the V-groove 22 to prevent current leakage. The main material of the gate 24 is polysilicon, which controls the conductivity of the V-groove 22 by applying voltage, thereby realizing the switching function of the transistor. The main material of the source 25 is aluminum or titanium, which serves as the current input terminal, providing electrons to be injected into the V-groove 22. The main material of the drain 26 is also aluminum or titanium, which serves as the current output terminal, collecting electrons flowing out of the V-groove 22. The doping layer 27... Layer 28 and layer 3 are formed by doping silicon carbide with impurities. When donor impurities are doped, they (such as phosphorus and arsenic) provide additional free electrons to the silicon carbide, increasing the electron concentration. These free electrons can move under the influence of an electric field, thus affecting the electric field distribution. When acceptor impurities are doped, they (such as boron) capture electrons from the semiconductor material, generating holes and increasing the hole concentration. These holes can also move under the influence of an electric field, thus affecting the electric field distribution. In semiconductor devices, the electric field is mainly determined by the distribution of charge carriers (electrons and holes). By changing the charge carrier concentration, layers 27, 28, and 29 can alter the charge distribution, thereby affecting the formation of the electric field. High doping concentrations... High carrier concentration in the low-doped layer allows for rapid response to external electric fields, thus improving the dynamic performance of the device. The low carrier concentration in the low-doped layer results in a more uniform electric field distribution because the fewer carriers in the low-doped layer have a weaker neutralizing effect on the electric field, allowing for a more uniform distribution throughout the region. Doped layer 27 has a high doping concentration (high doping concentration typically refers to 10^19 to 10^21 impurity atoms per cubic centimeter), enabling rapid response to external electric fields and providing low-resistance electrical contacts. This design ensures efficient current transmission and, in conjunction with the low-doped layer, optimizes the electric field distribution. Doped layer 28 has a medium doping concentration (medium doping concentration is typically around 10^19 to 10^21 impurity atoms per cubic centimeter). The impurity atoms (from the 16th to the 108th power) in the epitaxial layer 21 and substrate 3 serve to smooth the electric field transition and prevent sudden changes in the electric field between the epitaxial layer 21 and substrate 3. The doped layer 3 29 has a low doping concentration (meaning from 1015th to 1017th power impurity atoms per cubic centimeter), which disperses the electric field, reduces electric field concentration, and prevents localized breakdown. Substrate 3 is typically made of high-purity silicon carbide (SiC) single crystal. Substrate 3 provides mechanical support and electrical foundation, ensuring the stability and performance of the device, and possesses good electrical and thermal properties. The main material of the anti-oxidation layer 4 is silicon dioxide. The anti-oxidation layer 4 prevents corrosion of the insulating layer 23. During the use of trench silicon carbide transistors, when it is in the conducting state...The gate 24 is connected to the external circuit via a conductive metal strip (made of copper). A positive voltage is applied to the gate 24, and an electric field is formed by the insulating layer 23 between the gate 24 and the V-groove 22. The electric field is the gradient of the potential difference in space and is independent of the conductivity of the material. The voltage applied to the gate 24 (usually a positive voltage) gives the gate a higher potential. The direction of the electric field lines determines the potential distribution. The potential of the V-groove 22 is relatively low because it is the potential distribution formed by the electric field lines pointing from the gate 24 to the V-groove 22. The insulating layer 23, made of silicon dioxide, has a high dielectric constant. A material with a high dielectric constant can increase the dispersion of the electric field and reduce the concentration of the electric field in the V-groove 22. After the electric field is formed, it will attract electrons to form a conductive channel in the V-groove 22. The source 25 is connected to the external circuit via a conductive metal strip. As an input terminal, the source 25 can improve... A large number of free electrons are supplied, and then the electrons flow through the V-groove 22 to the drain 26. The drain 26 collects the electrons, thus forming a current. The drain 26 is connected to the external circuit through a conductive metal strip, thereby delivering the current to the external circuit. The protective layer 27 adjusts the charge distribution on both sides of the V-groove 22, optimizes the electric field distribution, and reduces the concentration of the electric field at the edge of the V-groove 22. In the V-groove 22, the current path from the source 25 to the drain 26 is shorter because the inclined design of the V-groove 22 allows the current to flow more directly from the source 25 to the drain 26, reducing the detour of the current path. On-resistance refers to the resistance encountered by the current when the transistor is in the conducting state. On-resistance is proportional to the current path. The inclined design of the V-groove 22 shortens the current path, thereby reducing on-resistance and improving the conductivity of the device.

[0026] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the content of this utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A trench silicon carbide transistor, comprising a transistor body (1), characterized in that: It also includes a conductive mechanism (2); Conductive mechanism (2): It includes an epitaxial layer (21), a V-shaped trench (22), an insulating layer (23), a gate (24) and a first doped layer (271). The epitaxial layer (21) is disposed inside the tube body (1). V-shaped trenches (22) are respectively disposed on the upper side of the epitaxial layer (21). An insulating layer (23) is disposed inside the two sets of V-shaped trenches (22). A gate (24) is disposed inside the two sets of insulating layers (23). The first doped layer (271) is disposed on the upper end of the epitaxial layer (21). The first doped layer (271) is located on the front and rear sides of the tube body (1) and between the two V-shaped trenches (22) near the center of the tube body (1).

2. The trench-type silicon carbide transistor according to claim 1, characterized in that: The conductive mechanism (2) further includes a source electrode (25), which is disposed at the upper end of the tube body (1), and the upper ends of the two insulating layers (23) are in contact with the lower end of the source electrode (25).

3. The trench-type silicon carbide transistor according to claim 1, characterized in that: The conductive mechanism (2) also includes a drain electrode (26), which is disposed on the lower side inside the tube body (1).

4. The trench-type silicon carbide transistor according to claim 1, characterized in that: The conductive mechanism (2) further includes a second doped layer (28), which is disposed at the lower end of the epitaxial layer (21).

5. The trench-type silicon carbide transistor according to claim 3, characterized in that: The conductive mechanism (2) further includes a doped layer three (29), which is disposed at the upper end of the drain (26).

6. The trench-type silicon carbide transistor according to claim 5, characterized in that: A substrate (3) is disposed between the lower end of the second doped layer (28) and the upper end of the third doped layer (29).

7. The trench-type silicon carbide transistor according to claim 1, characterized in that: The interior of each of the V-shaped grooves (22) is provided with an anti-oxidation layer (4), and the inner surface of the anti-oxidation layer (4) is fixedly connected to the outer surface of the vertically adjacent insulating layer (23).

Citation Information

Patent Citations

  • Groove type silicon carbide transistor

    CN218123412U