A reverse conducting siC-mosfet field termination structure

Abstract

The utility model provides a kind of reverse-conducting SiC-MOSFET field terminal structure, belong to SIC-MOSFET device technical field, this reverse-conducting SiC-MOSFET field terminal structure, including SiC substrate, buffer layer being arranged on the upper surface of SiC substrate, drift layer being arranged on the upper surface of buffer layer, channel region being arranged in drift layer inside, source region being arranged on the surface of channel region, gate oxide layer covering the surface of channel region, gate metal layer being arranged on the upper surface of gate oxide layer, source metal layer being arranged on the surface of source region, drain metal layer being arranged on the lower surface of SiC substrate, reverse-conducting structure being arranged in drift layer inside, field terminal structure being arranged on the edge of device and passivation layer covering the surface of device, solve the technical problem of existing reverse-conducting voltage drop high, bidirectional transmission efficiency low and device integration insufficient in prior art.

Description

Technical Field

[0001] This invention belongs to the technical field of SiC-MOSFET devices, and more specifically, relates to a reverse-conducting SiC-MOSFET field termination structure. Background Technology

[0002] In modern power electronics technology, power semiconductor devices are widely used in various high-efficiency, high-reliability power conversion systems, such as uninterruptible power supplies (UPS), motor drives, renewable energy converters, and electric vehicle charging devices. Traditional power MOSFETs (metal-oxide-semiconductor field-effect transistors) typically only achieve unidirectional conduction, with their conduction path limited to forward current. Therefore, in many applications requiring bidirectional power transfer, a single MOSFET cannot meet the design requirements. To achieve bidirectional power transfer, an anti-parallel diode scheme is commonly used, where a diode is connected in parallel between the drain and source of the power MOSFET. When the current direction reverses, the diode acts as a reverse conductor, thus ensuring the system's conduction function during bidirectional power transfer. However, while this scheme achieves basic reverse conduction, it also introduces several significant problems.

[0003] First, the introduction of anti-parallel diodes significantly increases the complexity of the entire system. To ensure high reliability during bidirectional power transmission, anti-parallel diodes need to possess certain reverse recovery characteristics and low forward voltage drop, which places higher demands on system design. Simultaneously, the parallel connection of diodes and MOSFETs leads to the design of more components, wiring, and control circuits, further increasing system complexity and causing difficulties in development and maintenance. Second, due to the presence of anti-parallel diodes, the system experiences a high voltage drop during reverse conduction, directly impacting overall system efficiency. This voltage drop issue is particularly pronounced in high-power, high-frequency switching applications, leading to heat accumulation and affecting the system's thermal design and overall operating efficiency. Furthermore, the parallel structure of diodes and MOSFETs may increase switching losses, especially in high-frequency switching, where losses during reverse recovery further exacerbate the decline in system efficiency. Besides efficiency issues, the introduction of anti-parallel diodes also brings a series of packaging and thermal management challenges. The parallel use of multiple components makes device packaging more complex, leading to higher integration requirements and uneven heat distribution within the device. Thermal management issues have become particularly serious, especially in high-power applications, where traditional heat dissipation solutions are ineffective in reducing device temperature, thereby affecting system stability and reliability. Utility Model Content

[0004] In view of this, the present invention provides a reverse-conducting SiC-MOSFET field-terminal structure, which solves the technical problems of high reverse conduction voltage drop and low bidirectional transmission efficiency in the prior art.

[0005] This utility model is implemented as follows:

[0006] This invention provides a reverse-conducting SiC-MOSFET field termination structure, comprising a SiC substrate, a buffer layer disposed on the upper surface of the SiC substrate, a drift layer disposed on the upper surface of the buffer layer, a channel region disposed inside the drift layer, a source region disposed on the surface of the channel region, a gate oxide layer covering the surface of the channel region, a gate metal layer disposed on the upper surface of the gate oxide layer, a source metal layer disposed on the surface of the source region, a drain metal layer disposed on the lower surface of the SiC substrate, a reverse conduction structure disposed inside the drift layer, a field termination structure disposed at the edge of the device, and a passivation layer covering the surface of the device.

[0007] Both the source metal layer and the gate oxide layer are located on the surface of the source region, but the gate oxide layer, situated between the source metal layer and the channel region, serves as both electrical isolation and control. The source metal layer is in direct contact with the source region, while the gate oxide layer is adjacent to both the source metal layer and the channel region, ensuring that the gate can control the conductivity characteristics of the channel region. The passivation layer is generally located outside the field termination structure, directly in contact with the environment, and provides protection. The field termination structure is located below or inside the passivation layer, directly acting on the electric field termination region of the SiC-MOSFET.

[0008] The technical advantages of the reverse-conducting SiC-MOSFET field termination structure provided by this utility model are as follows: By sequentially setting each functional layer and electrode structure on the SiC substrate, a complete reverse-conducting MOSFET device is formed, realizing bidirectional conductivity, improving the power density and switching performance of the device, and meeting the bidirectional power transmission requirements in power electronics applications.

[0009] Based on the above technical solution, the reverse-conducting SiC-MOSFET field termination structure of this utility model can be further improved as follows:

[0010] The reverse conduction structure includes P-type doped regions and N-type doped regions disposed inside the drift layer. The P-type doped regions and N-type doped regions are arranged alternately to form a PN junction array, and the doping concentration of the P-type doped regions is 10. 16 ~10 18 / cm 3 .

[0011] The beneficial effects of adopting the above-mentioned improved scheme are as follows: the PN junction array in the reverse conduction structure provides a conductive channel when reverse biased, reducing the reverse conduction voltage drop. At the same time, by optimizing the doping concentration of the P-type doped region, the reverse conduction performance and forward blocking capability are balanced, thereby improving the bidirectional transmission efficiency of the device.

[0012] Furthermore, the channel region is located on the upper surface of the drift layer and is adjacent to the source region. The doping type of the channel region is opposite to that of the drift layer. The width of the channel region is 1 to 5 μm and the depth is 0.5 to 2 μm.

[0013] Specifically, the source region is located at one end of the channel region, close to the channel surface, and is used to receive current and guide its flow through the channel region. The interface between the source and channel regions is in close contact, and the doping type of the source region differs from that of the channel region to form a current path between them. The source region is typically opposite the drain region, forming a current channel, while the channel region controls current flow through the gate.

[0014] The beneficial effects of adopting the above-mentioned improvement scheme are: the design of the channel size and doping type ensures the formation of an effective conductive channel under gate voltage control; by optimizing the geometric parameters of the channel region, the on-resistance is reduced, and the switching speed and current carrying capacity of the device are improved.

[0015] Furthermore, the thickness of the gate oxide layer is 20-100 nm, and the gate metal layer is made of polycrystalline silicon or metal material, with a thickness of 200-500 nm.

[0016] The gate oxide layer is located on the surface of the channel region, covering it. The function of the gate oxide layer is to provide an insulating layer to ensure electrical isolation between the gate and the channel region. The presence of the gate oxide layer allows the gate metal layer to modulate the conductivity of the channel region through an electric field without directly contacting it, thereby controlling the flow of current.

[0017] Although the gate oxide layer is located on the surface of the channel region, it does not directly cover the source region. The source region is located at one end of the channel region, and the gate oxide layer generally does not directly affect the source region. Instead, it is concentrated above the channel region, and the conduction and turn-off of the channel region are controlled by the gate metal layer. Therefore, the position of the gate oxide layer can be summarized as covering the surface of the channel region, serving both electrical isolation and control functions.

[0018] The beneficial effects of adopting the above-mentioned improvement scheme are: the thickness of the gate oxide layer controls the electric field distribution and coupling strength between the gate and the channel, and the material selection and thickness design of the gate metal layer ensure good gate control performance, thereby improving the switching characteristics and reliability of the device.

[0019] Furthermore, the field termination structure includes a guard ring and a field plate structure disposed at the edge of the device. The guard ring is composed of multiple concentric ring-shaped P-type doped regions, and the spacing between adjacent guard rings is 5 to 20 μm.

[0020] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the field terminal structure improves the electric field distribution at the edge of the device through the synergistic effect of the protection ring and the field plate, prevents edge breakdown, improves the withstand voltage and long-term reliability of the device, and ensures the stability of the device under high voltage operating conditions.

[0021] Furthermore, the thickness of the buffer layer is 0.5–2 μm, the doping concentration of the buffer layer is higher than that of the drift layer, and a homogeneous epitaxial growth interface is formed between the buffer layer and the SiC substrate.

[0022] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the buffer layer plays a transition role between the SiC substrate and the drift layer, reducing lattice mismatch and defect density, and improving carrier injection efficiency and device conduction performance through high doping concentration design.

[0023] Furthermore, the passivation layer is made of a material, and the thickness of the passivation layer is 500-2000 nm. Contact holes are formed on the surface of the passivation layer to expose the source metal layer and the gate metal layer.

[0024] The beneficial effects of adopting the above-mentioned improvement scheme are: the passivation layer protects the device surface from environmental influences, prevents the formation of surface states, and enables reliable connection with external circuits through the opening of contact holes, thereby improving the packaging reliability and environmental stability of the device.

[0025] Furthermore, the thickness of the drift layer is 10–50 μm, and the doping concentration of the drift layer is 10. 14 ~10 16 / cm 3 The drift layer is made of N-type doped SiC material.

[0026] The beneficial effects of adopting the above-mentioned improvement scheme are: the thickness and doping concentration of the drift layer are designed to balance the voltage withstand capability and on-resistance of the device, and excellent electrical performance is achieved through N-type doped SiC material to meet the requirements of high voltage and high power applications.

[0027] Furthermore, the source metal layer and the drain metal layer are respectively made of aluminum alloy or nickel silicide, the source metal layer forms an ohmic contact with the source region, and the drain metal layer forms an ohmic contact with the SiC substrate.

[0028] The beneficial effects of adopting the above-mentioned improvement scheme are: the material selection of the source metal layer and the drain metal layer ensures good ohmic contact with the semiconductor material, reduces contact resistance, and improves the current transmission efficiency and thermal stability of the device.

[0029] Furthermore, the width ratio of the P-type doped region to the N-type doped region in the reverse conduction structure is 1:1 to 1:3, and the periodic arrangement spacing of the PN junction array is 2 to 10 μm.

[0030] The beneficial effects of adopting the above-mentioned improved scheme are: the width ratio and periodic arrangement of the P-type and N-type doped regions in the reverse conduction structure optimize the reverse conduction characteristics, and the best balance between the reverse conduction resistance and the forward blocking voltage is achieved by precisely controlling the geometric parameters.

[0031] Compared with the prior art, the beneficial effects of the reverse-conducting SiC-MOSFET field termination structure provided by this utility model are:

[0032] This invention achieves a harmonious balance between low reverse conduction voltage drop and high forward blocking capability by incorporating a reverse conduction structure with a PN junction array within the drift layer, combined with an optimized gate structure and field termination design. This structure not only effectively reduces the voltage drop during reverse conduction, significantly improving system energy efficiency, but also solves the power loss problem caused by excessively high reverse conduction voltage drop in traditional solutions. Through this optimized design, the device exhibits high efficiency in bidirectional power transmission, particularly in high-frequency switching and high-power-density applications, significantly reducing system losses due to poor reverse conduction performance and improving overall system efficiency.

[0033] Furthermore, this invention utilizes SiC (silicon carbide) material, whose excellent thermal conductivity, high temperature resistance, and high power density characteristics enable the device to operate stably even at high temperatures, meeting the stringent requirements of modern power electronics applications for high-temperature operation and high power density. The application of SiC material not only improves the device's operational reliability but also optimizes thermal management performance, further enhancing the overall performance and integration of the device. Through this innovative design, this invention successfully overcomes the problems of poor reverse conduction performance, low device integration, and operating temperature limitations in existing technologies, providing a completely new solution for high-efficiency, highly integrated, and high-temperature-operating power electronic devices. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is an example diagram of a reverse-conducting SiC-MOSFET field-terminal structure;

[0036] The attached diagram lists the components represented by each number as follows:

[0037] 1. SiC substrate; 2. Buffer layer; 3. Drift layer; 4. Channel region; 5. Source region; 6. Gate oxide layer; 7. Gate metal layer; 8. Source metal layer; 9. Drain metal layer; 10. Reverse conduction structure; 11. Field termination structure; 12. Passivation layer. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.

[0039] like Figure 1 The diagram shows a first embodiment of a reverse-conducting SiC-MOSFET field termination structure provided by this utility model. In this embodiment, it includes a SiC substrate 1, a buffer layer 2 disposed on the upper surface of the SiC substrate 1, a drift layer 3 disposed on the upper surface of the buffer layer 2, a channel region 4 disposed inside the drift layer 3, a source region 5 disposed on the surface of the channel region 4, a gate oxide layer 6 covering the surface of the channel region 4, a gate metal layer 7 disposed on the upper surface of the gate oxide layer 6, a source metal layer 8 disposed on the surface of the source region 5, a drain metal layer 9 disposed on the lower surface of the SiC substrate 1, a reverse conduction structure 10 disposed inside the drift layer 3, a field termination structure 11 disposed at the edge of the device, and a passivation layer 12 covering the surface of the device.

[0040] The manufacturing process of this solution includes substrate preparation, epitaxial growth, ion implantation, thermal activation, oxidation, metallization, etching, and passivation. First, the SiC substrate 1 is cleaned and pretreated. Then, a buffer layer 2 and a drift layer 3 are grown sequentially using chemical vapor deposition. Next, various doped regions are formed through photolithography and ion implantation, including the channel region 4, the source region 5, and the doped regions in the reverse conduction structure 10. After implantation, high-temperature activation annealing is performed to activate the doped atoms and repair implantation damage. Subsequently, thermal oxidation growth of the gate oxide layer 6 is performed, and the gate metal layer 7 is deposited. The gate pattern is defined through photolithography and etching processes to form the ohmic contact between the source metal layer 8 and the drain metal layer 9. Finally, a passivation layer is deposited and contact holes are formed to complete the fabrication of the metal interconnect layer. The entire manufacturing process needs to be carried out in a cleanroom environment, and process parameters are strictly controlled to ensure device performance.

[0041] The improved manufacturing process adds a precision photolithography process to the striped PN junction array, requiring the use of electron beam lithography or deep ultraviolet lithography to accurately define the micro-patterns. The fabrication of the dual-channel structure requires multiple ion implantation and selective masking processes to ensure the uniformity and consistency of the two channels. The fabrication of the double-layer passivation requires precise control of the interface quality of the two layers of materials to avoid stress concentration and the generation of interface states. The entire process requires higher control precision, but can achieve superior device performance.

[0042] In the above technical solution, the reverse conduction structure includes P-type doped regions and N-type doped regions disposed inside the drift layer. The P-type doped regions and N-type doped regions are arranged alternately to form a PN junction array, and the doping concentration of the P-type doped regions is 10. 16 ~10 18 / cm 3 .

[0043] Furthermore, in the above technical solution, the channel region is located on the upper surface of the drift layer and is adjacent to the source region. The doping type of the channel region is opposite to that of the drift layer. The width of the channel region is 1 to 5 μm and the depth is 0.5 to 2 μm.

[0044] Furthermore, in the above technical solution, the thickness of the gate oxide layer is 20-100 nm, and the gate metal layer is made of polycrystalline silicon or metal material, with a thickness of 200-500 nm.

[0045] Furthermore, in the above technical solution, the field termination structure includes a guard ring and a field plate structure disposed at the edge of the device. The guard ring is composed of multiple concentric ring-shaped P-type doped regions, and the spacing between adjacent guard rings is 5 to 20 μm.

[0046] Furthermore, in the above technical solution, the thickness of the buffer layer is 0.5 to 2 μm, the doping concentration of the buffer layer is higher than that of the drift layer, and a homogeneous epitaxial growth interface is formed between the buffer layer and the SiC substrate.

[0047] Furthermore, in the above technical solution, the passivation layer is made of a certain material, the thickness of the passivation layer is 500-2000nm, and contact holes are formed on the surface of the passivation layer to expose the source metal layer and the gate metal layer.

[0048] Furthermore, in the above technical solution, the thickness of the drift layer is 10–50 μm, and the doping concentration of the drift layer is 10. 14 ~10 16 / cm 3 The drift layer is made of N-type doped SiC material.

[0049] Furthermore, in the above technical solution, the source metal layer and the drain metal layer are made of aluminum alloy or nickel silicide, respectively. The source metal layer forms an ohmic contact with the source region, and the drain metal layer forms an ohmic contact with the SiC substrate.

[0050] Furthermore, in the above technical solution, the width ratio of the P-type doped region to the N-type doped region in the reverse conduction structure is 1:1 to 1:3, and the periodic arrangement spacing of the PN junction array is 2 to 10 μm.

[0051] This invention provides a second embodiment of a reverse-conducting SiC-MOSFET field-termining structure. In this embodiment, the device structure is fabricated using a standard MOSFET process. The SiC substrate 1 is a 4H-SiC N-type single crystal wafer with a resistivity of 0.02 Ω·cm, a thickness of 350 μm, and a surface roughness of less than 0.5 nm. The buffer layer 2 is prepared by high-temperature epitaxial growth at 1550℃ at a growth rate of 5 μm / h. Nitrogen gas is used as the doping source, and the doping concentration is precisely controlled at 5 × 10⁻⁶. 17 / cm 3 The drift layer 3, with a thickness of 1 μm, was epitaxially grown at 1600℃ with a doping concentration of 8 × 10⁻⁶. 15 / cm 3 The epitaxial layer is 25 μm thick, and the carbon-to-silicon ratio is strictly controlled at 1.0 during growth to ensure the quality of the epitaxial layer. Channel region 4 is formed by boron ion implantation at an energy of 80 keV and a dose of 3 × 10⁻⁶. 13 / cm 2 After implantation, it was activated for 30 minutes in an argon atmosphere at 1700℃ to form a doping depth of 1.2 μm and a doping concentration of 8 × 10⁻⁶. 16 / cm 3 In the P-type channel region, source region 5 is implanted with phosphorus ions at an implantation energy of 40 keV and a dose of 10. 15 / cm 2 After activation, a doping depth of 0.25 μm and a doping concentration of 5 × 10⁻⁶ are formed. 18 / cm 3 The N-type heavily doped region is formed by dry oxidation of the gate oxide layer 6 at 1150℃ for 4 hours, resulting in a high-quality SiO₂ layer with a thickness of 45nm. The gate metal layer 7 is formed by low-pressure chemical vapor deposition of phosphorus-doped polycrystalline silicon at a deposition temperature of 620℃ and a doping concentration of 10. 20 / cm 3 The reverse-conducting structure 10, with a thickness of 400 nm, was prepared by multiple selective ion implantations. Boron was implanted into the P-type region, and phosphorus was implanted into the N-type region. The implantation depth was 15 μm, and the doping concentration in the P-type region was 3 × 10⁻⁶. 16 / cm 3 The doping concentration in the N-type region is 8 × 10⁻⁶.16 / cm 3 The PN junction array has a period of 5 μm. The source metal layer 8 is prepared by sputtering an aluminum-silicon alloy with a silicon content of 1% and a thickness of 1.2 μm. It is rapidly thermally annealed at 400 °C to form an ohmic contact. The drain metal layer 9 is prepared by nickel sputtering followed by silicide treatment. The nickel thickness is 100 nm, and it is annealed at 950 °C to form nickel silicide. The field termination structure includes four guard rings with a ring width of 5 μm and a ring spacing of 12 μm. They are formed by boron ion implantation with a doping concentration of 5 × 10⁻⁶. 15 / cm 3 The passivation layer is Si3N4 deposited by plasma-enhanced chemical vapor deposition at 300℃, with a thickness of 1.2 μm. The device fabricated in this embodiment has a forward blocking voltage of 1200 V and an on-resistance of 2.5 mΩ·cm at room temperature. 2 The reverse conduction voltage drop is 0.8V at rated current, which is 65% lower than that of the traditional anti-parallel diode solution. The device can still work stably at a high temperature of 175℃, the switching frequency can reach 100kHz, and the power density is increased by more than 40%. This embodiment fully verifies the technical advantages and practical value of this utility model.

[0052] This invention provides a third embodiment of a reverse-conducting SiC-MOSFET field termination structure. In this embodiment, more refined process technology and optimized structural parameters are used. The SiC substrate 1 is selected from 4H-SiC wafers with ultra-low defect density and a dislocation density of less than 102. 3 / cm 2 The buffer layer 2 and drift layer 3 are 300 μm thick. The epitaxial growth of these layers was carried out using a coaxial rotating epitaxial reactor to ensure thickness uniformity better than ±2%. The doping concentration of drift layer 3 was precisely controlled at 6 × 10⁻⁶. 15 / cm 3 The thickness is 28 μm. The dual-channel structure was fabricated using deep ion implantation technology. Each channel is 1.5 μm deep and 1.8 μm wide, with a channel spacing of 0.8 μm. Precise mask alignment ensures the parallelism of the two channels. The reverse conduction structure 10 adopts a striped layout with a stripe width of 2.5 μm and a spacing of 1.5 μm. The pattern is defined using electron beam lithography, achieving a linewidth accuracy of ±50 nm. The P-type stripes are implanted with boron ions at an implantation angle of 7°, an energy of 120 keV, and a dose of 5 × 10⁻⁶. 13 / cm 2 The N-type stripes were implanted using phosphorus ion implantation at an implantation angle of 0°, an energy of 150 keV, and a dose of 8 × 10⁻⁶. 13 / cm 2After implantation, activation was performed at 1750℃ for 45 minutes to form a striped PN junction array with a depth of 18μm. The gate oxide layer 6 thickness was optimized to 38nm and prepared using atomic layer deposition technology to ensure thickness uniformity and interface quality. The gate metal layer 7 adopts a TiN / polysilicon bilayer structure, with a TiN layer thickness of 20nm as a barrier layer and a polysilicon layer thickness of 300nm. In the bilayer passivation structure, the SiO2 layer is prepared by plasma-enhanced chemical vapor deposition with a thickness of 250nm, and the Si3N4 layer has a thickness of 750nm. Interface treatment is performed between the two layers to reduce stress. Field-terminated junctions are then established. The structure includes six guard rings with a variable spacing design, with spacings of 6μm, 8μm, 10μm, 12μm, and 14μm from the inside out. The source metal layer 8 adopts a Ti / Al / Ti three-layer metallization structure with a total thickness of 1.5μm. The Ti layer serves as an adhesion and barrier layer, while the Al layer serves as the main conductive layer. The drain metal layer 9 adopts a Ti / Ni / Au multilayer structure with a total thickness of 0.8μm. Stable ohmic contacts are formed through a multi-step annealing process. The device performance fabricated in this embodiment is further improved, with a forward blocking voltage of 1350V and an on-resistance reduced to 2.0mΩ·cm. 2 The reverse conduction voltage drop is only 0.6V at rated current, the current density of the device is increased by 25%, the switching loss is reduced by 30%, and it can still work normally at a high temperature of 200℃. Long-term reliability tests show that the device has no performance degradation under high temperature and high pressure stress. This embodiment demonstrates the great potential of this invention in high-performance applications and provides an ideal device solution for the next generation of power electronic systems.

[0053] Specifically, the principle of this invention is as follows: The reverse-conducting SiC-MOSFET device constructs a reverse-conducting structure with a PN junction array inside the drift layer. When the device is subjected to a reverse voltage, the PN junctions in the array conduct in the forward direction, providing a low-resistance reverse conductive path and significantly reducing the reverse conduction voltage drop. When the device is subjected to a forward voltage, the channel region forms a conductive channel under the control of the gate voltage, realizing the forward conduction function. The field termination structure effectively improves the electric field distribution at the device edge and prevents edge breakdown through the voltage division effect of the guard ring and the electric field redistribution effect of the field plate. The wide bandgap characteristics of SiC material enable the device to have high withstand voltage, low on-resistance, and high-temperature operating capability. The introduction of the buffer layer reduces interface defects and improves the carrier mobility of the device. The optimized thickness of the gate oxide layer ensures good gate control performance, and the protective effect of the passivation layer improves the long-term reliability of the device. The entire device structure achieves efficient bidirectional power transmission and excellent switching performance through the synergistic effect of each functional layer.

Claims

1. A reverse-conducting SiC-MOSFET field-termination structure, characterized in that, It includes a SiC substrate, a buffer layer disposed on the upper surface of the SiC substrate, a drift layer disposed on the upper surface of the buffer layer, a channel region disposed inside the drift layer, a source region disposed on the surface of the channel region, a gate oxide layer covering the surface of the channel region, a gate metal layer disposed on the upper surface of the gate oxide layer, a source metal layer disposed on the surface of the source region, a drain metal layer disposed on the lower surface of the SiC substrate, a reverse conduction structure disposed inside the drift layer, a field termination structure disposed at the edge of the device, and a passivation layer covering the surface of the device.

2. The reverse-conducting SiC-MOSFET field-termination structure according to claim 1, characterized in that, The reverse conduction structure includes P-type doped regions and N-type doped regions disposed inside the drift layer, with the P-type doped regions and N-type doped regions arranged alternately to form a PN junction array.

3. The reverse-conducting SiC-MOSFET field-termination structure according to claim 2, characterized in that, The channel region is located on the upper surface of the drift layer and is adjacent to the source region. The doping type of the channel region is opposite to that of the drift layer. The width of the channel region is 1 to 5 μm and the depth is 0.5 to 2 μm.

4. The reverse-conducting SiC-MOSFET field-termination structure according to claim 3, characterized in that, The thickness of the gate oxide layer is 20-100 nm, and the gate metal layer is made of polycrystalline silicon or metal material with a thickness of 200-500 nm.

5. The reverse-conducting SiC-MOSFET field-termination structure according to claim 4, characterized in that, The field termination structure includes a guard ring and a field plate structure disposed at the edge of the device. The guard ring is composed of multiple concentric ring-shaped P-type doped regions, and the spacing between adjacent guard rings is 5 to 20 μm.

6. The reverse-conducting SiC-MOSFET field-termination structure according to claim 5, characterized in that, The thickness of the buffer layer is 0.5 to 2 μm, the doping concentration of the buffer layer is higher than that of the drift layer, and a homogeneous epitaxial growth interface is formed between the buffer layer and the SiC substrate.

7. The reverse-conducting SiC-MOSFET field-termination structure according to claim 6, characterized in that, The passivation layer has a thickness of 500–2000 nm, and contact holes are formed on the surface of the passivation layer to expose the source metal layer and the gate metal layer.

8. The reverse-conducting SiC-MOSFET field-termination structure according to claim 7, characterized in that, The drift layer has a thickness of 10–50 μm and is made of N-type doped SiC material.

9. The reverse-conducting SiC-MOSFET field-termination structure according to claim 8, characterized in that, The source metal layer and drain metal layer are made of aluminum alloy or nickel silicide, respectively. The source metal layer forms an ohmic contact with the source region, and the drain metal layer forms an ohmic contact with the SiC substrate.

10. The reverse-conducting SiC-MOSFET field-termination structure according to claim 9, characterized in that, The width ratio of the P-type doped region to the N-type doped region in the reverse conduction structure is 1:1 to 1:3, and the periodic arrangement spacing of the PN junction array is 2 to 10 μm.

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