Semiconductor device

Abstract

A semiconductor device is provided that includes a plurality of semiconductor channel layers formed over a substrate. The semiconductor device further includes an internal spacer disposed between adjacent ones of the plurality of semiconductor channel layers and on both sides of a channel region. The semiconductor device further includes a metal gate structure disposed between the adjacent semiconductor channel layers, wherein the internal spacer is disposed on both sides of the metal gate structure, and wherein a liner layer is disposed between a portion of the metal gate structure and each of the adjacent semiconductor channel layers. A metal gate profile of the metal gate structure has a convex or concave shape.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and in particular to a gate structure for a semiconductor device. Background Technology

[0002] The electronics industry has experienced an increasing demand for smaller and faster electronic devices that can support a growing number of increasingly complex and sophisticated functions. Consequently, the semiconductor industry continues to move towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). These ambitious goals have been largely achieved by reducing the size of semiconductor ICs (e.g., the minimum component size), thereby improving production efficiency and reducing associated costs. However, such reductions have also increased the complexity of semiconductor manufacturing processes. Therefore, continued development in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCE). The fin field-effect transistor (FinFET) is one such multi-gate device. Its name comes from the fin-like structure that extends from the substrate it forms to create the transistor channel. The gate-all-around (GAA) transistor is another type of multi-gate device, introduced partly to address the performance challenges associated with finFETs. Its name comes from the fully extended gate structure surrounding the channel region, providing better electrostatic control than finFETs. Both finFETs and GAAs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their three-dimensional structure allows for aggressive miniaturization of device size while maintaining gate control and mitigating short-channel effects.

[0004] Generally, gate-all-around transistors (GALL-E) are used when fin field-effect transistors (FETs) can no longer meet the performance requirements of a device. However, the fabrication of GALL-E transistors also presents new challenges to semiconductor manufacturing processes and leads to reliability issues in related devices. Therefore, existing technologies have not yet proven to be completely satisfactory in all aspects. Utility Model Content

[0005] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0006] One embodiment of this utility model describes a method of manufacturing a semiconductor device, comprising providing a fin comprising an epitaxial layer stack having a plurality of semiconductor channel layers inserted by a plurality of dummy layers. In some embodiments, the method further comprises removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. In some examples, the method further comprises depositing a liner over the surface of the adjacent semiconductor channel layer exposed by the first gap. In some embodiments, the method further comprises performing a plasma processing process on the liner to provide a plasma-treated liner. In some cases, the method further comprises removing a first portion of the plasma-treated liner to form a second gap between the adjacent semiconductor channel layers, and a second portion of the adjacent semiconductor channel layer remaining disposed on the surface of the adjacent semiconductor channel layer.

[0007] In another embodiment, a method of manufacturing a semiconductor device is discussed, comprising providing a fin having an epitaxial layer defining a semiconductor channel layer, and using a liner to surround an exposed surface of the epitaxial layer. In some examples, the method further comprises performing a plasma processing process on the liner to define a first region of the liner disposed over a first portion of the epitaxial layer, and a second region of the liner disposed over a second portion of the epitaxial layer. In some embodiments, the method further comprises removing the first region of the liner to form a gap between the epitaxial layer and an adjacent epitaxial layer defining an adjacent semiconductor channel layer, and the second region of the liner remains disposed over the second portion of the epitaxial layer. In some cases, the method further comprises forming a portion of a metal gate structure within the gap, wherein the metal gate profile of the portion of the metal gate structure has a convex or concave shape.

[0008] In another embodiment, a semiconductor device is discussed, comprising a plurality of semiconductor channel layers formed over a substrate. In some embodiments, the semiconductor device further includes internal spacers disposed between adjacent semiconductor channel layers and on both sides of channel regions. In some examples, the semiconductor device further includes a metal gate structure disposed between the adjacent semiconductor channel layers, wherein the internal spacers are disposed on both sides of the metal gate structure, and wherein a liner is disposed between a portion of the metal gate structure and each of the adjacent semiconductor channel layers. In some embodiments, the metal gate profile of the metal gate structure has a convex or concave shape.

[0009] In some embodiments, when the metal gate profile has the convex shape, the metal gate structure has a first thickness near a central portion of the metal gate structure disposed between the central regions of the adjacent semiconductor channel layers, the first thickness being greater than a second thickness of the metal gate structure near the side ends of the metal gate structure disposed between the side ends of the adjacent semiconductor channel layers.

[0010] In some embodiments, when the metal gate profile has the concave shape, the metal gate structure has a first thickness near a central portion of the metal gate structure disposed between the central regions of the adjacent semiconductor channel layers, the first thickness being less than a second thickness of the metal gate structure near the side ends of the metal gate structure disposed between the side ends of the adjacent semiconductor channel layers.

[0011] In some embodiments, the metal gate structure includes a gate dielectric layer comprising: an interface layer; and a high dielectric constant dielectric layer formed on the interface layer.

[0012] In some embodiments, the gate dielectric layer has a total thickness of 1 to 5 nanometers.

[0013] In some embodiments, the gate dielectric layer is disposed above the surfaces of the adjacent semiconductor channel layer and the substrate.

[0014] In some embodiments, the interface layer is disposed on the entire surface of the adjacent semiconductor channel layers between the internal spacers.

[0015] In some embodiments, the high dielectric constant dielectric layer is disposed on the substrate and on the interface layer disposed in the region of the adjacent semiconductor channel layer not covered by the substrate.

[0016] In some embodiments, the interface layer is disposed over the portion of the adjacent semiconductor channel layer not covered by the liner.

[0017] In some embodiments, the metal gate structure further includes a metal layer disposed on the gate dielectric layer. Attached Figure Description

[0018] The following detailed description, in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of this utility model. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly illustrate the parts of the embodiments of this utility model.

[0019] Figure 1 This is a simplified top view schematic diagram of a multi-gate device according to some embodiments.

[0020] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device 300 according to one or more aspects of the present invention.

[0021] Figure 3 , Figure 4 , Figure 5 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a schematic cross-sectional view of an embodiment of a semiconductor device 300 along a plane, and this plane is substantially parallel to the plane provided by... Figure 1 The plane defined by section A-A'.

[0022] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 11A , Figure 12A , Figure 13A and Figure 14A This is an enlarged schematic diagram of a portion of a semiconductor device 300 according to some embodiments of the present invention.

[0023] Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 11B , Figure 12B , Figure 13B and Figure 14B This is an enlarged schematic diagram of a portion of a semiconductor device 300 according to other embodiments of the present invention.

[0024] The reference numerals in the attached figures are explained as follows:

[0025] 100: Multi-gate device

[0026] 104: Fin element

[0027] 105, 107: Source / Drain Regions

[0028] 108: Gate structure

[0029] 200: Method

[0030] Blocks 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222:

[0031] 300: Semiconductor Devices

[0032] 304: Base

[0033] 304A: Base

[0034] 306: Fins

[0035] 308, 310: Epitaxial layer

[0036] 316: Gate Stack

[0037] 320: Dielectric layer

[0038] 322: Electrode layer

[0039] 325: Spacer layer

[0040] 330: Trench

[0041] 402: Gap (or cavity)

[0042] 502: Lining

[0043] 502A: Oxide layer / Oxide liner

[0044] 502B: Carbon-containing layer / carbon-containing liner

[0045] 504: Partial

[0046] 602: Nitrogen-based plasma process

[0047] 604: Oxygen plasma process

[0048] 606: Nitrogen-rich area

[0049] 608: Low nitrogen concentration area / Nitrogen-free area

[0050] 610: Carbon-deficient areas

[0051] 612: High carbon concentration area

[0052] 702: Intermediary Layer

[0053] 802: Groove

[0054] 902: Internal spacers

[0055] 1002: Source / Drain Components

[0056] 1004: Contact Etching Stop Layer (CESL)

[0057] 1006: Interlayer Dielectric (ILD) Layer

[0058] 1102: Trench

[0059] 1104, 1106: Gap

[0060] 1202: Gate structure

[0061] 1204: Dielectric layer

[0062] 1204A: Interface Layer (IL)

[0063] 1204B: High dielectric constant dielectric layer

[0064] 1206: Metal layer

[0065] A-A': Cross-section

[0066] D: Depth of erosion

[0067] T1, T2, T3, T4: Thickness Detailed Implementation

[0068] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, if the description mentions that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of the embodiments of this utility model. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0069] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0070] Additionally, in the following description, dimensions (e.g., thickness, width, length, etc.) for a given film or other component may sometimes be described using terms such as “substantially equal,” “equal,” or “approximately,” where such terms are understood to be within + / - 10% of the described value or between the comparative values. For example, if dimension A is described as “substantially equal” to dimension B, it will be understood that dimension A is within + / - 10% of dimension B. In another example, if a film is described as having a thickness of approximately 100 nanometers, it will be understood that the thickness of this film will be between 90 and 110 nanometers.

[0071] It should also be noted that this invention is presented in the form of a multi-gate transistor. A multi-gate transistor includes those transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices may include P-type transistors or N-type transistors. Specific examples may be proposed herein and referred to as FinFETs because they have a fin-like structure. An embodiment of a multi-gate transistor, referred to as a fully-wound gate (GAA) transistor, is also described herein. A fully-wound gate (GAA) transistor includes any device having its gate structure or portions thereof formed on four sides of a channel region (e.g., surrounding a portion of the channel region). The devices described herein also include embodiments having channel regions disposed within a semiconductor channel layer. In various different embodiments, the semiconductor channel layer may include nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Embodiments of the devices described herein may have one or more channel regions (e.g., a semiconductor channel layer) coupled with a single, continuous gate structure. However, those skilled in the art will understand that embodiments of the present invention can be applied to a single channel (e.g., a single semiconductor channel layer) or any number of channels. Other examples of semiconductor devices that benefit from various embodiments of the present invention will be understood by those skilled in the art.

[0072] For multi-gate devices, such as gate-wound (GAA) devices, the metal gate profile (e.g., between adjacent semiconductor channel layers) is critical to both device performance and yield. In at least some existing implementations, the selection for modulating the metal gate profile remains limited, particularly for highly scaled devices. This can degrade device performance and lead to reliability concerns. Recently, as part of the GAA device process, a disposable interposer process has been introduced to improve device drive current, reduce capacitance, and mitigate short-channel effects. However, effective control of the metal gate profile achieved as part of the disposable interposer process remains a challenge. Therefore, the prior art has not yet proven to be completely satisfactory in all aspects.

[0073] The embodiments of this invention provide advantages over the prior art; however, it is understood that other embodiments may offer different advantages, and it is not necessary to discuss all advantages in this invention, nor are all embodiments necessarily advantageous. For example, the embodiments discussed in this invention include methods and structures for modulating the metal gate profile of a multi-gate device (e.g., a fully wrapped gate (GAA) device) to address various prior art challenges. In various embodiments, the metal gate profile in the final device structure (e.g., between adjacent semiconductor channel layers) may be convex or concave. For example, a convex metal gate profile may have a greater thickness near the center of the metal gate disposed between the central regions of adjacent semiconductor channel layers and a smaller thickness near the side ends of the metal gate disposed between the side ends of adjacent semiconductor channel layers. In another example, a concave metal gate profile may have a greater thickness near the side ends of the metal gate disposed between the side ends of adjacent semiconductor channel layers and a smaller thickness near the center of the metal gate disposed between the central regions of adjacent semiconductor channel layers.

[0074] In some examples, the method of modulating the metal gate profile includes initially removing a dummy layer (e.g., a silicon-germanium (SiGe) layer) inserted into an adjacent semiconductor channel layer, and then depositing a substrate and a discarded interposer (also referred to as an "interposer") to fill the cavity formed by removing the dummy layer. In some cases, the substrate may comprise an atomic layer deposition (ALD) layer, such as an oxide layer, a silicon oxycarbide (SiOC) layer, or other suitable layers, and the specific composition of the substrate may be selected depending on whether the metal gate profile required in the final device structure is convex or concave. After depositing the substrate and before depositing the interposer, a plasma process may be performed to process the substrate. For example, if the substrate comprises an oxide layer, a nitrogen-based plasma process (e.g., using ammonia (NH3) or nitrogen (N2)) may be performed to form a nitrogen-rich region within the oxide substrate on a portion of the oxide substrate disposed above the side region of the adjacent semiconductor channel layer. The formation of nitrogen-rich regions can simultaneously provide or define low-nitrogen-concentration regions (or nitrogen-free regions) on the oxide liner disposed above the central region of adjacent semiconductor channel layers. Furthermore, the nitrogen concentration difference between the nitrogen-rich regions and the low-nitrogen-concentration regions (or nitrogen-free regions) is sufficient to provide etch selectivity between the two regions, i.e., between the nitrogen-rich regions and the low-nitrogen-concentration regions (or nitrogen-free regions).

[0075] In another example, if the substrate comprises a silicon carbide layer, an oxygen-based plasma process (e.g., using oxygen (O2)) can be performed to form carbon-deficient regions within the silicon carbide substrate on a portion of the silicon carbide substrate disposed above the side regions of adjacent semiconductor channel layers. The formation of these carbon-deficient regions can simultaneously define high-carbon-concentration regions of the silicon carbide substrate disposed above the central regions of adjacent semiconductor channel layers (e.g., regions of the silicon carbide substrate substantially unaffected by the oxygen-based plasma process). Furthermore, the carbon concentration difference between the carbon-deficient and high-carbon-concentration regions is sufficient to provide etch selectivity between the two regions, i.e., between the carbon-deficient and high-carbon-concentration regions.

[0076] After plasma treatment of the substrate, an interposer can be deposited to fill the remaining space in the cavity formed by removing the dummy layer. Subsequently, an etching process is performed to etch the deposited substrate and interposer, thereby forming internal spacer trenches between the side ends of adjacent semiconductor channel layers. Internal spacer material is deposited within the internal spacer trenches and etched back to complete the formation of the internal spacers. After forming the internal spacers, epitaxial source / drain components are formed. Thereafter, the remaining portion of the interposer and selected portions of the substrate (described below) are removed to form gaps between adjacent semiconductor channel layers, and subsequently, a metal gate structure is formed therein.

[0077] In some embodiments, if the substrate comprises an oxide layer, the removal of a portion of the interposer (e.g., by a wet etching process) is also used to remove low-nitrogen concentration regions (or nitrogen-free regions) of the oxide substrate, while nitrogen-rich regions of the oxide substrate are retained above the side regions of the adjacent semiconductor channel layers. The retained nitrogen-rich regions of the oxide substrate, together with the adjacent semiconductor channel layers, are used to define a concave gap between the adjacent semiconductor channel layers. Therefore, a metal gate structure can subsequently be formed within the gap, wherein the metal gate profile of the metal gate structure has a convex shape complementary to the concavity of the gap.

[0078] In some embodiments, if the substrate comprises a silicon carbide layer, the removal of a portion of the interposer (e.g., by a wet etching process) is also used to remove carbon-deficient regions of the silicon carbide substrate, while high-carbon-concentration regions of the silicon carbide substrate (e.g., regions of the silicon carbide substrate substantially unaffected by oxygen plasma processes) are retained over the central region of the adjacent semiconductor channel layer. The retained high-carbon-concentration regions of the silicon carbide substrate, together with the adjacent semiconductor channel layer, are used to define a convex gap between the adjacent semiconductor channel layers. Therefore, a metal gate structure can subsequently be formed within the gap, wherein the metal gate profile of the metal gate structure has a concave shape complementary to the convexity of the gap. Thus, embodiments of the present invention provide effective control over the metal gate profile achieved as part of a discardable interposer process, which can be adjusted according to device design and / or performance requirements. Other embodiments and advantages will be apparent to those skilled in the art upon reading this disclosure.

[0079] For the purposes of the following explanation, Figure 1 A simplified top view schematic diagram of a multi-gate device 100 is provided. In various embodiments, the multi-gate device 100 may include a FinFET device, a gate-wound array (GAA) transistor, or other types of multi-gate devices. The multi-gate device 100 may include: a plurality of fin elements 104 extending from a substrate, a gate structure 108 disposed on and around the fin elements 104, and source / drain regions 105 and 107, wherein the source / drain regions 105 and 107 are formed in, on, and / or around the fin elements 104. Along substantially parallel to the... Figure 1 The plane defined by cross section A-A' contains a channel region of the multi-gate device 100 disposed within the fin element 104 and below the gate structure 108, wherein the channel region may include multiple semiconductor channel layers (e.g., when the multi-gate device 100 includes a fully wound gate (GAA) transistor). In some embodiments, sidewall spacers may also be formed on the sidewalls of the gate structure 108. Reference is made below. Figure 2 The method will be discussed in more detail with respect to the various other components of the multi-gate device 100.

[0080] Please refer to Figure 2This illustration depicts a semiconductor manufacturing method 200 according to various embodiments, comprising the fabrication of a semiconductor device 300 (e.g., comprising a multi-gate device) with a metal gate structure having a convex or concave metal gate profile. Method 200 will be described below in comparison with the fabrication of a fully wound gate (GAA) transistor. However, it is understood that the form of method 200 is equally applicable to other types of multi-gate devices, or to other types of devices implemented by multi-gate devices, without departing from the scope of this invention. In some embodiments, method 200 can be used to manufacture a reference... Figure 1 The multi-gate device 100 is described above. Therefore, one or more of the aforementioned types of the multi-gate device 100 can also be applied to method 200. It is understood that the steps included in method 200 have components with complementary metal-oxide-semiconductor (CMOS) technology process flows, and therefore, only a brief description is given here. In addition, other steps may also be performed before, after, and / or during method 200.

[0081] It should be further noted that in some embodiments, the semiconductor device 300 may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic circuits, etc., but these have been simplified for better understanding of the inventive concept of this invention. In some embodiments, the semiconductor device 300 may include a plurality of semiconductor devices (e.g., transistors) that are interconnected with each other. Furthermore, it should be noted that any descriptions of the process steps of method 200 with reference to the drawings are merely illustrative and do not constitute a limitation beyond the specific descriptions herein.

[0082] Method 200 begins at block 202, where a substrate is provided, which contains partially manufactured apparatus. Please refer to... Figure 3 For example, in one embodiment of block 202, a partially manufactured semiconductor device 300 is provided. Figures 3-5 and Figures 7-12 A cross-sectional schematic diagram of an embodiment of a semiconductor device 300 is provided along a plane, and this plane is substantially parallel to the plane formed by... Figure 1 The plane defined by section A-A' (e.g., along the direction of fin 306). Figures 5A to 9A and Figures 11A to 14A This is an enlarged schematic diagram of a portion 504 of a semiconductor device 300 according to some embodiments of the present invention. Figures 5B to 9B and Figures 11B to 14B This is an enlarged schematic diagram of a portion 504 of a semiconductor device 300 according to other embodiments of the present invention.

[0083] Semiconductor device 300 may be formed on substrate 304. In some embodiments, substrate 304 may be a semiconductor substrate, such as a silicon substrate. Substrate 304 may include various film layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 304 may include various different doping configurations, depending on design requirements known in the art. Substrate 304 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 304 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 304 may, as needed, include epitaxial layers, be strainable to enhance performance, include silicon-on-insulator (SOI) structures, and / or have other suitable reinforcing components.

[0084] like Figure 3 As shown, the semiconductor device 300 includes a fin 306 having a base 304A (formed from a substrate 304), an epitaxial layer 308 having a first composition, and an epitaxial layer 310 having a second composition, the epitaxial layer 310 separating the epitaxial layer 308 having the first composition. In some cases, shallow trench isolation (STI) components may be formed to isolate the fin 306 from adjacent fins. For illustrative purposes, the epitaxial layer 308 having the first composition includes a dummy layer, while the epitaxial layer 310 having the second composition includes a semiconductor channel layer. In one embodiment, the epitaxial layer 308 having the first composition includes SiGe, and the epitaxial layer 310 having the second composition includes silicon (Si). It should also be noted that although the epitaxial layers 308 and 310 are illustrated as having a specific stacking order within the fin 306, where the epitaxial layer 310 is the top layer of the stack of epitaxial layers 308 and 310, other configurations are also possible. For example, in some cases, epitaxial layer 308 can alternatively serve as the top layer of the stack of epitaxial layers 308 and 310. In other words, the growth order and stacking order of epitaxial layers 308 and 310 can be interchanged or used in other ways different from those shown in the figures, while still being covered within the scope of this invention.

[0085] In various embodiments, epitaxial layer 310 (e.g., comprising a second component) or a portion thereof may form a channel region of a fully wound gate (GAA) transistor of semiconductor device 300. For example, epitaxial layer 310 may be referred to as a semiconductor channel layer for forming the channel region of a fully wound gate (GAA) transistor. In various embodiments, the semiconductor channel layer (e.g., epitaxial layer 310 or a portion thereof) may comprise nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. In some embodiments, the semiconductor channel layer may also be used to form local source / drain components of a fully wound gate (GAA) transistor.

[0086] It should be noted that although fin 306 is illustrated as comprising three epitaxial layers 308 and three epitaxial layers 310, this is for illustrative purposes only and is not intended to limit the scope beyond what is expressly stated in the claims. It is understood that any number of epitaxial layers can be formed, wherein the number of epitaxial layers depends, for example, on the number of semiconductor channel layers required for a fully wrapped gate (GAA) transistor. In some embodiments, the number of epitaxial layers 310 (the number of semiconductor channel layers) is between 3 and 10.

[0087] In some embodiments, each of the epitaxial layers 308 (dummy layers) has a thickness in the range of about 4 to 8 nanometers (nm). In some cases, each of the epitaxial layers 310 (semiconductor channel layers) has a thickness in the range of about 4 to 8 nm. As described above, the epitaxial layer 310 can serve as a channel region for a subsequently formed multi-gate device (e.g., a fully wound gate (GAA) transistor), and its thickness can be selected at least in part based on device performance considerations. The epitaxial layer 308 can be used to define the gap distance between adjacent channel regions of a subsequently formed multi-gate device, and its thickness can also be selected at least in part based on device performance considerations.

[0088] The semiconductor device 300 further includes a plurality of gate stacks 316 formed on the fin 306. In one embodiment, the gate stacks 316 are dummy (sacrificial) gate stacks that are subsequently removed in a later process stage of the semiconductor device 300 and replaced by a final gate stack. For example, the gate stacks 316 may be replaced in a later process stage by a high-K dielectric layer (HK) and a metal gate electrode (MG). While the current description pertains to a gate-last process, i.e., forming a dummy gate structure and subsequently replacing it, other configurations are also possible (e.g., a gate-first process). The portion of the fin 306 located below the gate stacks 316 may be referred to as a channel region of the semiconductor device 300. The gate stacks 316 may also define source / drain regions of the fins 306, for example, adjacent to the channel region and the fin regions 306 located on either side of the channel region.

[0089] In some embodiments, the gate stack 316 includes a dielectric layer 320 and an electrode layer 322 situated above the dielectric layer 320. In some embodiments, the dielectric layer 320 includes silicon oxide. Alternatively or additionally, the dielectric layer 320 may include silicon nitride, a high-dielectric-constant dielectric material, or other suitable materials. In some embodiments, the electrode layer 322 may include polysilicon. In some embodiments, after the gate stack 316 is formed, one or more spacer layers 325 may be formed on the sidewalls of the gate stack 316. In some cases, one or more spacer layers 325 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, low-k material (e.g., having a dielectric constant 'k' < 7), and / or combinations thereof. In some embodiments, one or more spacer layers 325 include multiple layers, such as a main spacer layer, a liner, and the like.

[0090] Method 200 then proceeds to block 204, where source / drain etching is performed. Still referring to... Figure 3 In one embodiment of block 204, a source / drain etching process is performed on the semiconductor device 300. In some embodiments, the source / drain etching process is performed to remove the exposed epitaxial layers 308 and 310 in the source / drain regions of the semiconductor device 300 to form a trench 330 that exposes the lower portion of the substrate 304. Figure 3 As shown, the source / drain etching process is also used to expose the lateral surfaces of epitaxial layers 308 and 310. In some embodiments, the source / drain etching process may also remove portions of one or more spacer layers 325. In some embodiments, the source / drain etching process may include dry etching, wet etching, and / or combinations thereof.

[0091] Method 200 proceeds to block 206, where the dummy extension layer is removed. Please refer to [link / reference]. Figure 3 and Figure 4For example, in the embodiment of block 206, a dummy epitaxial layer (epitaxy layer 308) is selectively removed (e.g., using a selective etching process), while the semiconductor channel layer (epitaxy layer 310) remains unetched. It is certain that in various examples, the selective removal of the dummy epitaxial layer completely removes epitaxial layer 308. The selective etching process can be performed using trench 330 provided by a source / drain etching process (block 204). In some embodiments, the selective etching process may include a selective wet etching process. In some cases, selective wet etching includes ammonia (NH3) and / or ozone (O3). By way of example only, a selective wet etching process includes tetra-methyl ammonium hydroxide (TMAH). In some embodiments, the selective etching process may include a dry, plasma-free etching process. In some examples, the selective etching process may include etching using a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O), hydrofluoric acid (HF), buffered HF, and / or fluorine (F2)-based etching. In some examples, fluorine (F2)-based etching may include fluorine (F2) distal plasma etching. It should be noted that, as a result of the selective removal of the dummy epitaxial layer (epitaxy layer 308), a gap (or cavity) 402 is formed between adjacent semiconductor channel layers (epitaxy layers 310). As shown, the gap 402 exposes the surfaces of the semiconductor channel layers (epitaxy layers 310). Specifically, the gap 402 exposes the bottom surface of the topmost epitaxial layer 310, the top surface of the base layer 304A, and the top and bottom surfaces of the semiconductor channel layer (epitaxy layer 310) disposed between the topmost epitaxial layer 310 and the base layer 304A.

[0092] After removing the dummy epitaxial layer (block 206), method 200 proceeds to block 208, where a liner is deposited. Please refer to... Figure 4 and Figure 5 / Figure 5A / Figure 5BIn the embodiment of block 208, the liner 502 is conformally deposited over the semiconductor device 300 and within the trench 330, including an exposed surface along the trench 330. The liner 502 is also conformally deposited within the gap (or cavity) 402, including an exposed surface along the gap (or cavity) 402, which was previously formed by removing a dummy epitaxial layer (block 206). For example, the liner 502 is deposited along the sidewall surfaces of one or more spacer layers 325, the side surfaces of the semiconductor channel layer (epitaxy layer 310), the bottom surface of the topmost epitaxial layer 310, the top surface of the substrate 304A, and the top and bottom surfaces of the semiconductor channel layer (epitaxy layer 310) disposed between the topmost epitaxial layer 310 and the substrate 304A. In some examples, the liner 502 may be described as wrapping around the exposed surface of the semiconductor channel layer (epitaxy layer 310). In various embodiments, the liner 502 may comprise an oxide layer (e.g., silicon oxide (SiO2)) or a carbon-containing layer (e.g., silicon carbide (SiOC)). In some examples, the liner 502 may comprise another dielectric material, such as silicon carbide, a low dielectric constant material (e.g., having a dielectric constant 'k' < 7), or another suitable oxide or carbon-containing layer. In some cases, the liner 502 may be conformally deposited using an ALD process. Alternatively, the liner 502 may be deposited using a chemical vapor deposition (CVD) process, a subatmospheric CVD (SACVD) process, a flowable CVD process, or other suitable processes. In some embodiments, the thickness of the liner 502 may be in the range of about 1 to 3 nm.

[0093] For illustrative purposes, Figure 5A and Figure 5B According to various embodiments of the present utility model, the following are provided: Figure 5 An enlarged schematic diagram of portion 504 of the semiconductor device 300. Specifically, portion 504 shows a pair of adjacent semiconductor channel layers (epitaxy layers 310), including the side surfaces of the semiconductor channel layers and the opposing surfaces of the pair of adjacent semiconductor channel layers. In various embodiments, the specific composition of the substrate 502 may be selected depending on whether the metal gate profile required in the final device structure is convex or concave. Figure 5A As shown, if the metal gate profile in the final device structure will have a convex shape, then the liner 502 may include an oxide layer 502A, also referred to as oxide liner 502A. Alternatively, as... Figure 5B As shown, if the metal gate profile in the final device structure will have a concave shape, the liner 502 may include a carbon-containing layer 502B (e.g., SiOC), also known as a carbon-containing liner 502B.

[0094] After forming the substrate 502 (block 208), method 200 proceeds to block 210, where a plasma treatment process is performed. In various embodiments, the type of plasma treatment process may depend on whether the desired metal gate profile in the final device structure is convex or concave. For example, if the substrate comprises an oxide layer (e.g., where the metal gate profile in the final device structure will be convex), a nitrogen-based plasma process (e.g., using NH3 or N2 gas) may be performed, and if the substrate comprises a silicon oxide layer (e.g., where the metal gate profile in the final device structure will be concave), an oxygen-based plasma process (e.g., using O2 gas) may be performed. In some embodiments, the plasma treatment process may include low-pressure plasma treatment. For example, in some cases, the plasma treatment may be performed at a pressure less than about 1 Torr. As an example, in the embodiment of block 210, Figure 6A and Figure 6B The effects of plasma treatment processes on different components of liner 502 to form plasma-treated liner 502 are shown.

[0095] Specifically, Figure 6A Provides oxide liner 502A (e.g.) Figure 5A This is an enlarged schematic diagram of portion 504 of a semiconductor device 300. In this example, a nitrogen-based plasma process 602 (e.g., using NH3 or N2 gas) can be performed to form a nitrogen-rich region 606 within an oxide liner 502A disposed on a portion of the oxide liner 502A above the side end (or side end region) of an adjacent semiconductor channel layer (epipolar layer 310). The formation of the nitrogen-rich region 606 can simultaneously provide or define a low-nitrogen concentration region 608 (or in some cases, a nitrogen-free region 608) disposed on the oxide liner 502A above the central region of the adjacent semiconductor channel layer (epipolar layer 310). Furthermore, the nitrogen concentration difference between the nitrogen-rich region 606 having a first nitrogen concentration and the low-nitrogen concentration region 608 (or nitrogen-free region 608) having a second nitrogen concentration less than the first nitrogen concentration is sufficient to provide etch selectivity between the two regions, i.e., the nitrogen-rich region 606 and the low-nitrogen concentration region 608 (or nitrogen-free region 608). As described in more detail below, during a subsequent etching process, the low-nitrogen concentration region 608 (or nitrogen-free region 608) is removed, while the nitrogen-rich region 606 is retained, thereby defining the gap between adjacent semiconductor channel layers (epitaxy layer 310), and subsequently forming a metal gate structure with a convex metal gate profile.

[0096] Figure 6B Provides 502B containing a carbon-containing liner (e.g.) Figure 5B This is an enlarged schematic diagram of portion 504 of a semiconductor device 300. In this example, an oxygen-based plasma process 604 (e.g., using O2 gas) can be performed to form a carbon-deficient region 610 within a carbon-containing substrate 502B disposed above a side end (or side end region) of an adjacent semiconductor channel layer (epipolar layer 310). The formation of the carbon-deficient region 610 can simultaneously define a high-carbon-concentration region 612 of the carbon-containing substrate 502B disposed above a central region of the adjacent semiconductor channel layer (epipolar layer 310) (e.g., a region of the carbon-containing substrate 502B substantially unaffected by the oxygen-based plasma process 604). Furthermore, the carbon concentration difference between the carbon-deficient region 610 having a first carbon concentration and the high-carbon-concentration region 612 having a second carbon concentration greater than the first carbon concentration is sufficient to provide etch selectivity between the two regions, i.e., between the carbon-deficient region 610 and the high-carbon-concentration region 612. As described in more detail below, during a subsequent etching process, the carbon-deficient region 610 is removed, while the high-carbon-concentration region 612 is retained, thereby defining the gap between adjacent semiconductor channel layers (epitaxy layer 310), and subsequently forming a metal gate structure with a concave metal gate profile.

[0097] After the plasma processing (block 210), method 200 proceeds to block 212, where an intermediate layer is deposited. Please refer to... Figure 5 and Figure 7 / Figure 7A / Figure 7B In the embodiment of block 212, an interposer 702 is deposited over the semiconductor device 300 and over the trench 330 liner 502. The interposer 702 is also deposited over the gap (or cavity) 402 liner 502. Therefore, the interposer 702 can be used to fill the remaining space of the gap (or cavity) 402 formed by removing the dummy epitaxial layer 308, and to fill the remaining portion of the trench 330. Figure 7A The example provides an enlarged schematic diagram of portion 504 of a semiconductor device 300, which includes a nitrogen-based plasma process 602 (such as...). Figure 6A Following the oxide liner 502A, it further includes an interlayer 702. Similarly, Figure 7B The example provides an enlarged schematic diagram of portion 504 of a semiconductor device 300, which includes a portion 604 undergoing an oxygen plasma process (such as...). Figure 6B The carbon-containing liner 502B following the middle layer, and further includes an intermediate layer 702.

[0098] After depositing the intermediate layer (block 212), method 200 proceeds to block 214, where the previously deposited liner and intermediate layer are etched. Please refer to... Figure 7 / Figure 7A / Figure 7B and Figure 8 / Figure 8A / Figure 8B In the embodiment of block 214, an etching process is performed on the semiconductor device 300. In various examples, the etching process etches the liner 502 and the interposer 702 from above the semiconductor device 300 and along the sidewalls of the trench 330, while retaining at least a portion of the liner 502 and the interposer 702 between adjacent semiconductor channel layers (epitaxy layers 310). In other words, the etching process of block 214 etches the liner 502 and the interposer 702 at least partially between the side ends of adjacent semiconductor channel layers (epitaxy layers 310) to form a recess 802 along the sidewalls of the trench 330, for example, along the side surfaces of the liner 502 and the interposer 702 (e.g., facing the trench 330). In various embodiments, as described below, the recess 802 is used to define subsequently formed internal spacers. It should be noted that after the groove 802 is formed, and in embodiments including the oxide liner 502A, a portion of the nitrogen-rich region 606 is retained within a portion of the oxide liner 502A, and is located near the side end (or adjacent side end or side end region) of the adjacent semiconductor channel layer (epitaxy layer 310), such as... Figure 8A As shown. Similarly, after the groove 802 is formed, and for embodiments including a carbon-containing substrate 502B, a portion of the carbon-deficient region 610 is retained within a portion of the carbon-containing substrate 502B, which is located near the side end (or adjacent side end or side end region) of the adjacent semiconductor channel layer (epitaxy layer 310), such as Figure 8B As shown. As an example, the etching process (block 214) can be performed using a wet etching process. In some embodiments, the wet etching process may include phosphoric acid (H3PO4) chemical etching of the substrate 502. In some alternative examples, a cycle of a high-temperature sulfuric peroxide mixture (HTSPM) and dilute hydrofluoric acid (dHF), ozone (O3) and dHF, or combinations thereof, can be used to perform the etching process.

[0099] As an example, the etching process of block 214 etches the substrate 502 and the interposer 702 to a depth 'D' to form a groove 802 along the sidewall of trench 330. Although Figure 8 / Figure 8A / Figure 8BThe example depicts a substantially equal etch depth 'D' for both the substrate 502 and the interposer 702, but other embodiments are possible. For example, each of the substrate 502 and the interposer 702 may have different etch rates due to the different material compositions of each. The etch rate may also vary further based on the specific etchant used during the etch process. Thus, in some embodiments, the etch depth 'D' of the substrate 502 may be greater than the etch depth 'D' of the interposer 702. Alternatively, in some cases, the etch depth 'D' of the interposer 702 may be greater than the etch depth 'D' of the substrate 502. In some embodiments, the difference in etch depth 'D' between each of the substrate 502 and the interposer 702 may be at least 1 nm.

[0100] Method 200 then proceeds to block 216, where internal spacers are formed. Please refer to... Figure 8 / Figure 8A / Figure 8B and Figure 9 / Figure 9A / Figure 9B In the embodiment of block 216, internal spacer material is conformally deposited on the semiconductor device 300, within the trench 330, and within the recess 802 (e.g., formed by etching the substrate 502 and the interposer 702 at block 214). In some embodiments, the internal spacer material may comprise amorphous silicon. In some examples, the internal spacer material may comprise dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, low dielectric constant materials (e.g., having a dielectric constant 'k' < 7), and / or combinations thereof. As an example, the internal spacer material can be formed by conformally depositing the internal spacer material on the semiconductor device 300 using processes such as CVD, SACVD, flowable CVD, ALD, or other suitable processes. After depositing the internal spacer material, an internal spacer etch-back process is performed to etch the internal spacer material from above the semiconductor device 300 and along the sidewalls of the trench 330, while the internal spacer material remains disposed within the recess 802, thereby providing internal spacers 902 in the semiconductor device 300. Figure 9 / Figure 9A / Figure 9B As shown, the internal spacer 902 is formed to contact the etched liner 502 and the etched intermediate layer 702. Specifically, as Figure 9A As shown, and for the embodiment including oxide liner 502A, the internal spacer 902 is formed to partially contact the nitrogen-rich region 606 of oxide liner 502A near the side end of the adjacent semiconductor channel layer (epitaxy layer 310). Similarly, as Figure 9BAs shown, and for embodiments including a carbon-containing substrate 502B, the internal spacer 902 is formed to partially contact a carbon-deficient region 610 of the carbon-containing substrate 502B near the side end of an adjacent semiconductor channel layer (epitaxy layer 310). The internal spacer etch-back process for forming the internal spacer 902 may include a wet etching process, a dry etching process, or a combination thereof. In some cases, any remaining portions of internal spacer material, retained on the top surface of the semiconductor device 300 and / or on the sidewalls or bottom surface of the trench 330, may be removed during subsequent cleaning processes (e.g., prior to epitaxial growth of source / drain components), for example, after the internal spacer etch-back process. In various examples, the internal spacer 902 may extend at least partially beneath one or more spacer layers 325 (formed on the sidewalls of the gate stack 316) and adjacent to subsequently formed source / drain components, as described below.

[0101] Method 200 then proceeds to block 218, where the source / drain components are formed. Please refer to... Figure 9 and Figure 10 In the embodiment of block 218, and after the formation of the internal spacer 902, the source / drain component 1002 is formed in the source / drain regions adjacent to and on both sides of the gate stack 316 of the semiconductor device 300. For example, the source / drain component 1002 may be formed within the trench 330 of the semiconductor device 300, over an exposed portion of the substrate 304, and in contact with the adjacent internal spacer 902 and the semiconductor channel layer (epitaxy layer 310) of the semiconductor device 300. In some embodiments, a cleaning process may be performed immediately prior to the formation of the source / drain component 1002 to remove any residual portions of the internal spacer material, as previously described. The cleaning process may include wet etching, dry etching, or a combination thereof.

[0102] In some embodiments, the source / drain component 1002 is formed by epitaxially growing a semiconductor material layer in the source / drain region. In various embodiments, the semiconductor material layer grown to form the source / drain component 1002 may comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain component 1002 may be formed by one or more epitaxial (epi) processes. In some embodiments, the source / drain component 1002 may be in-situ doped during the epitaxial process. For example, in some embodiments, the epitaxially grown SiGe source / drain component may be doped with boron. In some cases, the epitaxially grown Si epitaxial source / drain component may be doped with carbon to form a Si:C source / drain component, doped with phosphorus to form a Si:P source / drain component, or doped with both carbon and phosphorus to form a SiCP source / drain component. In some embodiments, the source / drain component 1002 is not doped in situ, but rather a doping process is performed to dope the source / drain component 1002.

[0103] After the source / drain components 1002 are formed, in some embodiments, a contact etch stop layer (CESL) 1004 may be conformally formed on the semiconductor device 300, such as... Figure 10 As shown. In some embodiments, the contact etch stop layer (CESL) 1004 may comprise a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. In some embodiments, an inter-layer dielectric (ILD) layer 1006 may be formed on the contact etch stop layer (CESL) 1004, such as... Figure 10As shown. In various cases, the interlayer dielectric (ILD) layer 1006 may comprise materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)), and / or other suitable dielectric materials. In some embodiments, after forming the interlayer dielectric (ILD) layer 1006, the semiconductor device 300 may undergo a high thermal budget process to anneal the interlayer dielectric (ILD) layer 1006. In some embodiments, after the contact etch stop layer (CESL) 1004 and the interlayer dielectric (ILD) layer 1006 are formed, chemical mechanical polishing (CMP) can be performed to remove portions of the interlayer dielectric (ILD) layer 1006 and the contact etch stop layer (CESL) 1004 located above the gate stack 316, as well as any hard masking layer that may exist above the gate stack 316, thereby planarizing the top surface of the semiconductor device 300 and exposing the top surface of the electrode layer 322 of the gate stack 316.

[0104] Method 200 then proceeds to block 220, where the intermediary layer is removed. Please refer to [link / reference]. Figure 10 and Figure 11 / Figure 11A / Figure 11B For example, in the embodiment of block 220, the electrode layer 322 of the gate stack 316 (e.g., exposed by a chemical mechanical polishing (CMP) process as described above) can initially be removed by a suitable etching process to form trench 1102 and expose dielectric layer 320. Subsequently, in some embodiments, an etching process can be performed to remove the exposed dielectric layer 320 from trench 1102. In some examples, the etching process for removing electrode layer 322 and dielectric layer 320 may include wet etching, dry etching, or a combination thereof. It should be noted that the removal of electrode layer 322 and dielectric layer 320 provides for the removal of a dummy gate (gate stack 316), for example, as part of a gate replacement process.

[0105] Still refer to Figure 10 and Figure 11 / Figure 11A / Figure 11BFor example, in another embodiment of block 220, and after removing electrode layer 322 and dielectric layer 320, the interposer 702 is partially removed between adjacent semiconductor channel layers (epitaxy layers 310) in the channel region of semiconductor device 300 (e.g., by using a wet etching process), while the semiconductor channel layers (epitaxy layers 310) and internal spacers 902 remain substantially unetched. The etching process can be performed by removing the trench 1102 provided by removing electrode layer 322 and dielectric layer 320. Additionally, in various embodiments, removing interposer 702 also removes selected portions of substrate 502.

[0106] For example, in an embodiment including an oxide liner 502A processed using a nitrogen-based plasma process 602, the portion of the interposer 702 removed is also used to remove the low-nitrogen concentration region 608 (or nitrogen-free region 608) of the oxide liner 502A. Due to the etch selectivity between the nitrogen-rich region 606 and the low-nitrogen concentration region 608 (or nitrogen-free region 608) of the oxide liner 502A, the nitrogen-rich region 606 of the oxide liner 502A remains disposed above the side region of the adjacent semiconductor channel layer (e.g., Figure 11A The nitrogen-rich region 606 of the retained oxide liner 502A, together with the adjacent semiconductor channel layer (epitaxy layer 310), is used to define a concave gap 1104 between the adjacent semiconductor channel layers. As shown, the gap 1104 exposes a first portion of the epitaxial layer 310, while a second portion of the epitaxial layer 310 located on both sides of the first portion is covered by the nitrogen-rich region 606 of the oxide liner 502A, and a third portion of the epitaxial layer 310 remains covered by the internal spacer 902. The gap 1104 also exposes the sidewalls of the internal spacer 902 on both sides of the gap 1104. In some embodiments, as described below, the metal gate structure subsequently formed within the gap 1104 will have a metal gate profile having a convex shape complementary to the concavity of the gap 1104.

[0107] Alternatively, in embodiments including a carbon-containing substrate 502B treated using oxygen plasma process 604, the portion removing the interposer 702 is also used to remove the carbon-deficient region 610 of the carbon-containing substrate 502B, and due to the etch selectivity between the carbon-deficient region 610 and the high-carbon-concentration region 612 of the carbon-containing substrate 502B, the high-carbon-concentration region 612 of the carbon-containing substrate 502B remains disposed above the central region of the adjacent semiconductor channel layer (e.g., Figure 11BThe high-carbon-concentration region 612 of the retained carbon-containing substrate 502B, together with the adjacent semiconductor channel layer (epitaxy layer 310), is used to define a convex gap 1106 between the adjacent semiconductor channel layers. As shown, a first portion of the epitaxial layer 310 remains covered by the high-carbon-concentration region 612 of the carbon-containing substrate 502B, while the gap 1106 exposes a second portion of the epitaxial layer 310 located on both sides of the first portion, and a third portion of the epitaxial layer 310 remains covered by the internal spacer 902. The gap 1106 also exposes the sidewalls of the internal spacer 902 on both sides of the gap 1106. In some embodiments, as described below, the metal gate structure subsequently formed within the gap 1106 will have a metal gate profile having a concave shape complementary to the convexity of the gap 1106.

[0108] In some cases, the etching process for block 220 may include a wet etching process, as described above. Additionally, in some embodiments, ammonia (NH3) and / or ozone (O3) may be used to perform the etching process for block 220. In another example, tetramethylammonium hydroxide (TMAH) may be used to perform the etching process. In some embodiments, the etching process may include a dry, plasma-free etching process. In some examples, the etching process may include etching using a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O), hydrofluoric acid (HF), buffered HF, and / or fluorine (F2)-based etching. In some examples, fluorine (F2)-based etching may include fluorine (F2) distal plasma etching.

[0109] Method 200 then proceeds to block 222, where the gate structure is formed. Please refer to... Figure 11 / Figure 11A / Figure 11B , Figure 12 / Figure 12A / Figure 12B , Figure 13A / Figure 13B and Figure 14A / Figure 14BFor example, in the embodiment of block 222, a final gate structure 1202 for semiconductor device 300 is formed. Gate structure 1202 may comprise a high-dielectric-constant / metal gate stack, but may also have other compositions. In some embodiments, gate structure 1202 may form a gate that interacts with multiple channels provided by a plurality of semiconductor channel layers (eptaxial layers 310) in the channel region of semiconductor device 300. In some embodiments, gate structure 1202 includes a dielectric layer 1204, which comprises an interfacial layer (IL) 1204A and a high-dielectric-constant dielectric layer 1204B formed on the interfacial layer (IL) 1204A. In various embodiments, the interfacial layer (IL) 1204A and the high-dielectric-constant dielectric layer 1204B together define the gate dielectric layer of the gate structure for semiconductor device 300. In some embodiments, the gate dielectric layer has a total thickness of about 1 to 5 nm. The high-dielectric-constant dielectric layer used herein comprises a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermally oxidized silicon (~3.9). Generally, the gate dielectric layer can be formed on the respective surfaces of gaps 1104 and 1106. In some embodiments, such as Figure 12A As shown, the interface layer (IL) 1204A and the high-dielectric-constant dielectric layer 1204B can be deposited on the exposed surface of the nitrogen-rich region 606 of the epitaxial layer 310 and the oxide substrate 502A. Similarly, in some embodiments and as shown Figure 12B As shown, the interface layer (IL) 1204A and the high-dielectric-constant dielectric layer 1204B can be deposited on the exposed surface of the high-carbon-concentration region 612 of the epitaxial layer 310 and the carbon-containing substrate 502B. Figure 12A and Figure 12B In some embodiments, the interface layer (IL) 1204A can be deposited by a CVD process, thereby depositing on the nitrogen-rich region 606 or the high carbon concentration region 612. In some cases, the dielectric layer 1204, which includes the interface layer (IL) 1204A and / or the high dielectric constant dielectric layer 1204B, can also be deposited on the sidewall surface of the internal spacer 902.

[0110] In other embodiments, such as Figure 13AAs shown, the interface layer (IL) 1204A is initially formed by oxidizing the surface of the epitaxial layer 310. For the portions of the epitaxial layer 310 not covered by the nitrogen-rich region 606, the interface layer (IL) 1204A can be readily formed on the exposed surface of the epitaxial layer 310 during its formation. For the portions of the epitaxial layer 310 covered by the nitrogen-rich region 606, an oxidant can diffuse through the nitrogen-rich region 606 during its formation to form the interface layer (IL) 1204A at the interface between the epitaxial layer 310 and the nitrogen-rich region 606. In this way, the interface layer (IL) 1204A can be formed along the entire surface of the epitaxial layer 310 between the internal spacers 902. Subsequently, a high-dielectric-constant dielectric layer 1204B can be deposited on top of the nitrogen-rich region 606 and on the interface layer (IL) 1204A formed on the exposed surface of the epitaxial layer 310 (the region not covered by the nitrogen-rich region 606). Figure 13A In some embodiments, since an interface layer (IL) 1204A is formed at the interface between the epitaxial layer 310 and the nitrogen-rich region 606 by diffusion of the oxidant through the nitrogen-rich region 606, the interface layer (IL) 1204A disposed at the interface between the epitaxial layer 310 and the nitrogen-rich region 606 can have a different thickness (e.g., thinner in some cases) compared to the interface layer (IL) 1204A disposed on the exposed surface of the epitaxial layer 310 (the region not covered by the nitrogen-rich region 606). Similarly, in some embodiments and as in... Figure 13B As shown, the interface layer (IL) 1204A is initially formed by oxidizing the surface of the epitaxial layer 310. For the portions of the epitaxial layer 310 not covered by the high carbon concentration region 612, the interface layer (IL) 1204A can be easily formed on the exposed surface of the epitaxial layer 310 during its formation. For the portions of the epitaxial layer 310 covered by the high carbon concentration region 612, an oxidant can diffuse through the high carbon concentration region 612 during its formation to form the interface layer (IL) 1204A at the interface between the epitaxial layer 310 and the high carbon concentration region 612. In this way, the interface layer (IL) 1204A can be formed along the entire surface of the epitaxial layer 310 between the internal spacers 902. Subsequently, a high-dielectric-constant dielectric layer 1204B can be deposited over the high-carbon-concentration region 612 and over the interface layer (IL) 1204A formed on the exposed surface of the epitaxial layer 310 (the region not covered by the high-carbon-concentration region 612). Figure 13BIn the embodiments, since an interface layer (IL) 1204A is formed at the interface between the epitaxial layer 310 and the high carbon concentration region 612 by diffusion of the oxidant through the high carbon concentration region 612, the interface layer (IL) 1204A disposed at the interface between the epitaxial layer 310 and the high carbon concentration region 612 can have a different thickness (e.g., thinner in some cases) compared to the interface layer (IL) 1204A disposed on the exposed surface of the epitaxial layer 310 (the area not covered by the high carbon concentration region 612).

[0111] In some other embodiments, such as Figure 14A As shown, the interface layer (IL) 1204A is initially formed over the portion of the epitaxial layer 310 not covered by the nitrogen-rich region 606, but not over the portion of the epitaxial layer 310 covered by the nitrogen-rich region 606. Subsequently, a high-dielectric-constant dielectric layer 1204B can be deposited over the nitrogen-rich region 606 and over the interface layer (IL) 1204A formed on the exposed surface of the epitaxial layer 310 (the region not covered by the nitrogen-rich region 606). Similarly, in some embodiments and as... Figure 14B As shown, the interface layer (IL) 1204A is initially formed on the portion of the epitaxial layer 310 not covered by the high carbon concentration region 612, but not on the portion of the epitaxial layer 310 covered by the high carbon concentration region 612. Subsequently, a high dielectric constant dielectric layer 1204B can be deposited on the high carbon concentration region 612 and on the interface layer (IL) 1204A formed on the exposed surface of the epitaxial layer 310 (the region not covered by the high carbon concentration region 612).

[0112] In some embodiments, the interface layer (IL) 1204A may comprise a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some examples, the high dielectric constant dielectric layer 1204B may comprise hafnium oxide (HfO2). Alternatively, the high dielectric constant dielectric layer 1204B may comprise other high dielectric constant dielectric materials, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, silicon oxynitride (SiON), combinations thereof, or other suitable materials. Unless otherwise stated in the foregoing discussion, in various embodiments, the interface layer (IL) 1204A and the high dielectric constant dielectric layer 1204B may be formed by thermal oxidation, ALD, physical vapor deposition (PVD), pulsed laser deposition (PLD), CVD, and / or other suitable methods.

[0113] Still refer to Figure 11 / Figure 11A / Figure 11B , Figure 12 / Figure 12A / Figure 12B , Figure 13A / Figure 13B and Figure 14A / Figure 14B For example, a metal gate including a metal layer 1206 is formed on a gate dielectric layer (e.g., on an interface layer (IL) and a high-dielectric-constant dielectric layer). The metal layer 1206 may comprise a metal, a metal alloy, or a metal silicide. Additionally, the formation of the gate dielectric layer / metal gate stack may include depositing various gate materials, one or more substrates, and one or more chemical mechanical polishing (CMP) processes to remove excess gate material, thereby planarizing the top surface of the semiconductor device 300.

[0114] In some embodiments, metal layer 1206 may comprise a single layer or other multilayer structure, such as various combinations of metal layers having a selected work function to enhance device performance (work function metal layers), a substrate, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide. As an example, metal layer 1206 may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metallic materials, or combinations thereof. In various embodiments, metal layer 1206 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, metal layer 1206 may be formed separately for N-type and P-type transistors, wherein different metal layers may be used. Moreover, metal layer 1206 may provide an N-type or P-type work function and may serve as the gate electrode of a transistor (e.g., a fully wound gate (GAA) transistor), and in at least some embodiments, metal layer 1206 may comprise a polysilicon layer. Regarding the illustrated and described device, the gate structure includes portions of each epitaxial layer 310 inserted therein, each serving as a semiconductor channel layer for a fully wound gate (GAA) transistor.

[0115] Therefore, as Figure 12A / Figure 13A / Figure 14A As shown, the portion of the gate structure 1202 (including a dielectric layer 1204 and a metal layer 1206) formed in the gap 1104 between adjacent semiconductor channel layers (epitaxy layers 310) has a convex metal gate profile, which is complementary to the concave shape of the gap 1104 within which the gate structure 1202 is disposed. For example, the convex metal gate profile may have a thickness T1 near the center of the portion of the gate structure 1202 disposed between the central regions of adjacent semiconductor channel layers (adjacent epitaxial layers 310), wherein the thickness T1 is greater than the thickness T2 near the side ends of the portion of the gate structure 1202 disposed between the side ends of adjacent semiconductor channel layers (adjacent epitaxial layers 310). Similarly, as Figure 12B / Figure 13B / Figure 14BAs shown, the portion of the gate structure 1202 (including a dielectric layer 1204 and a metal layer 1206) formed in the gap 1106 between adjacent semiconductor channel layers (epitaxy layers 310) has a concave metal gate profile, which is complementary to the convex shape of the gap 1106 within which the gate structure 1202 is disposed. For example, the concave metal gate profile may have a thickness T3 near the center of the portion of the gate structure 1202 disposed between the central regions of adjacent semiconductor channel layers (adjacent epitaxial layers 310), wherein the thickness T3 is less than the thickness T4 near the side ends of the portion of the gate structure 1202 disposed between the side ends of adjacent semiconductor channel layers (adjacent epitaxial layers 310). In some embodiments, the thickness T1 may be substantially the same as the thickness T4. It should be noted that, although for ease of explanation... Figure 12 The liner 502 is not specifically shown, but as Figure 12A / Figure 13A / Figure 14A and Figure 12B / Figure 13B / Figure 14B As shown, there is a nitrogen-rich region 606 of oxide liner 502A and a high carbon concentration region 612 of carbon liner 502B.

[0116] Generally, the semiconductor device 300 can be further processed to form various components and regions known in the art. For example, further processing can form various contacts / vias / wiring and multilayer interconnect components (e.g., metal layers and interlayer dielectric layers) on the substrate 304 to connect various components to form a functional circuit, which may include one or more multi-gate devices (e.g., one or more fully wound gate (GAA) transistors). In a further example, the multilayer interconnects may include vertical interconnects (e.g., vias or contacts) and horizontal interconnects (e.g., metal wiring). The various interconnect components can be made of various conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form copper-related multilayer interconnect structures. Furthermore, additional process steps can be performed before, during, and after method 200, and some of the above-described process steps can be modified, replaced, or omitted according to various embodiments of method 200.

[0117] The description provided herein discloses methods and structures for modulating the metal gate profile of a multi-gate device (e.g., a fully wound gate (GAA) device). In various embodiments, the metal gate profile in the final device structure (e.g., between adjacent semiconductor channel layers) may be convex or concave. In some examples, the method of modulating the metal gate profile includes initially removing a dummy layer (e.g., a silicon-germanium (SiGe) layer) inserted into an adjacent semiconductor channel layer, and then depositing a liner and an interposer to fill the cavity formed by removing the dummy layer. The liner comprises an oxide layer, a carbon-containing layer, or other suitable layers, and the specific composition of the liner may be selected according to the desired metal gate profile in the final device structure. After depositing the liner and before depositing the interposer, a plasma process may be performed to treat the liner (e.g., a nitrogen-based plasma process is used if the liner contains an oxide layer, or an oxygen-based plasma process is used if the liner contains a silicon carbide layer). After the plasma treatment of the liner, an interposer may be deposited to fill the remaining space in the cavity. During subsequent processes, the remaining portion of the interposer and selected portions of the plasma-treated liner are removed to form a gap between adjacent semiconductor channel layers, within which a metal gate structure is formed. For example, if the liner comprises an oxide layer, the removal of part of the interposer also removes low-nitrogen concentration regions (or nitrogen-free regions) of the oxide liner, while nitrogen-rich regions of the oxide liner are retained above the side regions of the adjacent semiconductor channel layers. The retained nitrogen-rich regions of the oxide liner, together with the adjacent semiconductor channel layers, define a concave gap between the adjacent semiconductor channel layers. Therefore, a metal gate structure can subsequently be formed within the gap, wherein the metal gate profile of the metal gate structure has a convex shape complementary to the concavity of the gap. Alternatively, if the liner comprises a carbon-containing layer, the removal of part of the interposer also removes carbon-deficient regions of the carbon-containing liner, while high-carbon concentration regions of the carbon-containing liner are retained above the central region of the adjacent semiconductor channel layers. The retained high-carbon concentration regions of the carbon-containing liner, together with the adjacent semiconductor channel layers, define a convex gap between the adjacent semiconductor channel layers. Therefore, a metal gate structure can then be formed within the gap, wherein the metal gate profile of the metal gate structure has a concave shape that complements the convexity of the gap. Thus, embodiments of the present invention provide effective control over the metal gate profile achieved as part of a discardable intermediate process, which can be adjusted according to device design and / or performance requirements.

[0118] Therefore, one embodiment of the present invention describes a method of manufacturing a semiconductor device, comprising providing a fin comprising an epitaxial layer stack having a plurality of semiconductor channel layers inserted by a plurality of dummy layers. In some embodiments, the method further comprises removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. In some examples, the method further comprises depositing a liner over the surface of the adjacent semiconductor channel layer exposed by the first gap. In some embodiments, the method further comprises performing a plasma processing process on the liner to provide a plasma-treated liner. In some cases, the method further comprises removing a first portion of the plasma-treated liner to form a second gap between the adjacent semiconductor channel layers, and a second portion of the adjacent semiconductor channel layer remains disposed on the surface of the adjacent semiconductor channel layer.

[0119] In some embodiments, the liner comprises an oxide layer, and the plasma processing process comprises a nitrogen-based plasma process. In some embodiments, the liner comprises a carbon-containing layer, and the plasma processing process comprises an oxygen-based plasma process. In some embodiments, the first portion of the plasma-treated liner comprises an oxide layer having a first nitrogen concentration, and the second portion of the plasma-treated liner comprises the oxide layer having a second nitrogen concentration greater than the first nitrogen concentration. In some embodiments, the first portion of the plasma-treated liner comprises a carbon-containing layer having a first carbon concentration, and the second portion of the plasma-treated liner comprises the carbon-containing layer having a second carbon concentration greater than the first carbon concentration. In some embodiments, the second portion of the plasma-treated liner is retained on the surface of the adjacent semiconductor channel layer, together with the adjacent semiconductor channel layer, to define a second gap between the adjacent semiconductor channel layers, and the second gap is concave. In some embodiments, the second portion of the plasma-treated liner is retained on the surface of the adjacent semiconductor channel layer, together with the adjacent semiconductor channel layer, to define a second gap between the adjacent semiconductor channel layers, and the second gap is convex. In some embodiments, the method of manufacturing the semiconductor device further includes: after performing the plasma processing process and before removing the first portion of the plasma-treated liner, forming an interposer layer over the liner within the first gap, wherein the interposer layer is used to substantially fill the remaining portion of the first gap; and after forming an internal spacer, removing the interposer layer, wherein removing the interposer layer further removes the first portion of the plasma-treated liner. In some embodiments, the method further includes: before forming the internal spacer, etching side ends of the liner and the interposer layer, wherein etching the side ends recesses the side ends of the liner to a first depth and the side ends of the interposer layer to a second depth different from the first depth. In some embodiments, the method further includes: after removing the first portion of the plasma-treated liner, forming a portion of a gate structure within the second gap, wherein the portion of the gate structure has a convex shape complementary to the concave shape of the second gap.

[0120] In another embodiment, a method of manufacturing a semiconductor device is discussed, comprising providing a fin having an epitaxial layer defining a semiconductor channel layer, and using a liner to surround an exposed surface of the epitaxial layer. In some examples, the method further comprises performing a plasma processing process on the liner to define a first region of the liner disposed over a first portion of the epitaxial layer, and a second region of the liner disposed over a second portion of the epitaxial layer. In some embodiments, the method further comprises removing the first region of the liner to form a gap between the epitaxial layer and an adjacent epitaxial layer defining an adjacent semiconductor channel layer, and the second region of the liner remains disposed over the second portion of the epitaxial layer. In some cases, the method further comprises forming a portion of a metal gate structure within the gap, wherein the metal gate profile of the portion of the metal gate structure has a convex or concave shape.

[0121] In some embodiments, the liner comprises an oxide layer, and the plasma processing process comprises a nitrogen-based plasma process. In some embodiments, the liner comprises a carbon-containing layer, and the plasma processing process comprises an oxygen-based plasma process. In some embodiments, a first region of the liner comprises an oxide layer having a first nitrogen concentration, and a second region of the liner comprises the oxide layer having a second nitrogen concentration greater than the first nitrogen concentration. In some embodiments, a first region of the liner comprises a carbon-containing layer having a first carbon concentration, and a second region of the liner comprises the carbon-containing layer having a second carbon concentration greater than the first carbon concentration. In some embodiments, the second region of the liner comprises a nitrogen-rich region of the oxide layer. In some embodiments, the first region of the liner comprises a carbon-deficient region of the carbon-containing layer.

[0122] In another embodiment, a semiconductor device is discussed, comprising a plurality of semiconductor channel layers formed over a substrate. In some embodiments, the semiconductor device further includes internal spacers disposed between adjacent semiconductor channel layers and on both sides of channel regions. In some examples, the semiconductor device further includes a metal gate structure disposed between the adjacent semiconductor channel layers, wherein the internal spacers are disposed on both sides of the metal gate structure, and wherein a liner is disposed between a portion of the metal gate structure and each of the adjacent semiconductor channel layers. In some embodiments, the metal gate profile of the metal gate structure has a convex or concave shape.

[0123] In some embodiments, when the metal gate profile has the convex shape, the metal gate structure has a first thickness near a central portion of the metal gate structure disposed between the central regions of the adjacent semiconductor channel layers, the first thickness being greater than a second thickness of the metal gate structure near the side ends of the metal gate structure disposed between the side ends of the adjacent semiconductor channel layers. In some embodiments, when the metal gate profile has the concave shape, the metal gate structure has a first thickness near a central portion of the metal gate structure disposed between the central regions of the adjacent semiconductor channel layers, the first thickness being less than a second thickness of the metal gate structure near the side ends of the metal gate structure disposed between the side ends of the adjacent semiconductor channel layers.

[0124] The foregoing provides a brief overview of the components of several embodiments of this utility model, enabling those skilled in the art to more readily understand its form. Anyone skilled in the art should understand that this utility model can be readily used as a basis for modifications or designs to other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. It will also be understood by those skilled in the art that equivalent structures described above do not depart from the spirit and scope of this utility model, and that modifications, substitutions, and refinements can be made without departing from its spirit and scope.

Claims

1. A semiconductor device, characterized in that, include: Multiple semiconductor channel layers are formed on a substrate; Internal spacers are disposed between adjacent semiconductor channel layers and on both sides of a channel region in the plurality of semiconductor channel layers; as well as A metal gate structure is disposed between adjacent semiconductor channel layers, wherein internal spacers are disposed on both sides of the metal gate structure, and wherein a liner is disposed between a portion of the metal gate structure and each of the adjacent semiconductor channel layers; The metal gate profile of the metal gate structure is convex or concave.

2. The semiconductor device as claimed in claim 1, characterized in that, When the metal gate profile has the convex shape, the metal gate structure has a first thickness near a central portion of the metal gate structure disposed between the central regions of the adjacent semiconductor channel layers, the first thickness being greater than a second thickness of the metal gate structure near the side ends of the metal gate structure disposed between the side ends of the adjacent semiconductor channel layers.

3. The semiconductor device as claimed in claim 1, characterized in that, When the metal gate profile has the concave shape, the metal gate structure has a first thickness near a central portion of the metal gate structure disposed between the central regions of the adjacent semiconductor channel layers, the first thickness being less than a second thickness of the metal gate structure near the side ends of the metal gate structure disposed between the side ends of the adjacent semiconductor channel layers.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The metal gate structure includes a gate dielectric layer, which comprises: A single interface layer; and A high dielectric constant dielectric layer is formed on the interface layer.

5. The semiconductor device as claimed in claim 4, characterized in that, The gate dielectric layer has a total thickness of 1 to 5 nanometers.

6. The semiconductor device as claimed in claim 4, characterized in that, The gate dielectric layer is disposed on the surface of the adjacent semiconductor channel layer and the substrate.

7. The semiconductor device as claimed in claim 4, characterized in that, The interface layer is disposed on the entire surface of the adjacent semiconductor channel layers between the internal spacers.

8. The semiconductor device as claimed in claim 7, characterized in that, The high dielectric constant dielectric layer is disposed on the substrate and on the interface layer disposed in the region of the adjacent semiconductor channel layer not covered by the substrate.

9. The semiconductor device as claimed in claim 4, characterized in that, The interface layer is disposed on the portion of the adjacent semiconductor channel layer that is not covered by the liner.

10. The semiconductor device as claimed in claim 4, characterized in that, The metal gate structure further includes a metal layer disposed on the gate dielectric layer.

Images