Semiconductor device

Abstract

A semiconductor device includes nanowire channels arranged in a direction perpendicular to a semiconductor substrate of the semiconductor device, gate structures surrounding the nanowire channels, source / drain regions adjacent to a side of the gate structures and abutting end points of the nanowire channels, internal spacers between the source / drain regions and the gate structures, and discontinuous epitaxial regions between the source / drain regions and at least one of the nanowire channels or the internal spacers.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] As semiconductor device manufacturing advances and technology node sizes shrink, transistors can become susceptible to short-channel effects (SCE), such as hot carrier degradation, barrier lowering, and quantum confinement. Furthermore, as transistor gate lengths decrease to achieve smaller technology nodes, source / drain (S / D) electron tunneling increases, thereby increasing the transistor's cutoff current (the current flowing through the transistor's channels when it is in off-configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors, such as nanowires, nanosheets, and gate-all-around (GAA) devices, are potential candidates for overcoming short-channel effects at smaller technology nodes. Nanostructure transistors are highly efficient structures that, compared to other types of transistors, can reduce SCE and enhance carrier mobility. Utility Model Content

[0003] Some embodiments of this disclosure provide a semiconductor device including nanostructure channels arranged in an orientation perpendicular to the semiconductor substrate, a gate structure surrounding the nanostructure channels, a source / drain region adjacent to one side of the gate structure and adjacent to the endpoint of the nanostructure channels, an internal spacer between the source / drain region and the gate structure, a discontinuous epitaxial region adjacent to the source / drain region, an epitaxial region in the discontinuous epitaxial region continuously spanning the internal spacer, a portion of the endpoint of a first nanostructure channel in the nanostructure channels, and a portion of the endpoint of the first nanostructure channel perpendicularly adjacent to the internal spacer.

[0004] Some embodiments of this disclosure provide a semiconductor device including a nanostructured channel, a gate structure, a source / drain region, internal spacers, and a discontinuous epitaxial region. The nanostructured channel is arranged in an orientation approximately perpendicular to the semiconductor substrate of the semiconductor device. The gate structure surrounds the nanostructured channel. The source / drain region is adjacent to one side of the gate structure and abuts the endpoint of the nanostructured channel. The internal spacers are located between the source / drain region and the gate structure. The discontinuous epitaxial region is located between the source / drain region and at least one of the following: the nanostructured channel or the internal spacers.

[0005] Some embodiments of this disclosure provide a semiconductor device including nanostructure channels arranged in an orientation, a semiconductor substrate with an orientation perpendicular to the semiconductor device, a gate structure surrounding the nanostructure channels, a source / drain region adjacent to one side of the gate structure and adjacent to the endpoint of the nanostructure channels, an internal spacer between the source / drain region and the gate structure, and a discontinuous epitaxial region between the source / drain region and the nanostructure channels and the internal spacer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the following detailed description will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1C This is a schematic diagram of an example implementation of the fin definition process described in this article;

[0008] Figure 2 This is a schematic diagram of the example dummy gate structure formation process described in this article;

[0009] Figure 3 This is a schematic diagram of an example implementation of the source / drain recess formation process described in this article;

[0010] Figures 4A to 4C This is a schematic diagram of an example implementation of the sacrificial dielectric layer formation process described herein;

[0011] Figure 5 This is a schematic diagram of an example implementation of the internal spacer formation process described herein;

[0012] Figure 6A and Figure 6B This is a schematic diagram of an example implementation of the source / drain region formation process described in this article;

[0013] Figure 7A and Figure 7B This is a schematic diagram of an example implementation of the interlayer dielectric formation process described herein;

[0014] Figures 8A to 8D This is a schematic diagram of an example implementation of the alternative gate process described herein;

[0015] Figures 9A to 9D This is a schematic diagram of an exemplary embodiment of the semiconductor device described herein;

[0016] Figures 10A to 10D This is a schematic diagram of an exemplary embodiment of the semiconductor device described herein;

[0017] Figures 11A to 11DThis is a schematic diagram of an exemplary embodiment of the semiconductor device described herein;

[0018] Figures 12A to 12C This is a schematic diagram of an exemplary embodiment of the semiconductor device described herein;

[0019] Figures 13A to 13C This is a schematic diagram of an exemplary embodiment of the semiconductor device described herein;

[0020] Figures 14A to 14F This is a schematic diagram of an exemplary embodiment of the semiconductor device described herein;

[0021] Figure 15 This is a schematic diagram of an example embodiment of the semiconductor device described herein;

[0022] Figure 16 This is a schematic diagram of an example embodiment of the semiconductor device described herein;

[0023] Figure 17 This is a flowchart of an example process for forming a semiconductor device as described in this article;

[0024] Figure 18 This is a flowchart of an example process for forming a semiconductor device as described in this article;

[0025] Figures 19A to 19F This is a schematic diagram of an exemplary embodiment of the semiconductor device 105 described herein;

[0026] Figures 20A to 20F This is a schematic diagram of an example embodiment of the semiconductor device 105 described herein.

[0027] [Symbol Explanation]

[0028] 100: Example Implementation

[0029] 105: Semiconductor Devices

[0030] 110: Semiconductor substrate

[0031] 115: Layer stacking

[0032] 120: Sacrificial Semiconductor Layer

[0033] 125: Semiconductor Channel Layer

[0034] 130: Hybrid Layer

[0035] 135: Hard Mask

[0036] 140: Overlay

[0037] 145: Oxide layer

[0038] 150: Nitride layer

[0039] 155: Fin Structure

[0040] 155a: Fin structure

[0041] 155b: Fin structure

[0042] 160: Part

[0043] 165: Fin section

[0044] 170: Lining

[0045] 175: STI region

[0046] 200: Example Implementation

[0047] 205: Dummy gate structure

[0048] 210: Gate electrode layer

[0049] 215: Covering layer

[0050] 215a: Covering layer

[0051] 215b: Covering layer

[0052] 220: Spacer layer

[0053] 220a: Spacer layer

[0054] 220b: Spacer layer

[0055] 225: Gate dielectric layer

[0056] 300: Example Implementation

[0057] 305: Source / Drain Recess

[0058] 310: Countertop area

[0059] 315: Nanostructured Channels

[0060] 400: Example Implementation

[0061] 405: Space

[0062] 410: Dielectric layer

[0063] 415: Sacrificial Dielectric Layer

[0064] 415a: Lining

[0065] 415b: Core

[0066] 420: Cavity

[0067] 500: Example Implementation

[0068] 505: Internal spacers

[0069] 600: Example Implementation

[0070] 605: Epitaxial region

[0071] 605a: Epitaxial region

[0072] 605b: Epitaxial region

[0073] 610: Source / Drain Region

[0074] 610a: p-type source / drain region

[0075] 610b: n-type source / drain region

[0076] 615: Overlapping area

[0077] 700: Example Implementation

[0078] 705: Dielectric layer

[0079] 710: Covering layer

[0080] 800: Example Implementation

[0081] 805: Space

[0082] 810: Gate dielectric layer

[0083] 815: Gate Structure

[0084] 815a: p-type gate structure

[0085] 815b: n-type gate structure

[0086] 900: Example Implementation

[0087] 1000: Example Implementation

[0088] 1100: Example Implementation

[0089] 1105: Isolation spacers

[0090] 1200: Example Implementation

[0091] 1300: Example Implementation

[0092] 1400: Example Implementation

[0093] 1500: Example Implementation

[0094] 1505: PMOS nanostructure transistor

[0095] 1510: NMOS nanostructure transistor

[0096] 1600: Example Implementation

[0097] 1605: Sidewall

[0098] 1610: Section

[0099] 1615: Section

[0100] 1700: Process

[0101] 1710: Square

[0102] 1720: Square

[0103] 1730: Square

[0104] 1740: Square

[0105] 1750: Square

[0106] 1800: Process

[0107] 1810: Square

[0108] 1820: Square

[0109] 1830: Square

[0110] 1840: Square

[0111] 1860: Square

[0112] 1900: Example Implementation

[0113] 2000: Example Implementation

[0114] AA: Cross-section

[0115] BB: Cross-section

[0116] CC: Cross section

[0117] D1: Dimensions

[0118] D2: Dimensions

[0119] x: direction

[0120] y: direction

[0121] z: Direction Detailed Implementation

[0122] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and is not, in itself, merely a relationship between the various embodiments and / or configurations discussed.

[0123] Furthermore, the spatially related terms used herein, such as “below,” “under,” “below,” “above,” and “on,” are for descriptive purposes to describe the relationship between one element or feature and another, as shown in the figures. These spatially related terms are intended to cover different orientations of the device during use or operation, in addition to those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0124] In some cases, nanochannels for nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors) can be formed by creating a layer stack (sometimes called a superlattice) comprising multiple alternating sacrificial layers and channel layers, and then etching the layer stack to define the nanostructured channels. The sacrificial layers are defined by the vertical spacing between the nanostructured channels and are subsequently removed and replaced with the gate structure of the nanostructured transistor. However, the inclusion of sacrificial layers can lead to the formation of various types of defects in the nanostructured transistor and / or may cause performance degradation.

[0125] For example, nanostructured transistors may include internal spacers between the source / drain regions and the gate structure, and the mixing of materials between the nanostructured channels and the sacrificial layer can lead to defects in the internal spacers, such as rounded corners. Rounded corners may occur when forming cavities for the internal spacers in a nanostructured transistor, and may also occur due to reduced etch selectivity between the nanostructured channels and the sacrificial layer caused by mixing. Internal spacers can provide various process and / or performance benefits, such as electrical insulation between the source / drain regions and the gate structure, and / or protection of the source / drain regions from etching during gate replacement operations to replace the sacrificial nanostructured layer with the gate structure. However, when performing gate replacement operations, rounded corners may cause the internal spacers to provide less etch buffering or etch stop, and etching may occur through the internal spacers and into the source / drain regions. Etching of the source / drain regions may damage the crystal structure of the source / drain regions and / or may cause electrical shorting between the source / drain regions and the gate structure. This could lead to the failure of nanostructured transistors and potentially reduce the yield of nanostructured transistors on semiconductor devices.

[0126] As another example, a sacrificial layer can support nanostructured channels during the formation of the source / drain regions. While the support provided by the sacrificial layer reduces the likelihood of bending and / or thinning of the nanostructured channel, which might otherwise occur due to stress applied to the channel during source / drain formation, the high stiffness of the sacrificial layer can effectively absorb most of the stress applied to the nanostructured channel, thus limiting the strain that may be induced within the channel. A quantitative amount of strain within the nanostructured channel can be beneficial because strain can alter the crystal structure of the channel, thereby achieving higher charged carrier mobilities. Therefore, the limited strain that the high stiffness of the sacrificial layer can induce in the nanostructured channel may limit the improvement in charged carrier mobility that can be induced during the formation of the source / drain regions.

[0127] In some embodiments described herein, a sacrificial semiconductor layer is removed from the layer stack of the semiconductor device before forming the internal spacers and source / drain regions of the nanostructured transistors of the semiconductor device. The sacrificial semiconductor layer may be removed along with a hybrid layer that may be formed due to the mixing of materials between the sacrificial semiconductor layer and the semiconductor channel layer, and the sacrificial semiconductor layer and the hybrid layer may be replaced by a sacrificial dielectric layer. The sacrificial dielectric layer may then be etched to form a cavity in which the internal spacers are formed.

[0128] Compared to the selectivity between the sacrificial semiconductor layer and the semiconductor channel layer, the sacrificial dielectric layer provides greater etch selectivity between them, enabling increased control over over-etching of the cavity. This increased etch control, along with the removal of the mixed layer, allows the cavity to form sharp corners, resulting in near-square or right-angled cavities. The sharpness of these cavity angles, along with the subsequent formation of internal spacers within the cavity, provides greater protection against etching of the source / drain regions, reducing the likelihood of source / drain region damage. Furthermore, highly doped epitaxial regions can be formed on the internal spacers before the source / drain regions are formed, further protecting them from etching.

[0129] Additionally and / or alternatively, the dielectric material of the sacrificial dielectric layer may have less elasticity than the material of the sacrificial semiconductor layer. The less elasticity of the sacrificial dielectric layer allows it to deform rather than absorb the stress applied to the nanostructure channels of the transistor structure during the formation of the source / drain regions. This allows the stress to induce strain in the nanostructure channels, thereby enhancing the charged carrier mobility.

[0130] Figures 1A to 1C This is a schematic diagram of an example embodiment 100 of the fin definition process described herein. Example embodiment 100 includes examples of forming a fin structure 155 for a semiconductor device 105 and relating to a shallow trench isolation (STI) region. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. Example embodiment 100 includes examples of forming a fin structure 155 for transistors in the semiconductor device 105 and relating to an STI region 175.

[0131] Figures 1A to 1C Each shows a perspective view of the semiconductor device 105 and a cross-sectional view along cross section AA in the perspective view. Figure 1AAs shown, the semiconductor device 105 is processed in conjunction with a semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0132] A layer stack 115 is formed over a semiconductor substrate 110. The layer stack 115 can be considered as a superlattice. The layer stack 115 includes alternating layers arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes vertically alternating layers of a sacrificial semiconductor layer 120 and a semiconductor channel layer 125 over the semiconductor substrate 110. Figure 1A The number of sacrificial semiconductor layers 120 and semiconductor channel layers 125 shown are examples, and other numbers of sacrificial semiconductor layers 120 and semiconductor channel layers 125 are within the scope of this disclosure.

[0133] The sacrificial semiconductor layer 120 and the semiconductor channel layer 125 can be "nanostructure" layers or "nanoscale" layers because they can each have a z-direction thickness on the order of nanometers. For example, they can each have a z-direction thickness of about 10 nanometers or less. However, other values ​​for the z-direction thickness of the sacrificial semiconductor layer 120 and the semiconductor channel layer 125 are within the scope of this disclosure.

[0134] The sacrificial semiconductor layer 120 allows for the definition of the vertical distance between adjacent nanostructure channels formed by the semiconductor channel layer 125, and the sacrificial semiconductor layer 120 serves as a placeholder layer for the subsequently formed gate structure of the transistor in the semiconductor device 105, the gate structure being formed around the nanostructure channel. The sacrificial semiconductor layer 120 comprises a first material composition, and the semiconductor channel layer 125 comprises a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the sacrificial semiconductor layer 120 may comprise silicon germanide (SiGe), and the semiconductor channel layer 125 may comprise silicon (Si). Depending on the type of etchant used, the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 may be selectively etched (e.g., the sacrificial semiconductor layer 120 but not the semiconductor channel layer 125 may be etched, or the semiconductor channel layer 125 but not the sacrificial semiconductor layer 120 may be etched).

[0135] One or more types of deposition tools can be used to deposit and / or grow alternating layers of the stack 115 to include nanostructures (e.g., nanosheets) above the semiconductor substrate 110. For example, the deposition tools can be used to grow the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 via epitaxial growth, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial techniques. Additionally and / or alternatively, the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition techniques.

[0136] For example, partial layer stacking 115 in Figure 1AAs shown in the close-up view, mixing may occur between two or more nanostructure layers in the layer stack 115. For example, mixing may occur between the sacrificial semiconductor layer 120 and the vertically adjacent semiconductor channel layer 125. Mixing may result in cross-diffusion of silicon (Si) and / or germanium (Ge) between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125. Therefore, a mixing layer 130 may be present between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125. The mixing layer 130 may include a region of silicon germanide (SiGe) with a higher silicon (Si) concentration than the germanium (Ge) concentration in the mixing layer 130 (e.g., due to silicon diffusion from the semiconductor channel layer 125 to the sacrificial semiconductor layer 120). Cross-diffusion of silicon (Si) and / or germanium (Ge) between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125 may occur due to the high-temperature process used to form the layer stack 115. The sacrificial semiconductor layer 120 and semiconductor channel layer 125 of the layer stack 115 can be formed by epitaxial growth, and in some embodiments, the process temperature can exceed 1000 degrees Celsius. Higher temperatures may result in increased crystalline quality. However, low-temperature processes are within the scope of this disclosure. During the formation of the layer stack 115, high process temperatures can cause the material in the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 to migrate and mix between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125, resulting in the formation of a mixed layer 130.

[0137] One or more mask layers may be formed (e.g., using one or more deposition tools) over the layer stack 115. The mask layers may include a hard mask (HM) layer 135, a capping layer 140, an oxide layer 145, and / or a nitride layer 150. The mask layers may be used to perform fin patterning operations to form a fin structure 155 in the semiconductor substrate 110.

[0138] like Figure 1BAs shown, layer stack 115 and semiconductor substrate 110 are etched to remove portions of layer stack 115 and semiconductor substrate 110. This results in the formation of a fin structure 155 extending over semiconductor substrate 110. Fin structure 155 may extend along the x-direction in semiconductor device 105 and may be aligned along the y-direction in semiconductor device 105. Fin structure 155 includes a portion 160 of layer stack 115 above and / or on a fin portion 165 above semiconductor substrate 110. Fin structure 155 may be formed by patterning one or more masking layers and etching semiconductor substrate 110 based on the pattern formed in one or more masking layers. One or more masking layers may be patterned using photolithography techniques, including dual patterning or multi-patterning techniques. Etching tools may be used based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or a combination of the above.

[0139] like Figure 1B As further shown, for different types of nanostructure transistors, some fin structures 155 can be formed with different widths. For example, a first subset of fin structures 155a can be formed for p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset of fin structures 155b can be formed for n-type nanostructure transistors (e.g., n-type metal oxide semiconductor (NMOS) nanostructure transistors). As another example, a first subset of fin structures 155a can be formed for nanostructure transistors configured to operate at lower volts, and a second subset of fin structures 155b can be formed for nanostructure transistors configured to operate at higher volts.

[0140] like Figure 1C As shown, the liner 170 and the STI region 175 are formed between adjacent fin portions 165 of the fin structure 155. The liner 170 and the STI region 175 may each comprise a dielectric material, such as silicon oxide (SiO2). x Silicon nitride (Si) x N ySilicon oxynitride (SiON), fluoride-doped silicate glass (FSG), undoped silicate glass (USG), low-k dielectric materials (e.g., dielectric materials with a dielectric constant of about 3.9 or less), and / or other suitable insulating materials.

[0141] A deposition tool can be used to conformally deposit the substrate 170 (e.g., using ALD or other conformal deposition techniques) and to deposit a dielectric layer over the substrate 170 (e.g., using CVD, PVD, ALD, and other suitable deposition techniques) such that the dielectric layer completely fills the space between the fin structures 155 and extends above the top of the fin structures 155. A planarization tool can then be used to perform a planarization or polishing operation (e.g., chemical mechanical planarization (CMP)) to planarize the dielectric layer such that the top surface of the dielectric layer and the top of the nitride layer 150 are approximately coplanar. The nitride layer 150 serves as a CMP stop layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form the STI region 175 such that the top surface of the STI region 175 and the bottommost sacrificial semiconductor layer 120 are approximately coplanar, or the top surface of the STI region 175 is below the bottommost sacrificial semiconductor layer 120.

[0142] In some embodiments, a hard mask layer (not shown) may be formed over the STI region 175 between the fin structures 155 to protect the STI region 175 in subsequent processes. The hard mask layer may include a nitride, such as silicon nitride (Si). x N y Silicon oxynitride, silicon carbide, silicon carbonitride (SiCN), and / or silicon oxycarbonitride (SiOCN), etc. The hard masking layer can be deposited using appropriate processes such as CVD, plasma-enhanced CVD (PECVD), ALD, etc. The material of the masking layer deposited above the sidewalls of the fin structure 155 can be removed by any suitable etching process, such as dry etching or wet etching.

[0143] As shown above, Figures 1A to 1C One example is provided. Other examples are available. Figures 1A to 1C The differences mentioned above.

[0144] Figure 2This is a schematic diagram of an example embodiment 200 of the dummy gate formation process described herein. Example embodiment 200 includes an example of forming a dummy gate structure 205 for a nanostructured transistor in a semiconductor device 105. In some embodiments, in conjunction with... Figures 1A to 1C After the process, the operation described in conjunction with Example Implementation 200 is performed.

[0145] Figure 2 A perspective view showing a dummy gate structure 205 formed on semiconductor device 105 is shown. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed over a portion of fin structure 155 and a portion of STI region 175. The dummy gate structure 205 extends in the y-direction and is aligned in the x-direction such that the dummy gate structure 205 is approximately perpendicular to fin structure 155. The dummy gate structure 205 is a sacrificial structure, which is replaced by a replacement gate structure or replacement gate stack in a subsequent process stage of semiconductor device 105. The dummy gate structure 205 can also be used to define source / drain (S / D) recesses, the source / drain regions of nanostructured transistors formed in fin structure 155.

[0146] The dummy gate structure 205 may include a gate electrode layer 210, a capping layer 215 above and / or on the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 below the gate electrode layer 210. The gate electrode layer 210 includes polycrystalline silicon (polysilicon, or PO) or other materials. The capping layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or other materials) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer that may include silicon nitride such as Si3N4 or other materials). The spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiO2 such as SiO2). x ), silicon nitride (e.g., Si3N4, etc.) x N y ), high dielectric constant (high k) dielectric materials (e.g., dielectric materials with a dielectric constant greater than about 3.9) and / or other suitable materials.

[0147] The dummy gate structure 205 can be formed using a variety of semiconductor process technologies, such as depositing the dummy gate structure 205, patterning the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor process technologies.

[0148] Figure 2 Further, reference cross sections used in the following figures described herein are shown. Cross section AA crosses the fin structure 155 in the source / drain region of semiconductor device 105 in the yz plane (considered an x-cut). Cross section BB crosses the xz plane (considered a y-cut), which is perpendicular to cross section AA, and crosses the dummy gate structure 205 and the fin structure 155 below. Cross section CC crosses the xz plane, which is parallel to cross section AA and perpendicular to cross section BB, and along the dummy gate structure 205. For clarity, the following figures refer to these reference cross sections. In some figures, some reference numerals for elements or features shown may be omitted to avoid obscuring other elements or features in order to depict the figures.

[0149] As shown above, Figure 2 One example is provided. Other examples are available. Figure 2 The differences mentioned.

[0150] Figure 3 This is a schematic diagram of an example embodiment 300 of the source / drain recess formation process described herein. Example embodiment 300 includes an example of a source / drain recess 305 forming a source / drain region for a nanostructure transistor in a semiconductor device 105. Figure 3 From Figure 2 The perspective view shown includes Figure 2 Perspective view of cross section BB and Figure 2 A perspective view of the cross section CC. In some embodiments, in combination Figures 1A to 2 After the process, the operation described in conjunction with Example Implementation 300 is performed.

[0151] like Figure 3 As shown in cross-sections BB and CC, the capping layer 215 of the dummy gate structure 205 may include a multilayer stack. The multilayer stack may include a capping layer 215a on the gate electrode layer 210 and a capping layer 215b on the capping layer 215a. The capping layers 215a and 215b may include different materials to provide etch selectivity and / or enable multiple planarization operations while protecting the gate electrode layer 210 from removal. In some embodiments, the capping layer 215a includes a nitrogen-containing material such as silicon nitride (e.g., Si3N4). x N y The capping layer 215b includes an oxygen-containing material such as silicon oxide (e.g., SiO2). x However, other combinations of materials used for cover layers 215a and 215b are within the scope of this disclosure.

[0152] like Figure 3 As further shown in cross-sections BB and CC, spacer layer 220 may be located on the sidewalls of dummy gate structure 205. Spacer layer 220 includes spacer layer 220a on the sidewalls of dummy gate structure 205 and spacer layer 220b above spacer layer 220a. Spacer layers 220a and 220b may include different materials to provide etch selectivity to protect dummy gate structure 205 from etching during the formation of source / drain recess 305. In some embodiments, spacer layer 220a includes a low dielectric constant dielectric material, such as silicon oxide (e.g., SiO2). x The spacer layer 220b comprises a high dielectric constant dielectric material, such as silicon nitride (e.g., Si3N4). x N y However, other combinations of materials used for spacer layers 220a and 220b are within the scope of this disclosure.

[0153] like Figure 3 As further shown in the cross-section BB, a source / drain recess 305 is formed through a portion 160 of the fin structure 155 during the etching operation. The source / drain recess 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes using plasma etching technology, wet chemical etching technology, and / or other types of etching technology.

[0154] In some embodiments, the source / drain recess 305 also extends to a portion of the fin portion 165 of the fin structure 155. Specifically, the source / drain recess 305 may extend to the mesa region 310 in the fin structure 155. The sidewall of each portion of the source / drain recess 305 beneath the layer stack 115 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as a pedestal or fin pedestal) refers to the region of the fin portion 165 of the fin structure 155 that extends above the top surface of the STI region 175.

[0155] Or, combine Figures 9A to 9DThe source / drain recess 305 can be formed such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) to the mesa region 310 below the bottommost sacrificial semiconductor layer 120. In these embodiments, the bottom of the source / drain recess 305 may be approximately coplanar with the bottommost sacrificial semiconductor layer 120, or may be located at a higher vertical (z-direction) height in the semiconductor device 105 than the bottom surface of the bottommost sacrificial semiconductor layer 120. This can reduce the amount and / or likelihood of current leakage from the source / drain region to be formed in the source / drain recess 305, which would otherwise potentially occur through the mesa region 310.

[0156] The formation of source / drain recesses 305 defines nanostructured channels 315 (e.g., nanostructured channels 315 of nanostructured transistor structures) in semiconductor device 105. Nanostructured channels 315 extend between adjacent source / drain recesses 305 and are located below dummy gate structures 205 between adjacent source / drain recesses 305. Nanostructured channels 315 include silicon-based nanostructures (e.g., nanosheets or nanowires) as semiconductor channels for nanostructured transistors in semiconductor device 105. In some embodiments, nanostructured channels 315 may include silicon (Si), doped silicon, silicon-germanium (SiGe), and / or other silicon-based materials. Nanostructured channels 315 are arranged in a direction approximately perpendicular to semiconductor substrate 110 (e.g., the z-direction). In other words, nanostructured channels 315 are vertically arranged or stacked above semiconductor substrate 110.

[0157] like Figure 3 As further shown in the cross-section BB, the endpoints of the sacrificial semiconductor layer 120, the endpoints of the hybrid layer 130, and the endpoints of the nanostructure channel 315 are exposed in the source / drain recess 305.

[0158] As shown above, Figure 3 One example is provided. Other examples are available. Figure 3 The differences mentioned.

[0159] Figures 4A to 4C This is a schematic diagram of an example embodiment 400 of the sacrificial dielectric layer formation process described herein. Example embodiment 400 includes an example in which a sacrificial semiconductor layer 120 is replaced with a sacrificial dielectric layer 415. Figures 4A to 4C Each from Figure 2 The perspective views of cross sections BB and CC are shown. In some embodiments, in combination Figures 1A to 3 After the process, the operation described in conjunction with Example Implementation 400 is performed.

[0160] like Figure 4AAs shown in cross-sections BB and CC, the retained portion of the sacrificial semiconductor layer 120 can be removed between the nanostructure channels 315. In some embodiments, the retained portion of the sacrificial semiconductor layer 120 is etched and removed via the source / drain recess 305. Figure 4A As further shown, during the removal of the retained portion of the sacrificial semiconductor layer 120, the mixed layer 130 can also be removed from the semiconductor device 105. Because the mixed layer 130 includes material also contained in the retained portion of the sacrificial semiconductor layer 120 (e.g., a portion of silicon-germanium (SiGe)), the etchant used to etch the sacrificial semiconductor layer 120 also etches the mixed layer 130. During the removal of the retained portion of the sacrificial semiconductor layer 120, some etching of the nanostructure channels 315 may also occur. The removal of the retained portion of the sacrificial semiconductor layer 120 creates a space 405 between vertically adjacent nanostructure channels 315, which was previously occupied by the retained portion of the sacrificial semiconductor layer 120.

[0161] In some embodiments, the etchant may include a gas-based etchant, including combinations of fluorine-based etchants (e.g., F2 gas) and hydrofluoric acid etchants (e.g., HF gas). Other gases, such as purge gases, carrier gases, and / or other reactant gases, may also be supplied to the process chamber during the etching operation. These gases may include argon (Ar), ammonia (NH3), chlorine trifluoride (ClF3), and / or nitrogen (N2), etc. The etchant can be used to etch the sacrificial semiconductor layer 120 and the mixed layer 130 by removing silicon (Si) and germanium (Ge) from the sacrificial semiconductor layer 120 and the mixed layer 130. The removal of silicon (Si) from the sacrificial semiconductor layer 120 and the mixed layer 130 can be caused by a reaction between a fluorine-based etchant (e.g., F2 gas) in the etchant and silicon-germanium (SiGe) in the sacrificial semiconductor layer 120 and the mixed layer 130.

[0162] SiGe+F2→GeF3+SiF3→GeF2+SiF4

[0163] A fluorine-based etchant (e.g., F2 gas) in the etchant can attach to the silicon (Si) and germanium (Ge) in the sacrificial semiconductor layer 120 and the mixed layer 130 to form germanium trifluoride (GeF3) and silicon trifluoride (SiF3), respectively. Fluorine migration may occur when fluorine (F) atoms migrate from germanium trifluoride molecules to silicon trifluoride molecules, resulting in the formation of germanium difluoride (GeF2) and silicon tetrafluoride (SiF4) gases. The removal of silicon tetrafluoride from the semiconductor device 105 causes the removal of silicon (Si) from the sacrificial semiconductor layer 120 and the mixed layer 130.

[0164] Removal of germanium (Ge) from the sacrificial semiconductor layer 120 and the mixed layer 130 can be caused by a combination of fluorine-based etchants (e.g., F2 gas) and hydrofluoric acid etchants (e.g., HF gas) in the etchant and a reaction between silicon-germanium (SiGe) in the sacrificial semiconductor layer 120 and the mixed layer 130.

[0165] SiGe+F2+HF→GeH2F+SiHF2→GeH3F+SiF2

[0166] Fluorine (F) in fluorine-based etchants (e.g., F2 gas) and / or hydrofluoric acid etchants (e.g., HF gas) can attach to silicon (Si) and germanium (Ge) in the sacrificial semiconductor layer 120 and the mixed layer 130. Furthermore, hydrogen in the hydrofluoric acid etchant can attach to silicon (Si) and germanium (Ge) in the sacrificial semiconductor layer 120 and the mixed layer 130. Fluorine and hydrogen react with germanium to form GeH2F and SiHF2. Hydrogen migration may occur when hydrogen (H) atoms migrate from SiHF2 molecules to GeH2F molecules, resulting in the formation of GeH3F gas and silicon difluoride (SiF2). GeH3F gas is removed from the semiconductor device 105, causing germanium (Ge) to be removed from the sacrificial semiconductor layer 120 and the mixed layer 130.

[0167] like Figure 4B and Figure 4CAs shown in cross sections BB and CC, the sacrificial semiconductor layer 120 and the hybrid layer 130 are removed and replaced with a sacrificial dielectric layer 415. The sacrificial semiconductor layer 120 and the hybrid layer 130 can be replaced by the sacrificial dielectric layer 415 to achieve precise control over the size and shape of the cavity 420 in which the internal spacers of the semiconductor device 105 are formed. In particular, the etch selectivity between the dielectric material of the sacrificial dielectric layer 415 and the semiconductor material (e.g., silicon (Si)) of the nanostructure channel 315 can be greater than the etch selectivity between the semiconductor material of the sacrificial semiconductor layer 120 (e.g., silicon-germanium (SiGe)) and the semiconductor material (e.g., silicon (Si)) of the nanostructure channel 315. This greater etch selectivity allows the cavity 420 to be formed with sharper angles compared to retaining the sacrificial semiconductor layer 120 and the hybrid layer 130. The sharper angles of cavity 420 promote the formation of internal spacers with sharper angles (instead of rounded corners for the internal spacers if the sacrificial semiconductor layer 120 and hybrid layer 130 were retained). This reduces the risk of etching through the nanostructure channel 315 at the corners of the internal spacers during the alternative gate process of replacing the dummy gate structure 205 with a high-dielectric-constant / metal gate structure. Therefore, replacing the sacrificial semiconductor layer 120 and hybrid layer 130 with the sacrificial dielectric layer 415 reduces the risk of etch damage to the source / drain regions formed in the source / drain recess 305.

[0168] Instead of forming the layer stack 115 with a sacrificial dielectric layer 415 instead of a sacrificial semiconductor layer 120, the sacrificial semiconductor layer 120 and the hybrid layer 130 can be removed and replaced with a sacrificial dielectric layer 415 to achieve higher process efficiency and higher quality nanostructured channels 315. Since the semiconductor channel layer 125 (formed by the nanostructured channels 315) is epitaxially grown, the sacrificial semiconductor layer 120 provides a semiconductor substrate with a lattice structure on which the semiconductor channel layer 125 can be grown. The sacrificial semiconductor layer 120 and the semiconductor channel layer 125 can have similar lattice constants, which provides high-quality epitaxial growth of the semiconductor channel layer 125. If the semiconductor channel layer 125 is grown on the sacrificial dielectric layer 415, a lattice mismatch between the sacrificial dielectric layer 415 and the semiconductor channel layer 125 may lead to cracking and other defects in the semiconductor channel layer 125. Furthermore, the time, complexity, and / or cost of forming the source / drain recess 305 may be greater because additional steps and etchants may be required in separate steps to etch the semiconductor material of the semiconductor channel layer 125 and the dielectric material of the sacrificial dielectric layer 415 (while the semiconductor channel layer 125 and the sacrificial semiconductor layer 120 can be etched in the same etching step using the same etchant to form the source / drain recess 305).

[0169] like Figure 4B As shown in cross-sections BB and CC, dielectric layer 410 can be deposited along the bottom and sidewalls of source / drain recess 305. Dielectric layer 410 can be further deposited vertically in spaces (or regions) 405 between nanostructure channels 315, spaces 405 previously occupied by sacrificial semiconductor layer 120. In some embodiments, deposition tools are used to deposit dielectric layer 410 using CVD, PVD, ALD, and / or other deposition techniques. In some embodiments, deposition tools are used to deposit material of dielectric layer 410 using flowable deposition techniques. For example, material of dielectric layer 410 can be dispensed into source / drain recess 305 such that material can flow into spaces 405 between vertically adjacent nanostructure channels 315, and a curing process can be used to cure the material to form dielectric layer 410.

[0170] like Figure 4C As shown in cross-sections BB and CC, excess material of the dielectric layer 410 on the sidewalls and bottom surface of the source / drain recess 305 is removed, leaving the dielectric layer 410 in the space 405 between vertically adjacent nanostructure channels 315 as a sacrificial dielectric layer 415. Etching tools can be used to trim the dielectric layer 410 using wet etching, dry etching, and / or other suitable etching techniques.

[0171] The sacrificial dielectric layer 415 can be a "nanostructure" layer or a "nanoscale" layer, because each sacrificial dielectric layer 415 can have a z-direction thickness on the order of nanometers. For example, each sacrificial dielectric layer 415 can have a z-direction thickness of about 10 nanometers or less. However, other values ​​for the z-direction thickness of the sacrificial dielectric layer 415 are within the scope of this disclosure.

[0172] Flow deposition techniques (and / or other low-density deposition techniques) used to deposit dielectric layer 410 can result in a low material density for sacrificial dielectric layer 415, which in turn results in relatively low stiffness. For example, sacrificial dielectric layer 415 may comprise low-density silicon oxide with a Young's modulus less than that of the semiconductor material of sacrificial semiconductor layer 120 and less than that of the semiconductor material of nanostructure channel 315. Therefore, the elasticity (e.g., elastic modulus) of sacrificial dielectric layer 415 is less than that of sacrificial semiconductor layer 120 and less than that of nanostructure channel 315. Consequently, compared to sacrificial semiconductor layer 120, sacrificial dielectric layer 415 absorbs a small amount of tensile and compressive stress applied to nanostructure channel 315. Therefore, the sacrificial dielectric layer 415 can support the nanostructure channel 315 during subsequent stress-inducing processes (e.g., source / drain formation) to prevent or reduce the risk of permanent deformation (e.g., bending, thinning) of the nanostructure channel 315, while still enabling the lattice of the nanostructure channel 315 to be strained to increase carrier mobility in the nanostructure channel 315.

[0173] In some embodiments, the Young's modulus of the material of the sacrificial dielectric layer 415 is in the range of about 43 to about 92. In some embodiments, the Young's modulus of the material of the sacrificial semiconductor layer 120 is in the range of about 100 to about 190. In some embodiments, the Young's modulus of the material of the nanostructure channel 315 is in the range of about 130 to about 188. However, other values ​​and ranges of the Young's modulus of the materials of the sacrificial dielectric layer 415, the sacrificial semiconductor layer 120, and the nanostructure channel 315 are within the scope of this disclosure.

[0174] like Figure 4C As further shown in the cross-section BB, in one or more first etch operations, the endpoints of the sacrificial dielectric layer 415 exposed in the source / drain recess 305 are etched laterally (e.g., in the x-direction approximately parallel to the length of the sacrificial semiconductor layer 120), thus forming a cavity 420 between the endpoints of the nanostructured channels 315 exposed in the source / drain recess 305. Specifically, the etch tool can be used to laterally etch the endpoints of the sacrificial dielectric layer 415 beneath the dummy gate structure 205 through the source / drain recess 305 to form the cavity 420 between the endpoints of the nanostructured channels 315.

[0175] like Figure 4CAs shown in the close-up view, cavity 420 can have sharp inner corners, and the sidewalls and inner surface of cavity 420 are approximately orthogonal. As shown above, the etch selectivity between the dielectric material of the sacrificial dielectric layer 415 and the semiconductor material of the nanostructure channel 315, combined with the removal of the mixed layer 130, enables the formation of sharp inner corners in cavity 420. In some embodiments, the angle of the inner corner of cavity 420 (in...) Figure 4C (As shown in dimension D1) can be greater than 80 degrees and can be in the range of about 85 degrees to about 90 degrees. However, other interior angles are within the scope of this disclosure.

[0176] As shown above, Figures 4A to 4C One example is provided. Other examples are available. Figures 4A to 4C The differences mentioned.

[0177] Figure 5 This is a schematic diagram of an example embodiment 500 of the internal spacer formation process described herein. Example embodiment 500 includes an example of forming an internal spacer 505 between the endpoints of a nanostructured channel 315 exposed in a source / drain recess 305. Figure 5 From Figure 2 A perspective view of the cross-section BB is shown. In some embodiments, in combination Figures 1A to 4C After the process, the operation described in conjunction with Example Implementation 500 is performed.

[0178] like Figure 5 As shown, an internal spacer 505 is formed in the cavity 420 between the endpoints of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The internal spacer 505 reduces parasitic capacitance in the nanostructure transistor and protects the source / drain regions (subsequently formed in the source / drain recess 305) from being etched during nanosheet release operations to remove the sacrificial dielectric layer 415 between the nanostructure channels 315. The internal spacer 505 comprises silicon nitride (Si). x N y ), silicon dioxide (SiO) x ), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN) and / or other dielectric materials.

[0179] To form the internal spacers 505, deposition tools can be used to deposit a layer of dielectric material in the cavity 420 and along the sidewalls and bottom surface of the source / drain recess 305. CVD, PVD, ALD, and / or other deposition techniques can be used to deposit the dielectric material layer. Etching tools are used to subsequently remove excess material from the dielectric material layer in the source / drain recess 305, leaving a portion corresponding to the internal spacers 505 in the cavity 420.

[0180] like Figure 5 As shown in the close-up view, the internal spacer 505 may have a sharp inner angle, approximately orthogonal between the sidewalls and inner surface of the internal spacer 505. The sharp inner angle can be achieved as a result of the techniques described above for replacing the sacrificial semiconductor layer 120 and the hybrid layer 130, forming a cavity 420 in the sacrificial dielectric layer 415. In some embodiments, the angle of the inner angle of the internal spacer 505 (in...) Figure 5 (As shown in dimension D2) can be greater than 80 degrees and can be in the range of about 85 degrees to about 90 degrees. However, other interior angles are within the scope of this disclosure.

[0181] As shown above, Figure 5 One example is provided. Other examples are available. Figure 5 The differences mentioned.

[0182] Figure 6A and Figure 6B This is a schematic diagram of an example embodiment 600 of the source / drain region formation process described herein. Example embodiment 600 includes an example of forming the source / drain region 610 of a nanostructure transistor of semiconductor device 105. Figure 6A and Figure 6B From Figure 2 Multiple perspective views are displayed, including Figure 2 Perspective view of cross section AA and Figure 2 A perspective view of the cross-section BB in the figure. In some embodiments, in combination Figures 1A to 5 After the process, the operation described in conjunction with Example Implementation 600 is performed.

[0183] like Figure 6A As shown in the cross-section BB, a non-contiguous epitaxial region 605 is formed above the sidewalls in the source / drain recess 305. The epitaxial region 605 is non-contiguous because it consists of discrete regions of material that do not contact each other. However, in some embodiments, two or more epitaxial regions 605 may be in physical contact.

[0184] exist Figure 6AIn the example shown in the close-up view, a discontinuous epitaxial region 605 is formed on the endpoint of the internal spacer 505 exposed in the source / drain recess 305. The epitaxial region 605 may continuously span the endpoint of the internal spacer 505 and a portion of the endpoint of the nanostructure channel 315 on the vertically opposite side of the internal spacer 505. Therefore, an overlap region 615 occurs where the epitaxial region 605 partially overlaps with a portion of the endpoint of the nanostructure channel 315 on the vertically opposite side of the internal spacer 505. The epitaxial region 605 in the overlap region 615 protects the interface between the internal spacer 505 and the nanostructure channel 315 from being etched during the alternative gate process of the semiconductor device 105 (which would otherwise lead to the etching of the source / drain region 610 formed in the source / drain recess 305).

[0185] exist Figure 6A The location of the discontinuous epitaxial region 605 shown is an example; other locations of the discontinuous epitaxial region 605 are within the scope of this disclosure. Figures 12A to 12C and Figures 13A to 13C Other examples showing the location of the discontinuous epitaxial region 605.

[0186] In order for the discontinuous epitaxial region 605 to withstand etching during the replacement gate process of the semiconductor device 105, the discontinuous epitaxial region 605 may include a semiconductor material (e.g., silicon (Si)) with a higher doping concentration than that in the source / drain region 610.

[0187] For the p-type source / drain regions, the discontinuous epitaxial region 605 can be doped with p-type dopants such as boron (B) and / or gallium (Ga). P-type doping increases the energy required to remove electrons from the discontinuous epitaxial region 605 (e.g., from about 3.55 electron-volts to about 4.1 electron-volts), thus requiring significantly more energy to remove material from the discontinuous epitaxial region 605 compared to the source / drain region 610. The p-type doping concentration in the discontinuous epitaxial region 605 can be approximately 1 × 10⁻⁶ per cubic centimeter. 19 Atoms per cubic centimeter to approximately 1 × 103 22 Within the atomic range, sufficient etch resistance to halogen-based etchants is provided. However, other values ​​and ranges of p-type doping concentration in the discontinuous epitaxial region 605 are within the scope of this disclosure. Increasing the concentration of p-type doping can increase the etch resistance of the discontinuous epitaxial region 605.

[0188] For the n-type source / drain regions, the discontinuous epitaxial region 605 can be doped with carbon (C) and / or other suitable dopants. Carbon doping increases the etch resistance of the discontinuous epitaxial region 605 without negatively affecting the n-type doping in the n-type source / drain regions. The carbon doping concentration in the discontinuous epitaxial region 605 can be approximately 1 × 10⁻⁶ per cubic centimeter. 19 Atoms per cubic centimeter to approximately 1 × 103 22 Within the atomic range, sufficient etch resistance to halogen-based etchants is provided. However, other values ​​and ranges for the carbon doping concentration in the discontinuous epitaxial region 605 are within the scope of this disclosure.

[0189] In some embodiments, the discontinuous epitaxial region 605 may be doped with multiple dopants, including carbon doping and n-type doping such as arsenic (As) and / or phosphorus (P). In some embodiments, the concentration of carbon doping may be increased and / or the concentration of n-type doping may be decreased to increase the etch resistance of the discontinuous epitaxial region 605.

[0190] like Figure 6B As shown in cross sections AA and BB, additional epitaxial material is deposited over the discontinuous epitaxial region 605 in the source / drain recess 305 to form a source / drain region 610 in the source / drain recess 305. The term "source / drain region" may be used alone or collectively as source region and / or drain region, depending on the context. The source / drain region 610 may be on the opposite side of the dummy gate structure 205, such that a nanostructure channel 315 below the dummy gate structure 205 extends between and electrically couples the source / drain regions 610.

[0191] The source / drain regions 610 may each comprise epitaxially grown silicon (Si) and / or other epitaxial growth materials. In some embodiments, the source / drain regions 610 comprise silicon doped with one or more doped materials, such as p-type materials (e.g., boron (B) or germanium (Ge), other examples), n-type materials (e.g., phosphorus (P) or arsenic (As), other examples), and / or other types of doping. In these embodiments, the semiconductor device 105 may include a PMOS nanostructure transistor having p-type source / drain regions, an NMOS nanostructure transistor having n-type source / drain regions, and / or other types of nanostructure transistors.

[0192] The epitaxial technique used to form the source / drain region 610 can induce lateral stress in the nanostructure channel 315. For example, epitaxial growth (and associated high process temperatures) can cause tensile and / or compressive stresses in the nanostructure channel 315. The sacrificial dielectric layer 415 supports the nanostructure channel 315 during the epitaxial growth of the source / drain region 610 (preventing or reducing the possibility of bending and / or thinning of the nanostructure channel 315) while allowing lateral stress to still induce stress in the nanostructure channel 315. Strain in the nanostructure channel 315 increases the charged carrier mobility in the nanostructure channel 315.

[0193] like Figure 6B As shown, in some embodiments, the epitaxial material of the source / drain region 610 fills the source / drain recess 305. In some embodiments, an isolation layer is formed at the bottom of the source / drain recess 305, and the epitaxial material of the source / drain region 610 is formed above the isolation layer. In some embodiments, the bottom surface of the source / drain region 610 may be approximately perpendicularly aligned with the bottom surface of the lowest layer of the internal spacer 505.

[0194] As shown above, Figure 6A and Figure 6B One example is provided. Other examples are available. Figure 6A and Figure 6B The differences mentioned.

[0195] Figure 7A and Figure 7B This is a schematic diagram of an example embodiment 700 of the interlayer dielectric (ILD) formation process described herein. Figure 7A and Figure 7B From Figure 2 Multiple perspective views are displayed, including Figure 2 Perspective view of cross section BB and Figure 2 A perspective view of the cross-section CC in the figure. In some embodiments, in combination Figures 1A to 6B After the process, the operation described in conjunction with Example Implementation 700 is performed.

[0196] like Figure 7A As shown in the cross-section BB, a dielectric layer 705 is formed over the source / drain region 610. The dielectric layer 705 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 705 may be formed during a gate replacement process to replace the dummy gate structure 205 to reduce the likelihood of damage to the source / drain region 610 and / or prevent damage to the source / drain region 610. The dielectric layer 705 may be referred to as an ILD zero (ILD 0) layer or other ILD layers. The dielectric layer 705 may include silicon oxide (SiO2).x USG, FSG, and / or other suitable low dielectric constant materials. Deposition tools can be used to deposit dielectric layer 705 using PVD, ALD, CVD, and / or other suitable deposition techniques. In some embodiments, a contact etch stop layer (CESL) (not shown) is conformally deposited (e.g., via a deposition tool) over the source / drain regions 610 prior to the formation of dielectric layer 705.

[0197] like Figure 7B As shown in cross-sections BB and CC, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. The planarization operation can cause the capping layers 215a and 215b to be removed from the dummy gate structure 205, exposing the top of the gate electrode layer 210 of the dummy gate structure 205.

[0198] like Figure 7B As further shown, during subsequent operations such as a gate replacement process, a capping layer 710 can be formed over the dielectric layer 705 to protect the dielectric layer 705. The capping layer 710 may include silicon nitride (Si). x N y Examples include silicon carbonitride (SiCN), silicon oxynitride (SiON), or combinations thereof.

[0199] As shown above, Figure 7A and Figure 7B One example is provided. Other examples are available. Figure 7A and Figure 7B The differences mentioned.

[0200] Figures 8A to 8D This is a schematic diagram of an example embodiment 800 of the alternative gate process described herein. For the nanostructure transistor of the semiconductor device 105, the alternative gate process is a process of removing the remaining portions of the dummy gate structure 205 and the sacrificial dielectric layer 415 from the semiconductor device 105 and replacing them with a high dielectric constant / metal gate structure (e.g., an alternative gate structure). Figures 8A to 8D Each from Figure 2 Perspective view of cross section BB and Figure 2 A perspective view of the cross-section CC is shown. In some embodiments, in combination Figures 1A to 7B After the process, the operation described in conjunction with Example Implementation 800 is performed.

[0201] like Figure 8AAs shown in cross-sections BB and CC, a dummy gate removal operation can be performed. The dummy gate removal operation includes removing a dummy gate structure 205 (e.g., the gate electrode layer 210 of the dummy gate structure 205) from the semiconductor device 105. Removal of the dummy gate structure 205 leaves an opening (or recess) between the capping layers 710. The dummy gate structure 205 can be removed in one or more etching operations. This etching operation can include plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques.

[0202] like Figure 8B As shown in cross-sections BB and CC, the gate dielectric layer 225 can be removed from the semiconductor device 105. The removal of the dummy gate structure 205 and the gate dielectric layer 225 provides access to the underlying sacrificial dielectric layer 415 in a subsequent nanosheet removal process. The gate dielectric layer 225 can be removed in one or more etching operations. This etching operation can include plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques.

[0203] like Figure 8C As shown in cross sections BB and CC, the nanosheet release operation may include performing an etching operation to laterally etch the sacrificial dielectric layer 415 to remove the sacrificial dielectric layer 415 from between vertically adjacent nanostructure channels 315. The removal of the sacrificial dielectric layer 415 leaves a space 805 between the vertically adjacent nanostructure channels 315.

[0204] exist Figure 8C As shown in the close-up view, the epitaxial region 605 in the overlap region 615 protects the interface between the internal spacer 505 and the nanostructure channel 315 from etching during the nanosheet release process. Additionally and / or alternatively, the sharp inner corners of the internal spacer 505 (achieved at least in part by replacing the sacrificial semiconductor layer 120 and the hybrid layer 130 with a sacrificial dielectric layer 415) prevent and / or reduce the likelihood of etching at the interface between the internal spacer 505 and the nanostructure channel 315 during the nanosheet release process. Therefore, the sharp inner corners of the internal spacer 505 and / or the etch resistance of the epitaxial region 605 prevent and / or reduce the likelihood of etching into (e.g., damaging) the source / drain region 610 during nanosheet release operations that replace the gate process.

[0205] like Figure 8DAs shown in cross-sections BB and CC, the gate dielectric layer 810 can be formed around the nanostructure channel 315. In some embodiments, the gate dielectric layer 810 is also formed over the mesa region 310. Deposition tools can be used to deposit the gate dielectric layer 810 using PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, the gate dielectric layer 810 is a high-dielectric-constant gate dielectric layer comprising one or more high-dielectric-constant materials (e.g., dielectric materials having a dielectric constant greater than that of silicon dioxide (SiO2) (dielectric constant about 3.9)). Examples include lanthanum oxide (La). x O y For example, La2O3), hafnium oxide (HfO) x For example, HfO2), zirconium oxide (ZrO2) x For example, ZrO2) and / or aluminum oxide (Al) x O y Examples include, for instance, Al₂O₃. Additionally and / or alternatively, silicon dioxide (SiO₂) and / or other dielectric materials may be used instead of high-dielectric-constant dielectric materials. In some embodiments, the gate dielectric layer 810 may have a thickness ranging from about 0.5 nanometers to about 3 nanometers. However, other values ​​in the range are within the scope of this disclosure.

[0206] like Figure 8D As further shown, a gate structure 815 of the nanostructure transistor of the semiconductor device 105 can be formed above the gate dielectric layer 810. The gate structure 815 can be formed in the space 805 previously occupied by the sacrificial dielectric layer 415, such that the gate structure 815 surrounds the nanostructure channel 315 above one or more sides of the nanostructure channel 315. The material of the gate structure 815 can be deposited between vertically adjacent nanostructure channels 315.

[0207] The gate structure 815 includes one or more conductive metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo). Deposition tools can be used to deposit the gate structure 815 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The gate structure 815 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the gate structure 815 is deposited over the seed layer. In some embodiments, after depositing the gate structure 815, a planarization tool can be used to planarize the gate structure 815.

[0208] In some embodiments, one or more work function metal layers (not shown) may be deposited over the gate dielectric layer 810, and a gate structure 815 may be deposited over the one or more work function metal layers. The work function metal layers may be used to adjust the work function of the gate structure 815.

[0209] In some embodiments, for a PMOS nanostructure transistor, the gate structure 815 is a p-type gate structure, and a p-type work function metal layer is formed as the gate structure 815. In some embodiments, the p-type work function metal layer may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals having a work function greater than about 4.7 eV, to adjust the work function of the gate structure 815 such that the adjusted work function is close to the valence band (E) of the material of the nanostructure channel 315. V ).

[0210] In some embodiments, for NMOS nanostructure transistors, the gate structure 815 is an n-type gate structure, and an n-type work function metal layer is formed as the gate structure 815. In some embodiments, the n-type work function metal layer may include one or more n-type metals, such as titanium aluminum (TiAl) and / or titanium aluminum carbon (TiAlC), to adjust the work function of the gate structure 815 so that the work function is close to the conduction band (E) of the material of the nanostructure channel 315. C ).

[0211] As shown above, Figures 8A to 8D One example is provided. Other examples are available. Figures 8A to 8D The differences mentioned.

[0212] Figures 9A to 9D This is a schematic diagram of an exemplary embodiment 900 of forming the semiconductor device 105 described herein. Figure 9A As shown, the source / drain recess formation process in Example Implementation 900 may be combined with... Figure 3 The source / drain recess formation process shown differs from the described process because the source / drain recess 305 is formed at a depth in the z-direction within the semiconductor device 105. This means the bottom of the source / drain recess 305 does not extend downwards (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as... Figure 9AAs shown, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height above the bottom surface of the bottommost sacrificial semiconductor layer 120 in the semiconductor device 105.

[0213] The etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0214] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0215] like Figure 9B As shown, the sacrificial semiconductor layer 120 can be replaced by a sacrificial dielectric layer 415 and internal spacers 505. The sacrificial semiconductor layer 120 can be combined with... Figures 4A to 4C The similar method described above is replaced by a sacrificial dielectric layer 415, and the internal spacers 505 can be bonded. Figure 5 The method described above is used to form it.

[0216] like Figure 9C As shown, a source / drain region 610 is formed in the source / drain recess 305. The source / drain region 610 is combined with... Figures 6A to 6B The method described herein is similar, except that the discontinuous epitaxial region 605 is omitted from the semiconductor device 105 in Example Embodiment 900. Furthermore, the source / drain region 610 is formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or may be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which may occur through the mesa region 310.

[0217] like Figure 9D As shown, dielectric layer 705 and capping layer 710 can be combined. Figure 7A and Figure 7BA similar method as described above can be used to form it. Furthermore, the alternative gate process for semiconductor device 105 can be combined with... Figures 8A to 8D The method described above is performed to replace the dummy gate structure 205 and the sacrificial dielectric layer 415 with the gate dielectric layer 810 and the gate structure 815.

[0218] As shown above, Figures 9A to 9D One example is provided. Other examples are available. Figures 9A to 9D The differences mentioned.

[0219] Figures 10A to 10D This is a schematic diagram of an exemplary embodiment 1000 of forming the semiconductor device 105 described herein. Figure 10A As shown, the source / drain recess formation process in Example Implementation 1000 may be combined with... Figure 3 The source / drain recess formation process shown differs from the described process because the source / drain recess 305 is formed at a depth in the z-direction within the semiconductor device 105. This means the bottom of the source / drain recess 305 does not extend downwards (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as... Figure 10A As shown, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height above the bottom surface of the bottommost sacrificial semiconductor layer 120 in the semiconductor device 105.

[0220] The etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0221] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0222] like Figure 10B As shown, the sacrificial semiconductor layer 120 can be replaced by a sacrificial dielectric layer 415 and internal spacers 505. The sacrificial semiconductor layer 120 can be combined with... Figures 4A to 4C The similar method described above is replaced by a sacrificial dielectric layer 415, and the internal spacers 505 can be bonded. Figure 5 The method described above is used to form it.

[0223] like Figure 10C As shown, a discontinuous epitaxial region 605 and a source / drain region 610 are formed in the source / drain recess 305. The discontinuous epitaxial region 605 can be formed above the internal spacer 505, and the source / drain region 610 is combined with... Figure 6A and Figure 6B The source / drain region 610 is formed using a method similar to that described herein. However, the source / drain region 610 is formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or, in the semiconductor device 105, it can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which may occur through the mesa region 310.

[0224] like Figure 10D As shown, dielectric layer 705 and capping layer 710 can be combined. Figure 7A and Figure 7B A similar method as described above can be used to form it. Furthermore, the alternative gate process for semiconductor device 105 can be combined with... Figures 8A to 8D The method described above is performed to replace the dummy gate structure 205 and the sacrificial dielectric layer 415 with the gate dielectric layer 810 and the gate structure 815.

[0225] As shown above, Figures 10A to 10D One example is provided. Other examples are available. Figures 10A to 10D The differences mentioned.

[0226] Figures 11A to 11D This is a schematic diagram of an exemplary embodiment 1100 of forming a semiconductor device 105 as described herein. In exemplary embodiment 1100, an isolation spacer 1105 is formed at the bottom of the source / drain recess 305 to control the formation of the source / drain region 610 within the source / drain recess 305. In particular, the isolation spacer 1105 defines the position of the bottom surface of the source / drain region 610, which enables the source / drain region 610 to be formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial semiconductor layer 120 are approximately coplanar, or can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105.

[0227] like Figure 11A As shown, the source / drain recess formation process in Example Implementation 1100 may be combined with... Figure 3The source / drain recess formation process shown differs from the described process because the source / drain recess 305 is formed at a depth in the z-direction within the semiconductor device 105. This means the bottom of the source / drain recess 305 does not extend downwards (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as... Figure 10A As shown, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height above the bottom surface of the bottommost sacrificial semiconductor layer 120 in the semiconductor device 105.

[0228] The etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0229] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0230] like Figure 11A As further shown, the sacrificial semiconductor layer 120 can be replaced by a sacrificial dielectric layer 415 and internal spacers 505. The sacrificial semiconductor layer 120 can be combined with... Figures 4A to 4C The similar method described herein is replaced by a sacrificial dielectric layer 415, and the internal spacers 505 can be bonded. Figure 5 The method described above is used to form it.

[0231] like Figure 11B As shown, an isolation spacer 1105 is formed at the bottom of the source / drain recess 305. The isolation spacer 1105 can be formed such that the top surface of the isolation spacer 1105 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or in the semiconductor device 105 it can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415.

[0232] In some embodiments, the spacer 1105 comprises a dielectric material, such as silicon oxide (SiO2). x ) and / or silicon nitride (Si x N yExamples include [examples of other methods]. In these embodiments, deposition tools can be used to deposit spacer 1105 using PVD, ALD, CVD, and / or other suitable deposition techniques. In some embodiments, spacer 1105 comprises a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe)) or a doped semiconductor material (e.g., a p-type doped semiconductor material, an n-type doped semiconductor material, a carbon (C) doped semiconductor material). In these embodiments, deposition tools can be used to deposit spacer 1105 using epitaxial growth techniques.

[0233] In some embodiments, the spacer 1105 has a z-direction thickness smaller than that of the inner spacer 505. In some embodiments, the z-direction thickness of the spacer 1105 is in the range of about 1 nanometer to about 3 nanometers. However, other values ​​and ranges of the z-direction thickness of the spacer 1105 are within the scope of this disclosure.

[0234] like Figure 11C As shown, a discontinuous epitaxial region 605 and a source / drain region 610 are formed in the source / drain recess 305. The discontinuous epitaxial region 605 can be formed above the internal spacer 505, and the source / drain region 610 is coupled with... Figure 6A and Figure 6B A similar method as described above is used to form it. However, the source / drain region 610 is formed above the isolation spacer 1105 in the source / drain recess 305. The isolation spacer 1105 ensures that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or in the semiconductor device 105, it can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which may occur through the mesa region 310.

[0235] like Figure 11D As shown, dielectric layer 705 and capping layer 710 can be combined. Figure 7A and Figure 7B A similar method as described above can be used to form it. Furthermore, the alternative gate process for semiconductor device 105 can be combined with... Figures 8A to 8D The method described above is performed to replace the dummy gate structure 205 and the sacrificial dielectric layer 415 with the gate dielectric layer 810 and the gate structure 815.

[0236] As shown above, Figures 11A to 11D One example is provided. Other examples are available. Figures 11A to 11D The differences mentioned.

[0237] Figures 12A to 12CThis is a schematic diagram of an exemplary embodiment 1200 of forming the semiconductor device 105 described herein. In exemplary embodiment 1200, discontinuous epitaxial regions 605 are primarily formed on the endpoints of nanostructure channels 315 exposed through source / drain recesses 305, which is consistent with... Figure 6A and Figure 6B The example embodiment 600 shown in the example is mainly formed on the internal spacer 505 in the opposite way.

[0238] like Figure 12A As shown, the source / drain recess formation process in Example Implementation 1200 may be combined with... Figure 3 The source / drain recess formation process shown differs from the described process because the source / drain recess 305 is formed at a depth in the z-direction within the semiconductor device 105. This means the bottom of the source / drain recess 305 does not extend downwards (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as... Figure 12A As shown, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height above the bottom surface of the bottommost sacrificial semiconductor layer 120 in the semiconductor device 105.

[0239] The etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0240] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0241] like Figure 12A As further shown, the sacrificial semiconductor layer 120 can be replaced by a sacrificial dielectric layer 415 and internal spacers 505. The sacrificial semiconductor layer 120 can be combined with... Figures 4A to 4C The similar method described herein is replaced by a sacrificial dielectric layer 415, and the internal spacers 505 can be bonded. Figure 5 The method described above is used to form it.

[0242] like Figure 12CAs shown, discontinuous epitaxial regions 605 and 610 are formed in the source / drain recess 305. The discontinuous epitaxial regions 605 and 610 can be combined. Figure 6A and Figure 6B The source / drain region 610 is formed using a method similar to that described herein. However, the source / drain region 610 is formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or, in the semiconductor device 105, it can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which may occur through the mesa region 310.

[0243] In addition, such as Figure 12B As shown in the close-up view, the discontinuous epitaxial region 605 is mainly formed at the endpoints of the nanostructure channel 315 exposed through the source / drain recess 305, which is consistent with... Figure 6A and Figure 6B The example embodiment 600 shown in the example is formed primarily on the internal spacer 505, in contrast. In example embodiment 1200, the epitaxial region 605 may continuously span the endpoints of the nanostructure channel 315 and portions of the internal spacer 505 on the vertically opposite side of the nanostructure channel 315. Therefore, an overlap region 615 occurs where the vertical endpoint portion of the epitaxial region 605 overlaps with the portion of the internal spacer 505 on the vertically opposite side of the nanostructure channel 315.

[0244] Compared to Figure 6A and Figure 6B In Example Implementation 600, the epitaxial process parameters used to achieve the formation of the discontinuous epitaxial region 605 are different from those used in Example Implementation 1200, where different epitaxial process parameters can be used to achieve the formation of the discontinuous epitaxial region 605. Examples include different chamber pressures, different deposition temperatures, different gas flow rates, different annealing temperatures, and / or different growth rates. Figure 6A and Figure 6B The location where the discontinuous epitaxial region 605 is formed in Example Implementation 600 can be used to achieve the location where the discontinuous epitaxial region 605 is formed in Example Implementation 1200.

[0245] like Figure 12C As shown, dielectric layer 705 and capping layer 710 can be combined. Figure 7A and Figure 7B A similar method as described above can be used to form it. Furthermore, the alternative gate process for semiconductor device 105 can be combined with... Figures 8A to 8DThe method described above is performed to replace the dummy gate structure 205 and the sacrificial dielectric layer 415 with the gate dielectric layer 810 and the gate structure 815.

[0246] As shown above, Figures 12A to 12C One example is provided. Other examples are available. Figures 12A to 12C The differences mentioned.

[0247] Figures 13A to 13C This is a schematic diagram of an exemplary embodiment 1300 of forming a semiconductor device 105 as described herein. In exemplary embodiment 1300, discontinuous epitaxial regions 605 are formed such that each epitaxial region 605 spans a portion smaller than the entirety of the nanostructure channel 315 and a portion smaller than the entirety of the adjacent internal spacer 505.

[0248] like Figure 13A As shown, the source / drain recess formation process in Example Implementation 1300 may be combined with... Figure 3 The source / drain recess formation process shown differs from the described process because the source / drain recess 305 is formed at a depth in the z-direction within the semiconductor device 105. This means the bottom of the source / drain recess 305 does not extend downwards (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as... Figure 13A As shown, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height above the bottom surface of the bottommost sacrificial semiconductor layer 120 in the semiconductor device 105.

[0249] The etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0250] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0251] like Figure 13AAs further shown, the sacrificial semiconductor layer 120 can be replaced by a sacrificial dielectric layer 415 and internal spacers 505. The sacrificial semiconductor layer 120 can be combined with... Figures 4A to 4C The similar method described herein is replaced by a sacrificial dielectric layer 415, and the internal spacers 505 can be bonded. Figure 5 The method described above is used to form it.

[0252] like Figure 13C As shown, discontinuous epitaxial regions 605 and 610 are formed in the source / drain recess 305. The discontinuous epitaxial regions 605 and 610 can be combined. Figure 6A and Figure 6B The source / drain region 610 is formed using a method similar to that described herein. However, the source / drain region 610 is formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or, in the semiconductor device 105, it can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which may occur through the mesa region 310.

[0253] In addition, such as Figure 13B As shown in the close-up view, discontinuous epitaxial regions 605 are formed such that each epitaxial region 605 spans a portion smaller than the entirety of the nanostructure channel 315 and a portion smaller than the entirety of the adjacent internal spacer 505, which is consistent with... Figure 6A and Figure 6B The example embodiment 600 shown in the example is primarily formed on the internal spacer 505, in contrast. In example embodiment 1300, the epitaxial region 605 may continuously span only a portion of the single nanostructure channel 315 and only a portion of the adjacent internal spacer 505. Thus, the epitaxial region 605 is above the interface between the adjacent nanostructure channel 315 and the internal spacer 505.

[0254] Compared to Figure 6A and Figure 6B In Example Implementation 600, the epitaxial process parameters used to achieve the formation of the discontinuous epitaxial region 605 are different from those used in Example Implementation 1300. Different epitaxial process parameters can be used to achieve the formation of the discontinuous epitaxial region 605. Examples include different chamber pressures, different deposition temperatures, different gas flow rates, different annealing temperatures, and / or different growth rates. Figure 6A and Figure 6B The location where the discontinuous epitaxial region 605 is formed in Example Implementation 600 can be used to achieve the location where the discontinuous epitaxial region 605 is formed in Example Implementation 1300.

[0255] like Figure 13C As shown, dielectric layer 705 and capping layer 710 can be combined. Figure 7A and Figure 7B A similar method as described above can be used to form it. Furthermore, the alternative gate process for semiconductor device 105 can be combined with... Figures 8A to 8D The method described above is performed to replace the dummy gate structure 205 and the sacrificial dielectric layer 415 with the gate dielectric layer 810 and the gate structure 815.

[0256] As shown above, Figures 13A to 13C One example is provided. Other examples are available. Figures 13A to 13C The differences mentioned.

[0257] Figures 14A to 14F This is a schematic diagram of an exemplary embodiment 1400 of forming a semiconductor device 105 as described herein. Exemplary embodiment 1400 includes an example of forming a multilayer structure with a sacrificial dielectric layer 415.

[0258] like Figure 14A As shown, the source / drain recess formation process in Example Implementation 1400 may be combined with... Figure 3 The source / drain recess formation process shown differs from the described process because the source / drain recess 305 is formed at a depth in the z-direction within the semiconductor device 105. This means the bottom of the source / drain recess 305 does not extend downwards (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as... Figure 14A As shown, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height above the bottom surface of the bottommost sacrificial semiconductor layer 120 in the semiconductor device 105.

[0259] like Figure 14B As shown, combined Figures 4A to 4C The same method described above can remove the sacrificial semiconductor layer 120.

[0260] like Figure 14C As shown, combined Figures 4A to 4C In a similar method, the sacrificial semiconductor layer 120 can be replaced by a sacrificial dielectric layer 415, except that the sacrificial dielectric layer 415 forms a multilayer structure. The multilayer structure includes a core 415b and a substrate 415a. The substrate 415a may surround the core 415b between the core 415b and the nanostructure channel 315. The substrate 415a may have a smaller thickness than the core 415b. For example, the substrate 415a may have a thickness of about 1 nanometer, while the core 415b may have a thickness greater than 1 nanometer. However, other values ​​are within the scope of this disclosure.

[0261] Core 415b may include low-elasticity materials, such as low-density silicon oxide (SiO2). x Porous silica, other porous dielectric materials with extremely low dielectric constants, and / or other materials with Young's moduli smaller than that of the nanostructure channel 315. Core 415b can be deposited as a flowable film (e.g., as described above). Figures 4A to 4C (as described in the text) to achieve a low-density core 415b. The substrate 415a comprises a high-density dielectric material, such as silicon nitride (Si). x N y ) or other high dielectric constant dielectric materials, high-density silicon oxide (SiO2) x (and / or other high-density materials.) Liner 415a can be deposited by ALD to achieve high density and nanometer thickness liner 415a.

[0262] The core 415b provides the sacrificial dielectric layer 415 with low elasticity, enabling it to resist and absorb stress induced in the nanostructured channel 315. The liner 415a provides higher elasticity than the core 415b and reduces the likelihood of deformation of the nanostructured channel 315. The nanometer thickness of the liner 415a allows it to support the nanostructured channel 315 without reducing (or minimally reducing) the stress applied to it.

[0263] like Figure 14C As further shown, an internal spacer 505 can be formed in the cavity 420 at the endpoint of the sacrificial dielectric layer 415. The internal spacer 505 can be bonded to... Figure 5 The similar method is used to form, except for the inner surface of the internal spacer 505 formed above the core 415b and the liner 415a of the sacrificial dielectric layer 415.

[0264] like Figure 14D As shown, after forming the internal spacer 505, discontinuous epitaxial regions 605 and source / drain regions 610 can be formed in the source / drain recess 305. In some embodiments, combined with Figure 6A and Figure 6B A similar method is used to form a discontinuous epitaxial region 605 above the internal spacer 505. In some embodiments, combined with Figures 12A to 12C A similar method forms a discontinuous epitaxial region 605 above the endpoint of the nanostructure channel 315. In some embodiments, combined with Figures 13A to 13C A similar method forms a discontinuous epitaxial region 605 above the endpoints of the nanostructure channel 315 and above the internal spacer 505. In some embodiments, combined with Figures 9A to 9D The similar method described above omits the discontinuous epitaxial region 605. In some embodiments, it is combined with... Figures 9A to 9DThe same method described above forms the source / drain region 610.

[0265] like Figure 14E As shown, it can be combined Figure 7A and Figure 7B The dielectric layer 705 and the capping layer 710 are formed using a method similar to that described in [the text]. For example... Figure 14E As further shown in the figure, it can be combined with Figures 8A to 8D The similar method removes the dummy gate structure 205 and the sacrificial dielectric layer 415, except that it removes the core 415b and the liner 415a of the sacrificial dielectric layer 415. In some embodiments, the core 415b and the liner 415a of the sacrificial dielectric layer 415 are removed together (e.g., in the same etch operation) from the semiconductor device 105. In some embodiments, the core 415b is removed in a first etch operation, and the liner 415a is removed in a second etch operation after the core 415b is removed.

[0266] like Figure 14F As shown, the dummy gate structure 205 and the sacrificial dielectric layer 415 can be combined Figures 8A to 8D The similar method described herein is replaced by a gate dielectric layer 810 and a gate structure 815.

[0267] As shown above, Figures 14A to 14F One example is provided. Other examples are available. Figures 14A to 14F The differences mentioned.

[0268] Figure 15 This is a schematic diagram of an exemplary embodiment 1500 of the semiconductor device 105 described herein. In exemplary embodiment 1500, the semiconductor device 105 includes one or more PMOS nanostructure transistors 1505 and / or one or more NMOS nanostructure transistors 1510. In some embodiments, the semiconductor device 105 includes only PMOS nanostructure transistors 1505. In some embodiments, the semiconductor device 105 includes only NMOS nanostructure transistors 1510.

[0269] In some embodiments, the PMOS nanostructure transistor 1505 may include a p-type gate structure 815a, which includes one or more p-type work function metals. In some embodiments, the PMOS nanostructure transistor 1505 may include a p-type source / drain region 610a, which includes one or more p-type doped semiconductor materials (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe)) such as boron (B) and / or germanium (Ge). Doping of the p-type source / drain region 610a may increase the electrical performance of the p-type source / drain region 610a and / or induce compressive stress in the PMOS nanostructure transistor 1505.

[0270] The discontinuous epitaxial region 605a of the PMOS nanostructure transistor 1505 may include a higher p-type doping concentration (e.g., B) than the p-type doping concentration included in the p-type source / drain region 610a. The higher p-type doping concentration allows the discontinuous epitaxial region 605a to withstand etching during the gate replacement process of the PMOS nanostructure transistor 1505, thus protecting the p-type source / drain region 610a from etching during the gate replacement process. In some embodiments, the discontinuous epitaxial region 605a of the PMOS nanostructure transistor 1505 may include less Ge doping. The lower Ge doping concentration allows the discontinuous epitaxial region 605a to better withstand etching during the gate replacement process of the PMOS nanostructure transistor 1505, thus protecting the p-type source / drain region 610a from etching during the gate replacement process. In some implementations, Ge doping can be omitted from the discontinuous epitaxial region 605a of the PMOS nanostructure transistor 1505.

[0271] In some embodiments, the NMOS nanostructure transistor 1510 may include an n-type gate structure 815b, which includes one or more n-type work function metals. In some embodiments, the NMOS nanostructure transistor 1510 may include an n-type source / drain region 610b, which includes one or more n-type doped semiconductor materials (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe)) doped with examples such as arsenic (As) and / or phosphorus (P). Furthermore, the n-type source / drain region 610b may be doped with carbon (C). The n-type doping of the n-type source / drain region 610b can increase the electrical performance of the n-type source / drain region 610b and induce tensile stress in the nanostructure channel 315 of the NMOS nanostructure transistor 1510. Additionally and / or alternatively, the n-type source / drain region 610b may include semiconductor alloys such as silicon-phosphorus (SiP) and / or silicon-arsenic (SiAs).

[0272] The discontinuous epitaxial region 605b of the NMOS nanostructure transistor 1510 may include a higher carbon doping concentration than that included in the n-type source / drain region 610b. This higher carbon doping concentration allows the discontinuous epitaxial region 605b to withstand etching during the gate replacement process of the NMOS nanostructure transistor 1510, thus protecting the n-type source / drain region 610b from etching during the gate replacement process. In some embodiments, carbon doping may be omitted from the discontinuous epitaxial region 605b of the NMOS nanostructure transistor 1510.

[0273] In some implementations, the discontinuous epitaxial region 605b of the NMOS nanostructure transistor 1510 may include less arsenic doping and / or less phosphorus doping. The lower doping concentration of arsenic and / or phosphorus allows the discontinuous epitaxial region 605b to better withstand etching during the gate replacement process of the NMOS nanostructure transistor 1510, thus protecting the n-type source / drain region 610b from etching during the gate replacement process.

[0274] As shown above, Figure 15 One example is provided. Other examples are available. Figure 15 The differences mentioned.

[0275] Figure 16 This is a schematic diagram of an exemplary embodiment 1600 of the semiconductor device 105 described herein. Figure 16As shown, the discontinuous epitaxial region 605 has an approximately triangular cross-sectional profile. The triangular cross-sectional profile of the discontinuous epitaxial region 605 can create a zig-zag profile sidewall 1605 for the source / drain region 610. For example, the sidewall 1605 may include segments 1610 and 1615, which are arranged alternately along the sidewall 1605. Segment 1610 may be at an angle in a first direction, and segment 1615 may be at an angle in a second direction. In some embodiments, the first and second directions are opposite (or mirror) directions.

[0276] In other embodiments, the discontinuous epitaxial region 605 may have an approximately half-circle or semi-circle cross-sectional profile. In some embodiments, the discontinuous epitaxial region 605 may have an amorphous cross-sectional profile.

[0277] In some embodiments, in electron microscope images (e.g., in transmission electron microscopy (TEM) images), a higher doping concentration of the discontinuous epitaxial region 605 relative to the source / drain region 610 of the semiconductor device 105 can cause the discontinuous epitaxial region 605 to appear darker relative to the source / drain region 610 in the microscope image. Therefore, the interface between the discontinuous epitaxial region 605 and the source / drain region 610 can be seen in the microscope image.

[0278] As shown above, Figure 16 One example is provided. Other examples are available. Figure 16 The differences mentioned.

[0279] Figure 17 This is a flowchart of an example process 1700 for forming a semiconductor device 105 as described herein. In some embodiments, the process is performed using one or more other types of semiconductor process tools, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or semiconductor process tools. Figure 17 One or more process blocks.

[0280] like Figure 17As shown, process 1700 may include forming a semiconductor channel layer and a sacrificial semiconductor layer, which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device (block 1710). For example, one or more semiconductor process tools may be used to form a semiconductor channel layer (e.g., semiconductor channel layer 125) and a sacrificial semiconductor layer (e.g., sacrificial semiconductor layer 120), which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0281] like Figure 17 As further shown, process 1700 may include performing a first etch operation to etch the semiconductor channel layer and the sacrificial semiconductor layer to form a source / drain recess (block 1720). For example, one or more semiconductor process tools may be used to perform the first etch operation to etch the semiconductor channel layer and the sacrificial semiconductor layer to form a source / drain recess (e.g., source / drain recess 305), as described herein. In some embodiments, the source / drain recess defines a nanostructured channel (e.g., nanostructured channel 315) arranged in a direction approximately perpendicular to the semiconductor substrate. In some embodiments, the nanostructured channels and the sacrificial semiconductor layer are arranged alternately in a direction approximately perpendicular to the semiconductor substrate.

[0282] like Figure 17 As further shown, process 1700 may include performing a second etch operation to remove a sacrificial semiconductor layer from the semiconductor device (block 1730). For example, one or more semiconductor process tools may be used to perform the second etch operation to remove the sacrificial semiconductor layer from the semiconductor device, as described herein.

[0283] like Figure 17 As further shown, process 1700 may include forming a sacrificial dielectric layer (block 1740) in the space previously occupied by a sacrificial semiconductor layer between nanostructure channels. For example, one or more semiconductor process tools may be used to form a sacrificial dielectric layer (e.g., sacrificial dielectric layer 415) in the space previously occupied by a sacrificial semiconductor layer (e.g., space 405) between nanostructure channels, as described herein.

[0284] like Figure 17 As further shown, process 1700 may include forming source / drain regions in the source / drain recess (block 1750). For example, one or more semiconductor process tools may be used to form source / drain regions (e.g., source / drain region 610, p-type source / drain region 610a, n-type source / drain region 610b) in the source / drain recess, as described herein.

[0285] Process 1700 may include additional implementations, such as any single implementation or any combination of implementations described below and / or related to one or more other processes described elsewhere herein.

[0286] In the first embodiment, performing a second etching operation to remove the sacrificial semiconductor layer includes performing a second etching operation to remove the sacrificial semiconductor layer through a source / drain recess.

[0287] In the second embodiment, either alone or in combination with the first embodiment, forming the sacrificial dielectric layer includes forming a dielectric layer on the sidewalls of the source / drain recess and in the space previously occupied by the sacrificial semiconductor layer between the nanostructure channels, and performing a third etching operation to trim the dielectric layer such that a portion of the dielectric layer remaining in the space previously occupied by the sacrificial semiconductor layer between the nanostructure channels serves as the sacrificial dielectric layer.

[0288] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the Young's modulus of the dielectric material of the sacrificial dielectric layer is less than the Young's modulus of the semiconductor material of the sacrificial semiconductor layer.

[0289] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the Young's modulus of the dielectric material of the sacrificial dielectric layer is smaller than the Young's modulus of the semiconductor material of the nanostructure channel.

[0290] In the fifth embodiment, the sacrificial dielectric layer comprises porous silicon oxide (SiO2), either alone or in combination with one or more of the first to fourth embodiments. x )Material.

[0291] In the sixth embodiment, the sacrificial dielectric layer is formed, either alone or in combination with one or more of the first to fifth embodiments, by depositing a substrate (e.g., substrate 415a) of the sacrificial dielectric layer via ALD, and by depositing a porous silicon oxide (SiO2) substrate of the sacrificial dielectric layer. x The nucleus (e.g., nucleus 415b) serves as a flowable membrane.

[0292] Although Figure 17 The example block of display process 1700, in some implementations, is compared to... Figure 17 As described herein, process 1700 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently. Additionally or alternatively, two or more blocks in process 1700 can be executed in parallel.

[0293] Figure 18This is a flowchart of an example process 1800 for forming a semiconductor device as described herein. In some embodiments, the process is performed using one or more other types of semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or semiconductor process tools. Figure 18 One or more process blocks.

[0294] like Figure 18 As shown, process 1800 may include forming a semiconductor channel layer and a sacrificial semiconductor layer, which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device (block 1810). For example, one or more semiconductor process tools may be used to form a semiconductor channel layer (e.g., semiconductor channel layer 125) and a sacrificial semiconductor layer (e.g., sacrificial semiconductor layer 120), which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0295] like Figure 18 As further shown, process 1800 may include forming a source / drain recess through a semiconductor channel layer and a sacrificial semiconductor layer (block 1820). For example, one or more semiconductor process tools may be used to form a source / drain recess (e.g., source / drain recess 305) through a semiconductor channel layer and a sacrificial semiconductor layer, as described herein.

[0296] like Figure 18 As further shown, process 1800 may include removing a sacrificial semiconductor layer from a semiconductor device via a source / drain recess (block 1830). For example, one or more semiconductor process tools may be used to remove a sacrificial semiconductor layer from a semiconductor device via a source / drain recess, as described herein.

[0297] like Figure 18 As further shown, process 1800 may include forming a sacrificial dielectric layer (block 1840) in a space previously occupied by a sacrificial semiconductor layer between semiconductor channel layers. For example, one or more semiconductor process tools may be used to form a sacrificial dielectric layer (e.g., sacrificial dielectric layer 415) in a space previously occupied by a sacrificial semiconductor layer (e.g., space 405) between semiconductor channel layers, as described herein.

[0298] like Figure 18As further shown, process 1800 may include forming an internal spacer (block 1850) over the endpoints of the sacrificial dielectric layer exposed via the source / drain recess. For example, one or more semiconductor process tools may be used to form the internal spacer (e.g., internal spacer 505) over the endpoints of the sacrificial dielectric layer exposed via the source / drain recess, as described herein.

[0299] like Figure 18 As further shown, process 1800 may include forming a discontinuous epitaxial region (block 1860) above the sidewalls of the source / drain recess. For example, one or more semiconductor process tools may be used to form a discontinuous epitaxial region (e.g., discontinuous epitaxial region 605) above the sidewalls of the source / drain recess, as described herein.

[0300] like Figure 18 As further shown, process 1800 may include forming a source / drain region over a discontinuous epitaxial region in the source / drain recess (block 1870). For example, one or more semiconductor process tools may be used to form the source / drain region (e.g., source / drain region 610, p-type source / drain region 610a, n-type source / drain region 610b) over a discontinuous epitaxial region in the source / drain recess, as described herein.

[0301] Process 1800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or related to one or more other processes described elsewhere herein.

[0302] In the first embodiment, forming a discontinuous epitaxial region includes forming a discontinuous epitaxial region above the internal spacer.

[0303] In the second embodiment, either alone or in combination with the first embodiment, forming a discontinuous epitaxial region includes forming a discontinuous epitaxial region above the endpoints of the semiconductor channel layer exposed by the source / drain recess.

[0304] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 1800 includes forming a bottom isolation spacer (e.g., isolation spacer 1105) at the bottom of the source / drain recess and forming a source / drain region above the bottom isolation spacer in the source / drain recess.

[0305] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the top surface of the bottom isolation spacer in the semiconductor device is higher than the bottommost inner spacer of the inner spacer in the source / drain recess.

[0306] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the p-type transistor structure of the semiconductor device (e.g., PMOS nanostructure transistor 1505) includes source / drain regions, and the discontinuous epitaxial regions include p-type doped semiconductor materials such as B.

[0307] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the n-type transistor structure of the semiconductor device (e.g., NMOS nanostructure transistor 1510) includes source / drain regions, and the discontinuous epitaxial regions include a carbon (C) doped semiconductor material.

[0308] Although Figure 18 The example block of display process 1800, in some implementations, is compared to... Figure 18 As described herein, process 1800 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently. Additionally or alternatively, two or more blocks of process 1800 can be executed in parallel.

[0309] Figures 19A to 19F This is a schematic diagram of an exemplary embodiment 1900 of forming the semiconductor device 105 described herein. Exemplary embodiment 1900 includes an example of a multilayer structure forming a sacrificial dielectric layer 415. Exemplary embodiment 1900 is similar to... Figures 14A to 14F In the example embodiment 1400 shown, the core 415b of the sacrificial dielectric layer 415 is implemented as air spacers. Therefore, the dielectric constant of the core 415b of the sacrificial dielectric layer 415 can have a dielectric constant of about 1.0.

[0310] As shown above, Figures 19A to 19F One example is provided. Other examples are available. Figures 19A to 19F The differences mentioned above.

[0311] Figures 20A to 20F This is a schematic diagram of an exemplary embodiment 2000 of forming the semiconductor device 105 described herein. Exemplary embodiment 2000 is similar to... Figures 10A to 10D The example embodiment 900 shown is an example in which the sacrificial dielectric layer 415 is implemented as an air spacer. Therefore, the dielectric constant of the sacrificial dielectric layer 415 can have a dielectric constant of about 1.0.

[0312] As shown above, Figures 20A to 20F One example is provided. Other examples are available. Figures 20A to 20F The differences mentioned above.

[0313] Thus, a sacrificial semiconductor layer is removed from the semiconductor device's layer stack before the formation of the internal spacers and source / drain regions of the nanostructured transistors. The sacrificial semiconductor layer can be removed together with a hybrid layer, formed by mixing the materials of the sacrificial semiconductor layer and the semiconductor channel layer, and both the sacrificial semiconductor layer and the hybrid layer can be replaced by a sacrificial dielectric layer. The sacrificial dielectric layer can then be etched to form cavities, within which internal spacers are formed. Compared to the selectivity between the sacrificial semiconductor layer and the semiconductor channel layer, the sacrificial dielectric layer provides greater etch selectivity between them, enabling increased control over over-etching of the cavities. Additionally and / or alternatively, the dielectric material of the sacrificial dielectric layer can have lower elasticity than the material of the sacrificial semiconductor layer.

[0314] As described in more detail above, some embodiments described herein provide a method of forming a semiconductor device. The method includes forming a semiconductor channel layer and a sacrificial semiconductor layer, such that the semiconductor channel layer and the sacrificial semiconductor layer are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The method includes performing a first etch operation to etch the semiconductor channel layer and the sacrificial semiconductor layer to form source / drain recesses, the source / drain recesses defining nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate, the nanostructured channels and the sacrificial semiconductor layer being arranged alternately in a direction approximately perpendicular to the semiconductor substrate. The method includes performing a second etch operation to remove the sacrificial semiconductor layer from the semiconductor device. The method includes forming a sacrificial dielectric layer in spaces previously occupied by the sacrificial semiconductor layer between the nanostructured channels. The method includes forming source / drain regions in the source / drain recesses. In some embodiments, performing the second etch operation to remove the sacrificial semiconductor layer includes performing a second etch operation to remove the sacrificial semiconductor layer through the source / drain recesses. In some embodiments, forming a sacrificial dielectric layer includes forming a dielectric layer on the sidewalls of the source / drain recesses and in the spaces between the nanostructure channels, the spaces previously occupied by a sacrificial semiconductor layer, and performing a third etch operation to trim the dielectric layer such that a portion of the dielectric layer remains in the spaces between the nanostructure channels as a sacrificial dielectric layer, the spaces previously occupied by the sacrificial semiconductor layer. In some embodiments, the Young's modulus of the dielectric material of the sacrificial dielectric layer is less than the Young's modulus of the semiconductor material of the sacrificial semiconductor layer. In some embodiments, the Young's modulus of the dielectric material of the sacrificial dielectric layer is less than the Young's modulus of the semiconductor material of the nanostructure channels. In some embodiments, the sacrificial dielectric layer comprises a porous silicon oxide material. In some embodiments, forming a sacrificial dielectric layer comprises a substrate deposited by atomic layer deposition of the sacrificial dielectric layer, and a porous silicon oxide core deposited as a flowable film.

[0315] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes nanostructured channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure surrounding the nanostructured channels. The semiconductor device includes source / drain regions on one side of an adjacent gate structure and at the endpoints of adjacent nanostructured channels. The semiconductor device includes an internal spacer between the source / drain regions and the gate structure. The semiconductor device includes a discontinuous region between the source / drain regions and at least one nanostructured channel or internal spacer. In some embodiments, the epitaxial region in the discontinuous epitaxial region continuously spans an internal spacer of the internal spacer, a portion of the endpoint of a first nanostructured channel of the nanostructured channel perpendicularly adjacent to the internal spacer, and a portion of the endpoint of a second nanostructured channel of the nanostructured channel perpendicularly adjacent to the internal spacer. In some embodiments, the epitaxial region in the discontinuous epitaxial region continuously spans an endpoint of the nanostructured channel, a portion perpendicularly adjacent to a first internal spacer of the nanostructured channel, and a portion perpendicularly adjacent to a second internal spacer of the nanostructured channel. In some embodiments, an epitaxial region in a discontinuous epitaxial region continuously spans a portion of a single internal spacer of an internal spacer and a portion of the endpoint of a single nanostructure channel of a nanostructure channel, the endpoint of the single nanostructure channel being perpendicularly adjacent to the internal spacer. In some embodiments, another epitaxial region in a discontinuous epitaxial region continuously spans a portion of another single internal spacer perpendicularly adjacent to the internal spacer of a nanostructure channel, and another portion of the endpoint of the nanostructure channel. In some embodiments, the bottom surface of the source / drain region and the bottom surface of a subset of internal spacers located at the bottom of the source / drain region are approximately coplanar.

[0316] As described in more detail above, some embodiments described herein provide a method of forming a semiconductor device. The method includes forming a semiconductor channel layer and a sacrificial semiconductor layer, such that the semiconductor channel layer and the sacrificial semiconductor layer are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The method includes forming source / drain recesses through the semiconductor channel layer and the sacrificial semiconductor layer. The method includes removing the sacrificial semiconductor layer from the semiconductor device through the source / drain recess. The method includes forming a sacrificial dielectric layer in a space previously occupied by the sacrificial semiconductor layer between the semiconductor channel layers. The method includes forming an internal spacer over the endpoints of the sacrificial dielectric layer exposed by the source / drain recess. The method includes forming a discontinuous epitaxial region over the sidewalls of the source / drain recess. The method includes forming a source / drain region over the discontinuous epitaxial region in the source / drain recess. In some embodiments, forming the discontinuous epitaxial region includes forming the discontinuous epitaxial region on the internal spacer. In some embodiments, forming the discontinuous epitaxial region includes forming the discontinuous epitaxial region at the endpoints of the semiconductor channel layer exposed in the source / drain recess. In some embodiments, the method further includes forming a bottom isolation spacer at the bottom of the source / drain recess, and forming a source / drain region includes forming the source / drain region on the bottom isolation spacer in the source / drain recess. In some embodiments, the top surface of the bottom isolation spacer in the semiconductor device is higher than the bottommost inner spacer of the inner spacer in the source / drain recess. In some embodiments, the source / drain region is included in a p-type transistor structure of the semiconductor device, and the discontinuous epitaxial region includes p-type doped semiconductor material. In some embodiments, the source / drain region is included in an n-type transistor structure of the semiconductor device, and the discontinuous epitaxial region includes carbon doped semiconductor material.

[0317] As described in more detail above, some embodiments described herein provide a semiconductor device including nanostructured channels arranged in an orientation perpendicular to the semiconductor substrate, a gate structure surrounding the nanostructured channels, a source / drain region adjacent to one side of the gate structure and adjacent to the endpoint of the nanostructured channels, an internal spacer between the source / drain region and the gate structure, and a discontinuous epitaxial region adjacent to the source / drain region. The epitaxial region in the discontinuous epitaxial region continuously spans one of the internal spacers, a portion of the endpoint of a first nanostructured channel in the nanostructured channels, the portion of the endpoint of the first nanostructured channel being perpendicularly adjacent to the internal spacer. In some embodiments, the semiconductor device further includes a bottom isolation spacer located below the source / drain regions. In some embodiments, the source / drain regions are included in a p-type transistor structure of the semiconductor device, wherein the discontinuous epitaxial region includes p-type doping.

[0318] As described in more detail above, some embodiments described herein provide a semiconductor device including nanostructure channels arranged in an orientation perpendicular to the semiconductor device, a gate structure surrounding the nanostructure channels, a source / drain region adjacent to one side of the gate structure and adjacent to the endpoint of the nanostructure channels, an internal spacer between the source / drain region and the gate structure, and a discontinuous epitaxial region between the source / drain region and the nanostructure channels and the internal spacer.

[0319] The terms “approximately” and “substantially” can refer to a given quantity of value that varies within a range of 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and are not intended to be limiting. The terms “approximately” and “substantially” can refer to a percentage of that value given the given quantity disclosed herein.

[0320] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoint of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Multiple nanostructured channels are arranged in one direction, which is perpendicular to a semiconductor substrate of the semiconductor device; A gate structure surrounds the plurality of nanostructure channels; A source / drain region, adjacent to one side of the gate structure and adjacent to multiple endpoints of the plurality of nanostructure channels; Multiple internal spacers exist between the source / drain region and the gate structure; as well as Multiple discontinuous epitaxial regions, adjacent to the source / drain region, wherein one of the multiple discontinuous epitaxial regions continuously spans: One of the plurality of internal spacers A portion of one end of a first nanostructure channel of the plurality of nanostructure channels is perpendicularly adjacent to the internal spacer.

2. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A bottom isolation spacer is located below the source / drain region.

3. The semiconductor device as claimed in claim 1, characterized in that, The source / drain region is contained within a p-type transistor structure of the semiconductor device; and The plurality of discontinuous epitaxial regions include a p-type dopant.

4. A semiconductor device, characterized in that, include: Multiple nanostructured channels are arranged in one direction, which is perpendicular to a semiconductor substrate of the semiconductor device; A gate structure surrounds the plurality of nanostructure channels; A source / drain region, adjacent to one side of the gate structure and adjacent to multiple endpoints of the plurality of nanostructure channels; Multiple internal spacers exist between the source / drain region and the gate structure; as well as Multiple discontinuous epitaxial regions exist between the source / drain region and at least one of the following: The multiple nanostructure channels, or The plurality of internal spacers.

5. The semiconductor device as claimed in claim 4, characterized in that, One of the plurality of discontinuous epitaxial regions continuously spans: One of the plurality of internal spacers A portion of one end of a first nanostructure channel among the plurality of nanostructure channels, wherein the portion of that end of the first nanostructure channel is perpendicularly adjacent to the internal spacer, and A portion of one end of a second nanostructure channel among the plurality of nanostructure channels is perpendicularly adjacent to the internal spacer.

6. The semiconductor device as claimed in claim 4, characterized in that, One of the plurality of discontinuous epitaxial regions continuously spans: One end of a first nanostructure channel among the plurality of nanostructure channels. A portion of a first internal spacer, perpendicularly adjacent to the nanostructure channel, and A portion of a second internal spacer is perpendicularly adjacent to the nanostructure channel.

7. The semiconductor device as claimed in claim 4, characterized in that, One of the plurality of discontinuous epitaxial regions continuously spans: A portion of a single internal spacer among the plurality of internal spacers, and A portion of one end of a single nanostructure channel among the plurality of nanostructure channels, the portion of that end of the single nanostructure channel being perpendicularly adjacent to the internal spacer.

8. The semiconductor device as claimed in claim 4, characterized in that, One epitaxial region in the plurality of discontinuous epitaxial regions continuously spans: A portion of another single internal spacer among the plurality of internal spacers, wherein this portion of the other single internal spacer is perpendicularly adjacent to the nanostructure channel, and Another part of this endpoint of the nanostructure channel.

9. The semiconductor device as claimed in claim 4, characterized in that, The bottom surface of the source / drain region and the bottom surfaces of a subset of the plurality of internal spacers located at the bottom of the source / drain region are coplanar.

10. A semiconductor device, characterized in that, include: Multiple nanostructured channels are arranged in one direction, which is perpendicular to a semiconductor substrate of the semiconductor device; A gate structure surrounds the plurality of nanostructure channels; A source / drain region, adjacent to one side of the gate structure and adjacent to multiple endpoints of the plurality of nanostructure channels; Multiple internal spacers exist between the source / drain region and the gate structure; as well as Multiple discontinuous epitaxial regions are located between the source / drain region and the multiple nanostructure channels and the multiple internal spacers.

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