An integrated circuit chip and electronic device

Abstract

The application discloses an integrated circuit chip and an electronic device, relates to the technical field of integrated circuits, and innovatively extends a sealing ring located at the peripheral edge of the chip for physical protection to form an isolation belt between a first module and a second module, and uses the sealing ring as a noise isolation structure between the first module and the second module. Since the sealing ring can be formed by alternately stacking strip-shaped connecting holes and strip-shaped metal structures, the noise isolation structure between the first module and the second module can be formed by alternately stacking strip-shaped connecting holes and strip-shaped metal structures, so that the noise influence between the first module and the second module is effectively isolated, and the reliability of the chip is improved. In addition, the sealing ring and the isolation belt are connected to form a continuous whole structure, that is, the sealing ring and the isolation belt are synchronously completed in a process.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an integrated circuit chip and electronic device. Background Technology

[0002] In integrated circuits (ICs), not only do signals themselves generate common-mode interference and differential interference within the signal source, signal lines, and receivers, but signals are also affected by various factors during transmission, such as transmission distance, medium, and obstacles, which may lead to signal attenuation and thus interference. Therefore, to ensure the reliability of signal transmission, corresponding measures need to be taken to reduce or eliminate interference. For example, techniques such as using shielded cables, adding attenuators, and adding filters can be employed. In manufacturing processes, isolation techniques such as Localized Oxidation Separation (LOCOS), Shallow Trench Isolation (STI), and silicon epitaxial layer isolation can be used.

[0003] In integrated circuit layout design, interference between signals can be reduced by placing isolation structures on the layout. In typical CMOS processes, layout engineers usually use pn junction isolation rings for isolation, but this only isolates the substrate and cannot effectively isolate noise between modules. For some modules in integrated circuits with high noise levels, such as oscillators (OSCs), charge pumps (CPs), and amplifiers in analog circuits, how to reduce or eliminate the impact of these noisy modules on other important devices is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] To address the aforementioned technical problems, this application provides an integrated circuit chip and electronic device to reduce or eliminate the impact of noisy modules in the integrated circuit chip on other important components, thereby improving chip reliability.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] In a first aspect, this application provides an integrated circuit chip, comprising:

[0007] Substrate;

[0008] A first module, a second module, and a sealing isolation structure are located on the substrate. The sealing isolation structure includes at least one sealing ring and at least one isolation strip. The sealing ring surrounds the first module and the second module. The isolation strip is located inside the sealing ring and between the first module and the second module. The isolation strip is connected to the sealing ring to form a continuous integral structure.

[0009] The sealing ring includes connecting rings and metal rings that are alternately stacked in a direction away from the substrate. The connecting ring is located between the substrate and the metal ring closest to the substrate, or between two adjacent metal rings.

[0010] The isolation strip includes connecting strips and metal strips that are alternately stacked in a direction away from the substrate. The connecting strips are located between the substrate and the metal strip closest to the substrate, or between two adjacent metal strips.

[0011] Optionally, the sealing and isolation structure includes at least two sealing rings, each of which is arranged in a U-shape;

[0012] The sealed isolation structure includes at least two isolation strips, which are arranged sequentially between the first module and the second module.

[0013] Optionally, the integrated circuit chip further includes a first connection line, which electrically connects the first module and the second module;

[0014] The first connecting line is insulated from the insulating strip, and intersects the insulating strip in a direction perpendicular to the plane of the substrate.

[0015] Optionally, the metal ring furthest from the substrate among the sealing rings is located in the first metal layer;

[0016] The isolation strip includes a first isolation portion and a second isolation portion connected to each other. The metal strip in the first isolation portion that is furthest from the substrate is located in the first metal layer. The metal strip in the second isolation portion that is furthest from the substrate is located in the second metal layer. The second metal layer is located on the side of the first metal layer that is closer to the substrate.

[0017] The first connecting line is located in the first metal layer and crosses the second isolation portion.

[0018] Optionally, the integrated circuit chip further includes a shielding portion located in the first metal layer, and the shielding portion covering at least a portion of the first module;

[0019] The shielding portion has a notch, and the first connecting line is at least partially located within the notch.

[0020] Optionally, the metal ring furthest from the substrate among the sealing rings is located in the first metal layer;

[0021] The isolation strip includes a third isolation portion and a fourth isolation portion connected to each other. The metal strip in the third isolation portion that is furthest from the substrate is located in the second metal layer, and the metal strip in the fourth isolation portion that is furthest from the substrate is located in the third metal layer. The first metal layer, the second metal layer and the third metal layer are arranged in a direction close to the substrate.

[0022] The first connecting line is located in the second metal layer and crosses the fourth isolation section.

[0023] Optionally, the integrated circuit chip further includes a shielding portion located in the first metal layer, the shielding portion covering at least a portion of the first module.

[0024] Optionally, the metal ring furthest from the substrate among the sealing rings is located in the first metal layer;

[0025] The isolation strip includes a first isolation portion and a second isolation portion connected together. The metal strip in the first isolation portion that is furthest from the substrate is located in the first metal layer. The metal strip in the second isolation portion that is furthest from the substrate is located in the second metal layer. The second metal layer is located on the side of the first metal layer that is closer to the substrate. A portion of the first connecting line is located in the first metal layer and crosses the second isolation portion.

[0026] The isolation strip also includes a third isolation portion and a fourth isolation portion connected together. The metal strip in the third isolation portion that is furthest from the substrate is located in the second metal layer, and the metal strip in the fourth isolation portion that is furthest from the substrate is located in the third metal layer. The first metal layer, the second metal layer, and the third metal layer are arranged in a direction close to the substrate. A portion of the first connecting line is located in the second metal layer and crosses the fourth isolation portion.

[0027] Optionally, the shape of the isolation strip matches the shape of the area where the first module is located.

[0028] Optionally, the first module is a noise source module, and the second module is a noise-sensitive module.

[0029] Secondly, this application provides an electronic device including any of the aforementioned integrated circuit chips.

[0030] Compared with existing technologies, the above technical solution has the following advantages:

[0031] The integrated circuit chip provided in this application includes a substrate and a first module, a second module, and a sealing and isolation structure located on the substrate. The sealing and isolation structure includes at least one sealing ring and at least one isolation strip. The sealing ring surrounds the first module and the second module to prevent cracks or delamination during chip dicing, prevent moisture and impurities from entering the internal circuit from the chip edge, and provide electrical isolation between the chip and the external environment. The isolation strip is located inside the sealing ring and between the first module and the second module to provide noise isolation between the first module and the second module. The isolation strip is connected to the sealing ring to form a continuous integral structure. The sealing ring includes connecting rings and metal rings that are alternately stacked in a direction away from the substrate. The connecting ring is located between the substrate and the metal ring closest to the substrate, or between two adjacent metal rings. The isolation strip includes connecting strips and metal strips that are alternately stacked in a direction away from the substrate. The connecting strip is located between the substrate and the metal strip closest to the substrate, or between two adjacent metal strips. That is, both the sealing ring and the isolation strip are formed by alternating stacks of continuous, uninterrupted strip-shaped connecting holes and strip-shaped metal structures. In other words, this application innovatively extends the sealing ring, which provides physical protection at the outer edge of the chip, to form an isolation strip between the first and second modules. This isolation strip serves as a noise isolation structure between the first and second modules, allowing it to be constructed by alternating stacks of strip-shaped connection holes and strip-shaped metal structures. This effectively isolates noise interference between the first and second modules, improving chip reliability. Furthermore, the sealing ring and the isolation strip are connected to form a continuous, integrated structure, meaning they are manufactured synchronously. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the layout of an existing integrated circuit chip;

[0034] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the integrated circuit chip shown;

[0035] Figure 3 This is a schematic diagram of the layout of an integrated circuit chip provided in an embodiment of this application;

[0036] Figure 4 for Figure 3 The diagram shows the structure of the integrated circuit chip along sections AA' and BB'.

[0037] Figure 5 This is a schematic diagram of the layout of another integrated circuit chip provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the layout of another integrated circuit chip provided in an embodiment of this application;

[0039] Figure 7 for Figure 6 The diagram shows the structure of the integrated circuit chip along the CC' section.

[0040] Figure 8 for Figure 6 The diagram shows the structure of the integrated circuit chip along the DD' section.

[0041] Figure 9 This is a schematic diagram of the layout of another integrated circuit chip provided in an embodiment of this application;

[0042] Figure 10 for Figure 9 The diagram shows the structure of the integrated circuit chip along the cross section EE'.

[0043] Figure 11 for Figure 9 The diagram shows the structure of the integrated circuit chip along the FF' section.

[0044] Figure 12 This is a schematic diagram of the layout of another integrated circuit chip provided in an embodiment of this application;

[0045] Figure 13 This is a schematic diagram of the layout of another integrated circuit chip provided in an embodiment of this application;

[0046] Figure 14 This is a schematic diagram of the layout of another integrated circuit chip provided in an embodiment of this application.

[0047] Explanation of reference numerals in the attached figures:

[0048] Noise source module 01; protection ring 02; connecting holes Cont0, Cont1; metal pillar Me0; substrate Sub; first module 10; second module 20; sealing and isolation structure 30; sealing ring 31; isolation strip 32; connecting ring 311; metal ring 312; connecting strip 321; metal strip 322; first connecting line L1; first isolation part 32A; second isolation part 32B; third isolation part 32C; fourth isolation part 32D; through holes VIA1, VIA2, VIA3; metal layers M1, M2, M3, M4; notch K1; shielding part T1; buried oxide layer BOX. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0051] As described in the background section, for some modules in integrated circuits that have a lot of noise, such as oscillators (OSC), charge pumps (CP), amplifiers, etc. in analog circuits, how to reduce or eliminate the impact of these noisy modules on other important devices is a technical problem that urgently needs to be solved by those skilled in the art.

[0052] The inventors discovered that existing technologies typically employ a guard ring around the noise source module inside an integrated circuit chip to achieve noise isolation. Specifically, Figure 1 A schematic diagram of the layout of an existing integrated circuit chip is shown. Figure 2 It shows Figure 1 The schematic diagram of the cross-sectional structure of the integrated circuit chip shown is combined with... Figure 1 and Figure 2 As shown, in existing integrated circuit chips, the protective ring 02 surrounding the noise source module 01 includes multiple discrete connection holes Cont0 and metal pillars Me0. The connection holes Cont0 are located between the substrate Sub and the metal layer M1, and the metal pillars Me0 are located on the metal layer M1. The connection holes Cont0 and the metal pillars Me0 are stacked to achieve noise isolation. It should be noted that... Figure 1 and Figure 2 The noise source module 01 is represented by only one MOS device, and the source region S, drain region D and gate G of the MOS device are not actually electrically connected to each other. The connection holes are not distinguished in the figure only to show that the connection holes are not distinguished. Figure 2In the integrated circuit chip, metal layer M1 is the metal layer closest to the substrate Sub. The integrated circuit chip may also include metal layer M2, metal layer M3, and metal layer M4, etc.

[0053] However, when a protective ring is set around the noise source module inside an integrated circuit chip for noise isolation, the effect of the protective ring on noise isolation of the noise source module is limited because there are gaps between the connection holes and the protective ring is usually only connected to the metal layer (metal layer M1) that is closer to the substrate.

[0054] Furthermore, within integrated circuit chips, the guard ring surrounding the noise source module can only employ multiple discrete vias. This is because: First, the guard ring needs to provide a low-impedance discharge path for the noise current. Multiple discrete vias connected in parallel can significantly reduce the total contact resistance from the substrate to the metal layer M1. Consequently, the noise current will naturally choose all available parallel paths, ensuring rapid and uniform collection and discharge at any point within the guard ring, avoiding excessively high local current density and the generation of "hot spots." Second, during the thermal cycling process of chip manufacturing, mismatches in the coefficients of thermal expansion (CTE) between materials can generate stress. Long, continuous metal or via structures can accumulate and concentrate stress, easily leading to the metal layer peeling off from the insulating layer or cracking. Discrete via arrays, on the other hand, are natural stress-relieving structures that effectively disperse and block stress transmission paths, ensuring the structural integrity and reliability of the guard ring itself. Third, the guard ring is located inside the chip and must adhere to stringent design rules. These rules typically strictly limit the maximum continuous length of metal lines and vias to prevent the aforementioned stress problems. Therefore, designing the guard ring as a discrete array of holes is a necessary requirement to meet electrical performance requirements, thermomechanical stress management, and design rule constraints.

[0055] In view of this, embodiments of this application provide an integrated circuit chip. Figure 3 This illustration shows a layout diagram of an integrated circuit chip according to an embodiment of this application. Figure 4 It shows Figure 3 The diagram shows the structure of the integrated circuit chip along sections AA' and BB', combined with... Figure 3 and Figure 4As shown, the integrated circuit chip includes a substrate Sub and a first module 10, a second module 20, and a sealed isolation structure 30 located on the substrate Sub. The first module 10 can be a noise source module, that is, a module that generates noise. The first module 10 may include an oscillator (OSC), a charge pump (CP), etc. The second module 20 can be a noise-sensitive module. The second module 20 may include a switch (SW), etc. Noise isolation is required between the first module 10 and the second module 20.

[0056] In this embodiment of the application, combined with Figure 3 and Figure 4 As shown, the sealing and isolation structure 30 includes at least one sealing ring 31 and at least one isolation strip 32. The sealing ring 31 surrounds the first module 10 and the second module 20. The isolation strip 32 is located inside the sealing ring 31 and between the first module 10 and the second module 20. The isolation strip 32 is connected to the sealing ring 31 to form a continuous integral structure. The sealing ring 31 includes connecting rings 311 and metal rings 312 that are alternately stacked in a direction away from the substrate Sub. The connecting rings 311 are located between the substrate Sub and the metal ring 312 closest to the substrate Sub, or between two adjacent metal rings 312. The isolation strip 32 includes connecting strips 321 and metal strips 322 that are alternately stacked in a direction away from the substrate Sub. The connecting strips 321 are located between the substrate Sub and the metal strip 322 closest to the substrate Sub, or between two adjacent metal strips 322.

[0057] It is understood that an integrated circuit chip includes a substrate Sub and multiple metal layers located on the substrate Sub. The multiple metal layers are, for example, metal layers M1, M2 and M3 stacked in a direction away from the substrate Sub. The metal ring 312 in the sealing ring 31 is a ring-shaped metal structure located on a certain metal layer. The metal strip 322 in the isolation strip 32 is a strip-shaped metal structure located on a certain metal layer. The connecting ring 311 in the sealing ring 31 and the connecting strip 321 in the isolation strip 32 are connection holes Cont1 between the substrate Sub and the metal layer closest to the substrate Sub (such as metal layer M1), or connection holes between two adjacent metal layers (such as connection holes VIA1 and VIA2). Connection holes between two adjacent metal layers are usually also called vias.

[0058] It is also understandable that in the sealing ring 31, both the connecting ring 311 and the metal ring 312 are annular structures surrounding the first module 10 and the second module 20, and the connecting ring 311 and the metal ring 312 are alternately stacked along the direction away from the substrate Sub, which is equivalent to forming a strong and dense "wall" at the outer edge of the integrated circuit chip. The isolation strip 32 between the first module 10 and the second module 20 adopts the same or similar structure as the sealing ring 31. In the isolation strip 32, both the connecting strip 321 and the metal strip 322 are strip-shaped structures between the first module 10 and the second module 20, and the connecting strip 321 and the metal strip 322 are alternately stacked along the direction away from the substrate Sub. That is to say, both the sealing ring 31 and the isolation strip 32 are formed by the alternating stacking of continuous, uninterrupted strip-shaped connecting holes and strip-shaped metal structures.

[0059] In fact, a sealing ring 31, called a Seal Ring, is usually set on the outer edge of an integrated circuit chip. It is used to prevent cracks or delamination during chip cutting, block moisture and impurities from entering the internal circuit from the chip edge, and provide electrical isolation between the chip and the external environment. This protects the chip from damage caused by the external environment, and can also effectively enhance the electrothermal performance of the chip, reduce the impact of the external environment on the chip's operating temperature, and improve the chip's stability and reliability.

[0060] Unlike the aforementioned guard ring, the core function of a seal ring is mechanical protection. Therefore, using continuous, uninterrupted strip-shaped vias and stacked strip-shaped metal structures creates a robust and dense "wall" around the chip's outer edge, providing maximum mechanical strength and rigidity. Furthermore, seal rings are typically floating or single-point grounded and do not participate in circuit functionality. Therefore, they do not need to consider electrical issues such as contact resistance, current distribution, or potential uniformity, allowing for continuous, uninterrupted stacking of strip-shaped vias and metal structures. Moreover, since the seal ring is located at the chip's outer edge, foundry-specific rules for seal rings allow and even recommend the use of stacked strip-shaped vias and metal structures to optimize mechanical performance. Additionally, the multi-layered stacking of the seal ring from the substrate to the top metal layer is sufficient to withstand thermomechanical stresses.

[0061] Therefore, the integrated circuit chip provided in this application innovatively extends the sealing ring 31, which is physically protected at the outer edge of the chip, to form an isolation strip 32 between the first module 10 and the second module 20. This isolation strip serves as a noise isolation structure between the first module 10 and the second module 20, allowing the noise isolation structure between the first module 10 and the second module 20 to be formed by alternating stacks of strip-shaped connecting holes and strip-shaped metal structures. This effectively isolates the noise influence between the first module 10 and the second module 20, improving chip reliability. Furthermore, the sealing ring 31 and the isolation strip 32 are connected to form a continuous integral structure, meaning that the sealing ring 31 and the isolation strip 32 are completed synchronously in the manufacturing process.

[0062] Optional, such as Figure 3 As shown, the sealing and isolation structure 30 may include a sealing ring 31 and an isolation strip 32, that is, the outer periphery of the first module 10 and the second module 20 is surrounded by a sealing ring 31, and an isolation strip 32 is provided between the first module 10 and the second module 20; alternatively, such as Figure 5 As shown, Figure 5 The diagram shows a layout schematic of another integrated circuit chip provided in an embodiment of this application. The sealing isolation structure 30 may also include at least two sealing rings 31, each sealing ring 31 being arranged in a U-shape so that each sealing ring 31 surrounds the first module 10 and the second module 20. Similarly, the sealing isolation structure 30 may also include at least two isolation strips 32, each isolation strip 32 being arranged sequentially between the first module 10 and the second module 20. The number of sealing rings 31 and isolation strips 32 may be equal or unequal, depending on the specific circumstances.

[0063] Understandably, the sealing isolation structure 30 includes at least two sealing rings 31 arranged in a U-shape, which provides better overall protection for the chip compared to a sealing isolation structure 30 with only one sealing ring 31. Similarly, providing at least two isolation strips 32 between the first module 10 and the second module 20 provides better noise isolation between the first module 10 and the second module 20 compared to providing only one isolation strip 32.

[0064] It should be noted that the sealed isolation structure 30 is grounded, but this application does not limit the specific grounding location of the sealed isolation structure 30.

[0065] Figure 6 This illustration shows a layout diagram of another integrated circuit chip provided in an embodiment of this application, such as... Figure 6As shown, the integrated circuit chip also includes a first connection line L1, which electrically connects the first module 10 and the second module 20 for signal transmission between the first module 10 and the second module 20. Since the sealed isolation structure 30 is grounded, the first connection line L1 is insulated from the isolation strip 32. In the direction perpendicular to the plane of the substrate Sub, the first connection line L1 intersects the isolation strip 32. That is, the first connection line L1 needs to cross or pass through the isolation strip 32 to realize the electrical connection between the first module 10 and the second module 20.

[0066] It is understood that an integrated circuit chip includes a substrate Sub and multiple metal layers located on the substrate Sub. Specifically, the multiple metal layers may include metal layers M1, M2, M3 and M4 stacked in a direction away from the substrate Sub. The first connection line L1 is located in a certain metal layer, and the isolation band 32 needs to make appropriate avoidance to the position of the first connection line L1.

[0067] One possible approach is, such as Figures 6-8 As shown, Figure 7 It shows Figure 6 The diagram shown is a structural schematic of the integrated circuit chip along the CC' section. Figure 8 It shows Figure 6 The schematic diagram of the integrated circuit chip along the DD' section shows that the first connection line L1 can be located in the top metal layer. In this case, the metal strip 322 in the isolation strip 32 located in the top metal layer corresponding to the position of the first connection line L1 needs to be grooved to facilitate the setting of the first connection line L1.

[0068] Specifically, taking a multilayer metal layer on a substrate Sub in an integrated circuit chip, including metal layers M1, M2, M3, and M4 stacked in a direction away from the substrate Sub, as an example, as follows: Figure 7 and Figure 8 As shown, the metal ring 312 furthest from the substrate Sub in the sealing ring 31 is located in the first metal layer (i.e., the top metal layer M4); the isolation strip 32 includes a first isolation portion 32A and a second isolation portion 32B connected to each other. The metal strip 322 furthest from the substrate Sub in the first isolation portion 32A is located in the first metal layer (i.e., the top metal layer M4), and the metal strip 322 furthest from the substrate Sub in the second isolation portion 32A is located in the second metal layer (i.e., the second-to-top metal layer M3). The second metal layer (i.e., the second-to-top metal layer M3) is located on the side of the first metal layer (i.e., the top metal layer M4) closer to the substrate Sub; the first connecting line L1 is located in the first metal layer (i.e., the top metal layer M4) and crosses the second isolation portion 32B.

[0069] In other words, starting from the substrate Sub, the sealing ring 31 is stacked in sequence with the following rings: a connecting ring 311 between the substrate Sub and the metal layer M1 (i.e., an annular connecting hole Cont1 between the substrate Sub and the metal layer M1), a metal ring 312 located in the metal layer M1, a connecting ring 311 between the metal layer M1 and the metal layer M2 (i.e., an annular through hole VIA1 between the metal layer M1 and the metal layer M2), a metal ring 312 located in the metal layer M2, a connecting ring 311 between the metal layer M2 and the metal layer M3 (i.e., an annular through hole VIA2 between the metal layer M2 and the metal layer M3), a metal ring 312 located in the metal layer M3, a connecting ring 311 between the metal layer M3 and the metal layer M4 (i.e., an annular through hole VIA3 between the metal layer M3 and the metal layer M4), and a metal ring 312 located in the metal layer M4.

[0070] Similarly, the first isolation portion 32A in the isolation band 32, starting from the substrate Sub, is sequentially stacked with a connecting band 321 between the substrate Sub and the metal layer M1 (i.e., a strip-shaped connecting hole Cont1 between the substrate Sub and the metal layer M1), a metal band 322 located in the metal layer M1, a connecting band 321 between the metal layer M1 and the metal layer M2 (i.e., a strip-shaped through hole VIA1 between the metal layer M1 and the metal layer M2), a metal band 322 located in the metal layer M2, a connecting band 321 between the metal layer M2 and the metal layer M3 (i.e., a strip-shaped through hole VIA2 between the metal layer M2 and the metal layer M3), a metal band 322 located in the metal layer M3, a connecting band 321 between the metal layer M3 and the metal layer M4 (i.e., a strip-shaped through hole VIA3 between the metal layer M3 and the metal layer M4), and a metal band 322 located in the metal layer M4. However, the second isolation portion 32B corresponding to the first connection line L1 in the isolation band 32 is stacked sequentially from the substrate Sub, including the connection band 321 between the substrate Sub and the metal layer M1 (i.e., the connection hole Cont1 between the substrate Sub and the metal layer M1), the metal band 322 located in the metal layer M1, the connection band 321 between the metal layer M1 and the metal layer M2 (i.e., the through hole VIA1 between the metal layer M1 and the metal layer M2), the metal band 322 located in the metal layer M2, the connection band 321 between the metal layer M2 and the metal layer M3 (i.e., the through hole VIA2 between the metal layer M2 and the metal layer M3), and the metal band 322 located in the metal layer M3; the first connection line L1 is provided on the side of the second isolation portion 32B in the isolation band 32 away from the substrate Sub, that is, the first connection line L1 crosses the second isolation portion 32B in the isolation band 32 to realize the electrical connection between the first module 10 and the second module 20.

[0071] Further optional, such as Figure 6As shown, the integrated circuit chip also includes a shielding part T1, which is located on the first metal layer (i.e., the top metal layer M4). The shielding part T1 covers at least a portion of the first module 10. It is understood that by using the shielding part T1 located on the top metal layer to cover the first module 10 (the noise source module), the outflow of noise signals can be further reduced, providing comprehensive shielding against noise from the first module 10 and further minimizing the impact on other modules. Meanwhile, considering that both the shielding part T1 and the first connecting line L1 are located on the first metal layer (i.e., the top metal layer M4), and that the shielding part T1 is used to cover the first module 10, the shielding part T1 is provided with a notch K1. At least a portion of the first connecting line L1 is located within the notch K1; that is, the shielding part T1 provides a notch at the position of the first connecting line L1 for clearance.

[0072] Another possible approach is, such as Figures 9-11 As shown, Figure 9 This illustration shows a layout diagram of another integrated circuit chip provided in an embodiment of this application. Figure 10 It shows Figure 9 The diagram shown is a structural schematic of the integrated circuit chip along section EE'. Figure 11 It shows Figure 9 The schematic diagram of the integrated circuit chip along the cross section FF' shows that the first connection line L1 may not be located in the top metal layer M4, but may be located in the second-to-top metal layer M3. In this case, the metal strip 322 in the isolation strip 32 located in the same metal layer corresponding to the position of the first connection line L1 needs to be grooved to facilitate the setting of the first connection line L1.

[0073] Specifically, taking a multilayer metal layer on a substrate Sub in an integrated circuit chip, including metal layers M1, M2, M3, and M4 stacked in a direction away from the substrate Sub, as an example, as follows: Figure 9 and Figure 10 As shown, the metal ring 312 furthest from the substrate Sub in the sealing ring 31 is located in the first metal layer (i.e., the top metal layer M4); the isolation strip 32 includes a third isolation portion 32C and a fourth isolation portion 32D connected to each other. The metal strip 322 furthest from the substrate Sub in the third isolation portion 32C is located in the second metal layer (i.e., the second-to-top metal layer M3), and the metal strip 322 furthest from the substrate Sub in the fourth isolation portion 32D is located in the third metal layer (i.e., metal layer M2). The first metal layer (i.e., the top metal layer M4), the second metal layer (i.e., the second-to-top metal layer M3), and the third metal layer (i.e., metal layer M2) are arranged in a direction close to the substrate Sub; the first connecting line L1 is located in the second metal layer (i.e., the second-to-top metal layer M3) and crosses the fourth isolation portion 32D.

[0074] In other words, starting from the substrate Sub, the sealing ring 31 is stacked in sequence with the following rings: a connecting ring 311 between the substrate Sub and the metal layer M1 (i.e., an annular connecting hole Cont1 between the substrate Sub and the metal layer M1), a metal ring 312 located in the metal layer M1, a connecting ring 311 between the metal layer M1 and the metal layer M2 (i.e., an annular through hole VIA1 between the metal layer M1 and the metal layer M2), a metal ring 312 located in the metal layer M2, a connecting ring 311 between the metal layer M2 and the metal layer M3 (i.e., an annular through hole VIA2 between the metal layer M2 and the metal layer M3), a metal ring 312 located in the metal layer M3, a connecting ring 311 between the metal layer M3 and the metal layer M4 (i.e., an annular through hole VIA3 between the metal layer M3 and the metal layer M4), and a metal ring 312 located in the metal layer M4.

[0075] The third isolation section 32C in the isolation band 32, starting from the substrate Sub, consists of a connecting band 321 between the substrate Sub and the metal layer M1 (i.e., a strip-shaped connecting hole Cont1 between the substrate Sub and the metal layer M1), a metal band 322 located in the metal layer M1, a connecting band 321 between the metal layer M1 and the metal layer M2 (i.e., a strip-shaped through hole VIA1 between the metal layer M1 and the metal layer M2), a metal band 322 located in the metal layer M2, a connecting band 321 between the metal layer M2 and the metal layer M3 (i.e., a strip-shaped through hole VIA2 between the metal layer M2 and the metal layer M3), and a metal band 322 located in the metal layer M3. The fourth isolation portion 32D in the isolation band 32, starting from the substrate Sub, consists of a connecting band 321 between the substrate Sub and the metal layer M1 (i.e., a strip-shaped connecting hole Cont1 between the substrate Sub and the metal layer M1), a metal strip 322 located in the metal layer M1, a connecting band 321 between the metal layer M1 and the metal layer M2 (i.e., a strip-shaped through hole VIA1 between the metal layer M1 and the metal layer M2), and a metal strip 322 located in the metal layer M2. A first connecting line L1 is provided on the side of the fourth isolation portion 32D in the isolation band 32 away from the substrate Sub. That is, the first connecting line L1 crosses the fourth isolation portion 32D in the isolation band 32 to realize the electrical connection between the first module 10 and the second module 20.

[0076] Further optional, such as Figure 9As shown, the integrated circuit also includes a shielding portion T1, which is located on the first metal layer (i.e., the top metal layer M4). The shielding portion T1 covers at least a portion of the first module 10. It is understood that by using the shielding portion T1 located on the top metal layer to cover the first module 10 (i.e., the noise source module), the outflow of noise signals can be further reduced, providing comprehensive shielding against noise from the first module 10 and further minimizing the impact on other modules. Furthermore, considering that the first connection line L1 is located on the second metal layer (i.e., the next-top metal layer M3), the shielding portion T1 does not need to have a notch; that is, the shielding portion B1 can completely cover the first module 10.

[0077] Further optional, such as Figures 9-11 As shown, the metal strip 322 of the third isolation part 32C in the isolation strip 32, which is furthest from the substrate Sub, is electrically connected to the shielding part T1. Specifically, it can be electrically connected through the strip-shaped through hole VIA3 between the metal layer M3 and the metal layer M4. Similarly, the metal ring 312 of the sealing ring 31, which is furthest from the substrate Sub, can also be electrically connected to the shielding part T1. With this configuration, the first module 10 (i.e., the noise source module) is completely covered around its perimeter and top, which can further reduce the outflow of noise signals and reduce the impact on other modules.

[0078] Another possible approach is to combine Figure 12 , Figures 7-8 as well as Figures 10-11 As shown, Figure 12 This illustration shows a layout diagram of yet another integrated circuit chip provided in an embodiment of this application. Figure 7 Also for Figure 12 The diagram shown is a structural schematic of the integrated circuit chip along the CC' section. Figure 8 Also for Figure 12 The diagram shown is a structural schematic of the integrated circuit chip along the DD' section. Figure 10 for Figure 12 The diagram shown is a structural schematic of the integrated circuit chip along section EE'. Figure 11 Also for Figure 12 The schematic diagram of the integrated circuit chip along the cross section FF' shows that some of the first connection lines L1 can be located in the top metal layer, and some of the first connection lines L1 can be located in other metal layers, such as the second-to-top metal layer M3. This situation is a combination of the two methods mentioned above.

[0079] Specifically, taking a multilayer metal layer on a substrate Sub in an integrated circuit chip, including metal layers M1, M2, M3, and M4 stacked in a direction away from the substrate Sub, as an example, as follows: Figure 12 , Figures 7-8As shown, the metal ring 312 furthest from the substrate Sub in the sealing ring 31 is located in the first metal layer (i.e., the top metal layer M4); the isolation strip 32 includes a first isolation portion 32A and a second isolation portion 32B connected to each other. The metal strip 322 furthest from the substrate Sub in the first isolation portion 32A is located in the first metal layer (i.e., the top metal layer M4), and the metal strip 322 furthest from the substrate Sub in the second isolation portion 32A is located in the second metal layer (i.e., the second-to-top metal layer M3). The second metal layer (i.e., the second-to-top metal layer M3) is located on the side of the first metal layer (i.e., the top metal layer M4) close to the substrate Sub; a portion of the first connecting line L1 is located in the first metal layer (i.e., the top metal layer M4) and crosses the second isolation portion 32B.

[0080] And, as Figure 12 , Figures 10-11 As shown, the isolation strip 32 also includes a third isolation portion 32C and a fourth isolation portion 32D connected to each other. The metal strip 322 in the third isolation portion 32C that is farthest from the substrate Sub is located in the second metal layer (i.e., the second-to-top metal layer M3). The metal strip 322 in the fourth isolation portion 32D that is farthest from the substrate Sub is located in the third metal layer (i.e., metal layer M2). The first metal layer (i.e., the top metal layer M4), the second metal layer (i.e., the second-to-top metal layer M3), and the third metal layer (i.e., metal layer M2) are arranged in a direction close to the substrate Sub. A portion of the first connecting line L1 is located in the second metal layer (i.e., the second-to-top metal layer M3) and crosses the fourth isolation portion 32D.

[0081] Further optional, such as Figure 12 As shown, the integrated circuit chip also includes a shielding portion T1, which is located on the first metal layer (i.e., the top metal layer M4). The shielding portion T1 covers at least a portion of the first module 10. It is understood that by using the shielding portion T1 located on the top metal layer to cover the first module 10 (the noise source module), the outflow of noise signals can be further reduced, providing comprehensive shielding against noise from the first module 10 and further minimizing the impact on other modules. Meanwhile, considering that both the shielding portion T1 and a portion of the first connecting lines L1 are located on the first metal layer (i.e., the top metal layer M4), and that the shielding portion T1 is used to cover the first module 10, the shielding portion B1 is provided with a notch K1. At least a portion of the first connecting lines L1 is located within the notch K1; that is, the shielding portion B1 provides a notch at the location of a portion of the first connecting lines L1 for clearance.

[0082] Based on any of the above embodiments, it can be understood that in the integrated circuit chip, the shape of the isolation band 32 matches the shape of the area where the first module 10 is located. Optionally, such as Figure 6 , Figure 9 as well as Figure 12 As shown, the isolation strip 32 is straight. Other options include... Figure 13 and Figure 14 As shown, Figure 13 and Figure 14 The diagram shows two more integrated circuit chip layouts provided in the embodiments of this application. The isolation band 32 can also be L-shaped, stepped, or other shapes, as long as it matches the shape of the area where the first module 10 is located.

[0083] It should be noted that in the figures of this application, only one MOS device is used to represent the first module 10 and the second module 20, and the source region S, drain region D and gate G of the MOS device are not actually electrically connected to each other. The figures are not distinguished only to show the connection holes; and the substrate Sub is shown as an SOI substrate, including the buried oxide layer BOX.

[0084] Accordingly, this application also provides an electronic device, which includes the integrated circuit chip provided in any of the above embodiments. Since the specific structure of the integrated circuit chip has been described in detail in the foregoing embodiments, it can be referred to the foregoing embodiments and will not be repeated here.

[0085] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0086] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit chip, characterized in that, include: Substrate; A first module, a second module, and a sealing isolation structure are located on the substrate. The sealing isolation structure includes at least one sealing ring and at least one isolation strip. The sealing ring surrounds the first module and the second module. The isolation strip is located inside the sealing ring and between the first module and the second module. The isolation strip is connected to the sealing ring to form a continuous integral structure. The sealing ring includes connecting rings and metal rings that are alternately stacked in a direction away from the substrate. The connecting ring is located between the substrate and the metal ring closest to the substrate, or between two adjacent metal rings. The isolation strip includes connecting strips and metal strips that are alternately stacked in a direction away from the substrate. The connecting strips are located between the substrate and the metal strip closest to the substrate, or between two adjacent metal strips.

2. The integrated circuit chip according to claim 1, characterized in that, The sealing and isolation structure includes at least two sealing rings, and each sealing ring is arranged in a U-shape. The sealed isolation structure includes at least two isolation strips, which are arranged sequentially between the first module and the second module.

3. The integrated circuit chip according to claim 1, characterized in that, The integrated circuit chip further includes a first connection line, which electrically connects the first module and the second module; The first connecting line is insulated from the insulating strip, and intersects the insulating strip in a direction perpendicular to the plane of the substrate.

4. The integrated circuit chip according to claim 3, characterized in that, The metal ring furthest from the substrate in the sealing ring is located in the first metal layer; The isolation strip includes a first isolation portion and a second isolation portion connected to each other. The metal strip in the first isolation portion that is furthest from the substrate is located in the first metal layer. The metal strip in the second isolation portion that is furthest from the substrate is located in the second metal layer. The second metal layer is located on the side of the first metal layer that is closer to the substrate. The first connecting line is located in the first metal layer and crosses the second isolation portion.

5. The integrated circuit chip according to claim 4, characterized in that, The integrated circuit chip further includes a shielding portion located in the first metal layer and covering at least a portion of the first module; The shielding portion has a notch, and the first connecting line is at least partially located within the notch.

6. The integrated circuit chip according to claim 3, characterized in that, The metal ring furthest from the substrate in the sealing ring is located in the first metal layer; The isolation strip includes a third isolation portion and a fourth isolation portion connected to each other. The metal strip in the third isolation portion that is furthest from the substrate is located in the second metal layer, and the metal strip in the fourth isolation portion that is furthest from the substrate is located in the third metal layer. The first metal layer, the second metal layer and the third metal layer are arranged in a direction close to the substrate. The first connecting line is located in the second metal layer and crosses the fourth isolation section.

7. The integrated circuit chip according to claim 6, characterized in that, The integrated circuit chip further includes a shielding portion located in the first metal layer, which covers at least a portion of the first module.

8. The integrated circuit chip according to claim 3, characterized in that, The metal ring furthest from the substrate in the sealing ring is located in the first metal layer; The isolation strip includes a first isolation portion and a second isolation portion connected together. The metal strip in the first isolation portion that is furthest from the substrate is located in the first metal layer. The metal strip in the second isolation portion that is furthest from the substrate is located in the second metal layer. The second metal layer is located on the side of the first metal layer that is closer to the substrate. A portion of the first connecting line is located in the first metal layer and crosses the second isolation portion. The isolation strip also includes a third isolation portion and a fourth isolation portion connected together. The metal strip in the third isolation portion that is furthest from the substrate is located in the second metal layer, and the metal strip in the fourth isolation portion that is furthest from the substrate is located in the third metal layer. The first metal layer, the second metal layer, and the third metal layer are arranged in a direction close to the substrate. A portion of the first connecting line is located in the second metal layer and crosses the fourth isolation portion.

9. The integrated circuit chip according to any one of claims 1-8, characterized in that, The first module is a noise source module, and the second module is a noise-sensitive module.

10. An electronic device, characterized in that, Includes the integrated circuit chip according to any one of claims 1-9.

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