Image sensor and electronic device

Abstract

The application relates to an image sensor and an electronic device. The image sensor comprises: a pixel region; a logic region located at the periphery of the pixel region; an isolation region located between the pixel region and the logic region; the isolation region comprises a substrate, a trench isolation structure on the substrate, and a conductive plug penetrating through the trench isolation structure along a first direction perpendicular to the top surface of the substrate, the conductive plug being used for connecting a positive bias; wherein a plurality of conductive plugs are distributed in the isolation region along a second direction parallel to the top surface of the substrate. By adding the conductive plug penetrating through the trench isolation structure and connecting the positive bias, a dark current collection ring is formed in the original DPDN epitaxial region, so that the problem of pixel edge bright edges caused by the diffusion of photoelectrons into the adjacent pixel region at this position is avoided.

Description

Technical Field

[0001] This application relates to the field of optoelectronic equipment technology, and in particular to an image sensor and electronic device. Background Technology

[0002] A complementary metal-oxide-semiconductor (CMOS) image sensor is a device that converts optical signals into reliable electrical signals and outputs them through a readout circuit. It consists of a two-dimensional pixel array, row selection circuitry, column-level circuitry, readout circuitry, bias circuitry, and other components. Currently, CIS image sensors are widely used in consumer electronics, industrial inspection, medical, and aerospace fields.

[0003] However, in conventional chip structures, due to process deviations during fabrication or insufficient shallow trench isolation (STI) performance between logic and pixel regions, parasitic photoelectron enrichment regions often form near the boundary between the two regions, causing a significant increase in dark current and resulting in bright edges. Ultimately, this has a direct negative impact on the performance and imaging quality of the image sensor. Utility Model Content

[0004] Therefore, it is necessary to provide an image sensor and electronic device that addresses the problems mentioned above in the background technology, at least reducing the risk of bright edges caused by increased dark current at the interface.

[0005] To address the aforementioned technical problems and other issues, according to some embodiments, one aspect of this application provides an image sensor, comprising: a pixel region; a logic region located around the pixel region; and an isolation region located between the pixel region and the logic region. The isolation region includes a substrate, a trench isolation structure, and conductive plugs located on the substrate. The conductive plugs penetrate the trench isolation structure along a first direction perpendicular to the top surface of the substrate, and are used to connect a positive bias voltage. A plurality of conductive plugs are spaced apart within the isolation region along a second direction parallel to the top surface of the substrate; the second direction is perpendicular to the first direction.

[0006] In the image sensor described above, the conductive plug located in the isolation region extends through the trench isolation structure into the substrate. When the CIS image sensor is working normally, a positive voltage is applied to the conductive plug. The photoelectrons generated in the isolation region are subjected to the electric field force and move directionally toward the conductive plug, reducing the recombination rate of carriers in the region. This effectively suppresses the generation of dark current in the region and reduces the risk of bright edges on pixels.

[0007] In some embodiments, a logic region surrounds a pixel region; an isolation region surrounds the logic region; the image sensor further includes: a plurality of conductive plugs spaced apart in the isolation region along a third direction parallel to the top surface of the substrate; the third direction is perpendicular to the second direction.

[0008] In the image sensor described in the above embodiments, the conductive plugs are spaced apart at the boundary between the pixel area and the logic area. After a positive bias is applied, they collect photoelectrons that diffuse from the logic area into the isolation area, thus playing a role in synergistic isolation and enhancing the isolation effect of the trench isolation structure.

[0009] In some embodiments, a logic region circumferentially surrounds a pixel region; an isolation region circumferentially surrounds the logic region; an isolation region extending along a second direction includes a plurality of conductive plugs spaced apart along the second direction; an isolation region extending along a third direction includes a plurality of conductive plugs spaced apart along the third direction.

[0010] In the image sensor described in the above embodiments, conductive plugs are distributed circumferentially around the pixel area, forming a dark current collection ring within the original isolation area. This ensures that the photoelectron collection area within the isolation area covers the entire chip structure, maximizing the suppression of bright edges at the pixel area edges.

[0011] In some embodiments, the top surface shape of the conductive plug is selected from rectangles, circles, ellipses, polygons, and combinations thereof.

[0012] In the image sensor described above, since conductive plugs of different shapes have different charge collection efficiencies, structural compatibility, space occupation, and electric field distributions, dark current suppression can be achieved more effectively by setting conductive plugs of corresponding shapes.

[0013] In some embodiments, adjacent conductive plugs along the second direction have the same spacing; and adjacent conductive plugs along the third direction have the same spacing.

[0014] In the image sensor of the above embodiments, by uniformly arranging conductive plugs, the electric fields cooperate with each other to form a regular electric field network in a large area, thereby further improving the photoelectron collection efficiency.

[0015] In some embodiments, the substrate of the isolation region includes an epitaxial layer and an epitaxial portion arranged sequentially along a first direction; the epitaxial portion is an extension of the N-type well region of a photodiode; the epitaxial layer is located between the epitaxial layer and the trench isolation structure; and the conductive plug extends to the epitaxial portion along the first direction.

[0016] In the image sensor of the above embodiments, the conductive plug extends through the trench isolation structure to the epitaxial portion. The conductive plug, which is in direct contact with the epitaxial portion, can clear the photoelectron enrichment area in the epitaxial portion and improve the bright edge problem caused by the photoelectron enrichment area.

[0017] In some embodiments, the length of the trench isolation structure along the third direction is greater than the length of the isolation zone along the third direction.

[0018] In the image sensor described above, by appropriately increasing the width of the trench isolation structure, the lateral diffusion of photoelectrons is effectively blocked, reducing the probability of photoelectrons crossing from the logic area to the pixel area, thereby reducing edge dark current and bright edge problems caused by photoelectron diffusion.

[0019] In some embodiments, the bottom surface of the conductive plug is located inside the top surface of the extension portion.

[0020] In some embodiments, the top surface of the conductive plug is located within the isolation zone.

[0021] In the image sensor of the above embodiments, the position of the conductive plug and its size along the second direction are restricted and defined to avoid the conductive plug area being too large and affecting the pixel size when the spacing is constant.

[0022] Another aspect of this application provides an electronic device including the image sensor of any of the above embodiments.

[0023] The electronic devices described in the above embodiments, by configuring the image sensor of any of the above embodiments, effectively solve the image quality problems caused by bright edges and the problems of abnormal brightness in edge areas and loss of image details, improve the detection accuracy of light signals by the electronic devices, and ensure the accuracy and integrity of images. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a top view of the chip structure of an image sensor in the prior art;

[0026] Figure 2 This is a schematic diagram of the cross-sectional shape of a chip structure for an image sensor in the prior art;

[0027] Figure 3 This is a schematic diagram of the cross-sectional shape of a traditional image sensor chip structure;

[0028] Figure 4 This is a top view of the chip structure of a traditional image sensor;

[0029] Figure 5 This is a cross-sectional schematic diagram of the chip structure of an image sensor provided in one embodiment of this application;

[0030] Figure 6This is a top view schematic diagram of the chip structure of an image sensor provided in one embodiment of this application.

[0031] Explanation of reference numerals in the attached figures:

[0032] 10. Substrate; 20. Trench isolation structure; 30. Backside isolation structure; 40. Implantation isolation structure; 41. PDW; 42. PPW; 51. First DPDN; 52. Second DPDN; 53. PDN; 60. Epitaxial portion; 70. Conductive plug. Detailed Implementation

[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0036] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0037] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0038] In this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and third directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). For example, the pixel unit arrangement direction is the first direction, and the plane in which the substrate lies can be determined based on the first and third directions. The first, second, and third directions may be mutually perpendicular. In this embodiment, the first direction is defined as the Z-axis direction, the second direction as the Y-axis direction, and the third direction as the X-axis direction.

[0039] Based on regional functions, the chip structure can be mainly divided into pixel area and logic area. The pixel area is located in the center of the chip and is responsible for collecting light signals, while the logic area is distributed around the pixel area and is responsible for data processing and device driving. The two areas are isolated by a trench isolation structure.

[0040] However, in conventional chip structures, such as Figure 1 As shown, the deep photodiode N-type well (DPDN) within the pixel region extends outward by one pixel, forming a photoelectron-rich region near the boundary between the pixel region and the logic region. This leads to increased dark current at the edge, causing a bright edge problem. Additionally, as... Figure 2 As shown, during the operation of the peripheral circuit, if the trench isolation structure is insufficient to separate the two, photoelectrons generated in the logic area can diffuse across the trench isolation structure into the pixel area, interfering with the photoelectric signal conversion and transmission process. This can also cause bright edges at the pixel area, resulting in image distortion. Please refer to... Figure 3 , Figure 3 This is a cross-sectional schematic diagram of an existing image sensor chip structure. Figure 4 Figure 6 shows a top view of the chip structure of an image sensor in the prior art. Figure (a) is a top view of a partial structure of the chip, and Figure (b) is a top view of the overall structure of the chip. As shown in the figure, as mentioned above, the first DPDN in the pixel area extends out by one pixel. The epitaxial part 60 forms a photoelectron enrichment area near the boundary between the pixel area and the logic area, which leads to an increase in dark current at the edge and causes the bright edge problem.

[0041] The current conventional method to address the bright edge problem caused by the epitaxial portion of the N-type deep well of the photodiode is to change the photolithography mask and shrink the first DPDN into the pixel area. However, this method not only increases the fabrication cycle and cost of the image sensor, but also cannot avoid the bright edge problem caused by photoelectrons generated in the logic area diffusing into the pixel area across the trench isolation structure when the isolation capability of the trench isolation structure 20 is insufficient.

[0042] It should be noted that, for ease of understanding, this application simplifies the pixel unit structure arranged within the pixel area, showing only the internal structure of pixel unit 1 closest to the isolation area. Of course, Figure 3 The given cross-sectional schematic diagram of the chip structure is only one example. Other suitable examples of the cross-sectional schematic diagram of the chip structure may also exist, and this application does not impose any restrictions on them.

[0043] Based on this, one aspect of this application provides an image sensor, which includes: a pixel area; a logic area located around the pixel area; and an isolation area located between the pixel area and the logic area. The isolation area includes a substrate, a trench isolation structure 20 and a conductive plug 70 located on the substrate. The conductive plug 70 penetrates the trench isolation structure 20 along the OZ direction perpendicular to the top surface of the substrate and is used to connect a positive bias voltage. A plurality of conductive plugs 70 are spaced apart in the isolation area along the OY direction parallel to the top surface of the substrate 10.

[0044] Specifically, the image sensor chip structure mentioned in this application is similar to the image sensor chip structure in the prior art.

[0045] Please see Figure 5 The pixel region includes multiple pixel units distributed sequentially along the OY direction. The pixel unit 1 also includes P-type deep wells (PDW) and P-type pocket wells (PPW) arranged along the ZO direction (opposite to the OZ direction), as well as a trench isolation structure 20 located on one side of the pixel region, extending through the first plane into the first plane and distributed at intervals along the OY direction, and a back isolation structure 30 extending into the PDW 41 along the ZO direction through the second plane.

[0046] For example, the trench isolation structure 20 and the back-side isolation structure 30 are used to isolate electrons and light energy. The cross-sectional shape along the OY direction can include a regular trapezoid, an inverted trapezoid, a rectangle, etc., or a combination of regular trapezoids, inverted trapezoids, rectangles, etc. In this embodiment of the application, the trench isolation structure only needs to be able to isolate electrons and light energy, and there is no specific limitation on the shape.

[0047] Specifically, the trench isolation structure 20 and the back isolation structure 30 in the pixel unit 1 are filled with materials such as non-polar oxide, which can effectively reflect the light at the interface of adjacent pixels and reduce optical crosstalk. The PPW 42 and PDW 41 located on both sides of the N region of the photodiode constitute the injection isolation structure 40, which forms an inversion layer with the substrate 10, making it difficult for photogenerated carriers to cross, thereby reducing electrical crosstalk.

[0048] Please continue reading. Figure 5 The pixel unit 1 also includes a first N-type deep well (DPDN), a second N-type deep well (DPDN), an N-type well (PDN), and a P-type well (PDP) arranged along the ZO direction between adjacent PPW 42 and PDW 41 to form the N region of the photodiode.

[0049] In the above photodiode structure, the doping concentrations in the first DPDN 51, the second DPDN 52, and the PDN 53 are different. With the light-receiving surface unchanged, the N-region with the change in concentration gradient can improve the overall capacitance and extend the depletion region as far as possible towards the photon incident side, so as to better collect signal electrons. It should be noted that the conductivity type of the substrate 10 mentioned in this application is P-type. If the conductivity type of the substrate 10 is N-type, then the conductivity type of the above doped regions is the opposite of that in this embodiment.

[0050] Please continue reading. Figure 5 The logic region is located outside the pixel region and includes row selection circuits, bias circuits, column-level circuits, readout circuits, etc. (not shown). The isolation region is located between the pixel region and the logic region and includes a trench isolation structure 20 extending from the first surface to the inner substrate 10 of the first surface.

[0051] In an optional embodiment, the logic region surrounds the pixel region;

[0052] The isolation zone surrounds the logic zone;

[0053] The image sensor also includes a plurality of conductive plugs 70 spaced apart in the isolation region along the OX direction parallel to the top surface of the substrate 10.

[0054] Furthermore, in an optional embodiment, the logic region circumferentially surrounds the pixel region;

[0055] The isolation zone surrounds the logic area.

[0056] The isolation zone extending along the OY direction includes multiple conductive plugs 70 spaced apart along the OY direction.

[0057] The isolation zone extending along the OX direction includes multiple conductive plugs 70 spaced apart along the OX direction.

[0058] Specifically, please refer to Figure 6 In image sensors, Figure 6 (a) is a top view of a partial chip structure of an image sensor provided in one embodiment of this application. Figure 6 (b) is a top view of the overall chip structure of the image sensor provided in one embodiment of this application. Figure 6 The chip structure shown in (a) consists of Figure 5 The local chip structure shown extends along the OX direction, and multiple conductive plugs 70 are spaced apart in the isolation region along the OX direction parallel to the top surface of the substrate 10. Figure 6 (b) includes multiple such as Figure 6 (a) shows a local chip structure in which the pixel area is located at the center of the chip structure and the isolation area surrounds the pixel area. The conductive plugs 70 distributed in the isolation area surround the pixel area to form a dark current collection ring, thereby avoiding the diffusion of photoelectrons into the adjacent pixel area and causing the bright edge problem of the pixel, thus transforming the problem into an active pixel edge dark current isolation method.

[0059] In an alternative embodiment, the top surface shape of the conductive plug 70 is selected from rectangles, circles, ellipses, polygons, and combinations thereof.

[0060] The top surface shape of the conductive plug 70 represents the cross-sectional shape of the first surface of the conductive plug 70 in the plane formed by the OX and OY directions. Since conductive plugs 70 of different shapes have different charge collection efficiencies, structural compatibility, space occupation and electric field distribution, dark current suppression can be achieved more effectively by setting conductive plugs 70 of corresponding shapes.

[0061] For example, the top surface shape of the conductive plug is selected from rectangles or polygons.

[0062] Prismatic conductive plugs, due to their angular shape, exhibit electric field distortion at the corners, which can enhance the collection of photoelectrons from specific directions in certain situations. For example, when photoelectrons primarily diffuse from a particular direction (e.g., due to pixel layout causing photoelectrons to tend to diffuse from one side), the corners of the prismatic conductive plug can act as "guide slots," directing photoelectrons to rapidly accumulate within the plug along the stronger electric field lines at the corners, thereby improving photoelectron collection efficiency in that direction.

[0063] However, there may be a risk of tip discharge at the corners of conductive plugs. Optimizing the shape of conductive plugs and avoiding overly sharp prismatic shapes, and adopting a more rounded or smooth transition design, can reduce the accumulation of charge at the tips and lower the risk of tip discharge.

[0064] For example, the top surface shape of the conductive plug is selected from a circle or an ellipse.

[0065] Cylindrical conductive plugs exhibit a relatively symmetrical electric field distribution when collecting photoelectrons. Ideally, after applying a positive voltage, the electric field strength around the sides and bottom of the cylinder can uniformly drive photoelectrons towards the plug. This shape offers high photoelectron collection efficiency for areas directly below and around the plug. For example, in some small, high-pixel-density image sensors, cylindrical conductive plugs can effectively collect photoelectrons generated in nearby isolation areas because their electric field covers a relatively small but concentrated area, facilitating precise collection of localized photoelectrons and reducing dark current.

[0066] Please continue reading. Figure 6 In an optional embodiment, adjacent conductive plugs 70 along the OY direction have the same spacing; and adjacent conductive plugs 70 along the OX direction have the same spacing.

[0067] It should be noted that the charge collection capability of the conductive plugs 70 is related to the equivalence of the spacing between adjacent conductive plugs 70. Specifically, the center lines of the conductive plugs 70 in the OY or OX directions are on the same straight line. If the spacing between adjacent conductive plugs 70 is too large, some photoelectrons will be difficult to collect, and photoelectrons are prone to recombination in uncollected areas, generating dark current. If the spacing is too small, the electric field distribution will be uneven, and the abnormal movement of photoelectrons due to electric field interference will increase dark current. In addition, the spacing is also related to the pixel size and resolution. Therefore, the specific spacing value can be set according to the actual situation, and this embodiment does not limit it.

[0068] Please continue reading. Figure 5 In an optional embodiment, the substrate 10 of the isolation region includes an epitaxial layer and an epitaxial portion 60 arranged sequentially along a first direction; the epitaxial portion 60 is an extension of the N-type well region (first DPDN 51) of a photodiode; the epitaxial layer is located between the epitaxial layer and the trench isolation structure 20; and the conductive plug 70 extends along the OZ to the epitaxial portion 60.

[0069] As an example, substrate 10 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 10 can be a single-layer structure or a multi-layer structure. For example, substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 10 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 10 should not limit the scope of protection of this disclosure. The conductivity type and material of the epitaxial layer may be the same as or different from that of the substrate, as this is well known to those skilled in the art, and will not be described in detail here.

[0070] The materials for conductive plugs can include, but are not limited to, metals such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0071] Specifically, the conductive plug 70 is used to connect a positive bias voltage. The conductive plug 70 with the applied positive bias voltage can form an appropriate electric field within the isolation region. When the image sensor begins exposure, the pixel area, isolation region, and logic region all generate a certain amount of photoelectrons through the photoelectric effect. In particular, a photoelectron-rich region is formed in the epitaxial portion 60 inside the pixel area and isolation region. The light signal in the pixel area is read out by the circuit in the logic region to form an effective electrical signal. The photoelectrons that diffuse from the logic region into the isolation region and epitaxial portion 60 are collected by the conductive plug 70, reducing the probability of photoelectrons outside the pixel area crossing the isolation region, thereby reducing edge dark current and bright edge problems caused by photoelectron diffusion.

[0072] Please continue reading. Figure 6 In one optional embodiment, the length of the trench isolation structure 20 along the OX direction is greater than the length of the isolation area along the OX direction.

[0073] Specifically, the trench isolation structure surrounds the isolation area 20 circumferentially to isolate the pixel area and logic area, preventing electrical crosstalk. The width of the trench isolation structure must meet the minimum dimensions of the design.

[0074] Please continue reading. Figure 5 In an optional embodiment, the bottom surface of the conductive plug 70 is located inside the top surface of the extension portion.

[0075] Please continue reading. Figure 5 In an optional embodiment, the top surface of the conductive plug 70 is located within the isolation zone.

[0076] Specifically, the conductive plug 70 is disposed within the isolation region, and its dimension along the OY direction is smaller than that of the isolation region along the OY direction. In high-resolution image sensors, pixel sizes are typically small. If the pixel size is very small, the area of ​​the conductive plug needs to be reduced accordingly to accommodate the limited space of the isolation region; for low-resolution image sensors with large pixel sizes, the area of ​​the conductive plug can be appropriately increased. This allows for more effective collection of photoelectrons, reduces dark current, and improves image quality.

[0077] Please see Figure 6 Another aspect of this application provides an electronic device including the image sensor described in the above embodiments.

[0078] The image sensor and electronic device provided in this application have the following unexpected technical effects:

[0079] The image sensor provided in this application forms a dark current collection ring around the pixel area by setting a conductive plug through a trench isolation structure at the boundary between the pixel area and the logic area. This dark current collection ring can form a regular electric field network over a large area, causing photoelectrons in non-pixel areas to be driven by the electric field and flow to the conductive plug, thereby clearing photoelectron-rich areas. Furthermore, this dark current collection ring can be combined with the trench isolation structure for synergistic isolation, effectively enhancing the isolation effect, limiting the lateral diffusion of photoelectrons, and reducing edge dark current.

[0080] Therefore, this image sensor chip structure can improve the original image sensor chip structure without adding too many process steps, realize the directional movement of photoelectrons in non-pixel areas, effectively reduce dark current near pixel edges, and avoid the problem of bright pixel edges.

[0081] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0082] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An image sensor, characterized in that, include: Pixel area; The logical region is located outside the pixel region; An isolation zone is located between the pixel area and the logical area; The isolation region includes a substrate, a trench isolation structure and a conductive plug located on the substrate, the conductive plug penetrating the trench isolation structure along a first direction perpendicular to the top surface of the substrate, and the conductive plug being used to connect a positive bias voltage; The plurality of conductive plugs are spaced apart in the isolation region along a second direction parallel to the top surface of the substrate; the second direction is perpendicular to the first direction.

2. The image sensor according to claim 1, characterized in that, The logical region surrounds the pixel region; The isolation zone surrounds the logic zone; The image sensor further includes: a plurality of conductive plugs spaced apart in the isolation region along a third direction parallel to the top surface of the substrate; The third direction is perpendicular to the second direction.

3. The image sensor according to claim 2, characterized in that, The logical region surrounds the pixel region circumferentially; The isolation zone surrounds the logic zone circumferentially; The isolation zone extending along the second direction includes a plurality of conductive plugs spaced apart along the second direction; The isolation zone extending along the third direction includes a plurality of conductive plugs spaced apart along the third direction.

4. The image sensor according to any one of claims 1-3, characterized in that, The top surface shape of the conductive plug is selected from rectangles, circles, ellipses, polygons, and combinations thereof.

5. The image sensor according to claim 2 or 3, characterized in that, The spacing between adjacent conductive plugs along the second direction is the same; and The spacing between adjacent conductive plugs along the third direction is the same.

6. The image sensor according to any one of claims 1-3, characterized in that, The substrate of the isolation region includes an epitaxial layer and an epitaxial portion arranged sequentially along the first direction; the epitaxial portion is an extension of the N-type well region of a photodiode. The epitaxial layer is located between the epitaxial layer and the trench isolation structure; The conductive plug extends along the first direction to the outer portion.

7. The image sensor according to claim 2 or 3, characterized in that, The length of the trench isolation structure along the third direction is greater than the length of the isolation zone along the third direction.

8. The image sensor according to claim 6, characterized in that, The bottom surface of the conductive plug is located inside the top surface of the extension portion.

9. The image sensor according to any one of claims 1-3, characterized in that, The top surface of the conductive plug is located within the isolation zone.

10. An electronic device, characterized in that, Includes the image sensor according to any one of claims 1-9.

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