Packaging structure for improving yield of vertical chip eutectic and high-power light source

Abstract

The utility model discloses a kind of packaging structure and high-power light source for improving vertical chip eutectic yield, it is related to light source technical field, including ceramic substrate and vertical chip, ceramic substrate includes first electrode area and second electrode area of interval arrangement, the surface of first electrode area is equipped with exhaust structure;Vertical chip is fixed in the first electrode area by eutectic solder layer, and is connected with the second electrode area;Wherein, the exhaust structure is equipped in the lower side of the vertical chip, and at least part extends to the outside of the vertical chip.The utility model provides effective discharge passage for volatile gas generated in the eutectic welding process by setting exhaust structure located in the lower side of vertical chip and extending to its outside on the surface of first electrode area.The structure can timely release the gas pressure accumulated below chip, fundamentally suppresses the phenomenon that chip is offset when welding, to significantly improve the yield of packaging production.

Description

Technical Field

[0001] This utility model relates to the field of light source technology, and in particular to a packaging structure and a high-power light source for improving the yield of vertical chip eutectic bonding. Background Technology

[0002] High-power light source devices typically use aluminum nitride ceramic substrates as carriers, on which vertically structured chips are bonded using silver paste. The front electrodes of the chip are connected to the circuit area at the other end of the substrate via gold wire bonding to achieve electrical conduction. After phosphor film coating and ball-end encapsulation, the LED chip is finally manufactured. In this manufacturing process, the method of fixing the vertical chip to the substrate has a critical impact on the device's performance and reliability. While the currently widely used silver paste die bonding process achieves a certain degree of mechanical connection and electrical conduction, several technical limitations have gradually emerged in practical applications. Due to the fluidity of the silver paste itself, sputtering is prone to occur during dispensing and mounting, leading to paste contamination of the substrate surface and even the chip electrodes. This not only affects the device's appearance quality but may also cause degradation of the chip's electrical performance or even leakage failure. Furthermore, as an adhesive medium, silver paste has limited thermal conductivity, making it difficult to meet the stringent heat dissipation requirements of high-power chips operating under high current conditions. Long-term use carries the risk of reliability degradation due to insufficient thermal management.

[0003] To improve heat dissipation and connection reliability, the industry has been exploring the use of eutectic bonding to replace silver paste bonding. Eutectic bonding achieves the connection between the chip and the substrate by forming an intermetallic compound, offering superior thermal conductivity and mechanical strength. However, new technical challenges have arisen when applying the eutectic process to the assembly of vertical chips with ordinary ceramic substrates. During the eutectic process, the gases generated by the evaporation of flux cannot be expelled in time, easily accumulating between the chip and the substrate and creating localized pressure. This causes the chip to shift at the molten solder interface, severely impacting welding alignment accuracy and product yield. Utility Model Content

[0004] The technical problem to be solved by this utility model embodiment is: how to effectively prevent the chip from shifting during the welding process when using eutectic bonding to fix the vertical chip and the ceramic substrate, thereby ensuring the packaging yield and device reliability.

[0005] To address the aforementioned problems, in a first aspect, this utility model proposes a packaging structure to improve the yield of vertical chip eutectic bonding, comprising:

[0006] A ceramic substrate includes a first electrode region and a second electrode region spaced apart, and the surface of the first electrode region is provided with an exhaust structure.

[0007] A vertical chip is fixed to the first electrode region by a eutectic bonding layer and connected to the second electrode region; wherein the venting structure is located on the lower side of the vertical chip and extends at least partially to the outer side of the vertical chip.

[0008] A further technical solution is that the exhaust structure includes multiple interconnected exhaust channels, with at least one exhaust channel extending to the outside of the vertical chip.

[0009] A further technical solution is that multiple exhaust grooves are evenly distributed on the lower side of the vertical chip.

[0010] A further technical solution is that at least one exhaust groove is connected to the gap between the first electrode region and the second electrode region.

[0011] A further technical solution involves evenly distributing flux dots among multiple venting grooves.

[0012] A further technical solution is that the vertical chip is connected to the second electrode region via gold wires.

[0013] A further technical solution is that the ceramic substrate is made of aluminum nitride.

[0014] Secondly, this utility model embodiment proposes a high-power light source, including the packaging structure described in the first aspect for improving the eutectic yield of vertical chips.

[0015] Compared with the prior art, the technical effects achieved by the embodiments of this utility model include:

[0016] This invention provides a packaging structure for improving the eutectic bonding yield of vertical chips. The structure includes a ceramic substrate and a vertical chip. The ceramic substrate includes a first electrode region and a second electrode region spaced apart. An exhaust structure is provided on the surface of the first electrode region. The vertical chip is fixed to the first electrode region by a eutectic bonding layer and connected to the second electrode region. The exhaust structure is located on the underside of the vertical chip and extends at least partially to its outer side. This invention provides an effective exhaust channel for volatile gases generated during eutectic bonding by providing an exhaust structure on the surface of the first electrode region located on the underside of the vertical chip and extending to its outer side. This structure can promptly release the gas pressure accumulated under the chip, fundamentally suppressing chip misalignment during bonding, thereby significantly improving the yield of packaging production. Simultaneously, the stable bonding position ensures the integrity and uniformity of the eutectic bonding layer, enhances interface thermal conductivity, and thus improves the reliability and long-term service life of the device. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This is a schematic diagram of a packaging structure for improving the yield of vertical chip eutectic bonding, as proposed in an embodiment of this utility model.

[0021] Figure 2 This is a schematic diagram of the packaging structure for improving the eutectic yield of vertical chips proposed in this embodiment of the present invention before the vertical chips are arranged.

[0022] Figure Labels

[0023] First electrode area 10, second electrode area 20, vertical chip 30, venting groove 40, flux dots 50, gold wire 60. Detailed Implementation

[0024] The technical solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of this utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0025] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used in this specification of embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the present invention. As used in this specification of embodiments of the present invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0027] See Figures 1-2 This utility model embodiment proposes a packaging structure to improve the eutectic yield of the vertical chip 30, including a ceramic substrate and the vertical chip 30, the specific structure of which is described below:

[0028] The ceramic substrate includes a first electrode region 10 and a second electrode region 20 spaced apart. The surface of the first electrode region 10 is provided with an exhaust structure. Specifically, the first electrode region 10 is the negative electrode and the second electrode region 20 is the positive electrode, or vice versa; this invention does not specifically limit the type of electrode region. A vertical chip 30 is fixed to the first electrode region 10 via a eutectic bonding layer and connected to the second electrode region 20. The exhaust structure is located on the underside of the vertical chip 30 and at least partially extends to the outer side of the vertical chip 30.

[0029] In specific implementation, by setting an exhaust structure on the surface of the first electrode region 10, located below the vertical chip 30 and extending at least partially to its outer side, an effective structural basis is provided for solving the chip misalignment problem during eutectic bonding. During eutectic bonding, if the gases emitted by the flux and solder due to heat cannot dissipate in time, they will accumulate in the enclosed space between the chip and the substrate, forming localized high pressure. This will disturb the solder interface that has not yet fully solidified, directly causing chip displacement.

[0030] The exhaust structure in this design, by its placement on the underside of the chip, provides an initial collection and guidance channel for these volatile gases; its design, extending at least partially to the outside of the chip, ensures that the gases have a clear and unobstructed exit path to the external environment. This allows internal gases to be continuously and smoothly discharged before the pressure accumulates to a dangerous level, thus significantly weakening the fundamental driving force that causes chip displacement. With an unobstructed gas exhaust path, the chip can stably maintain its preset position during the eutectic bonding process, forming a precisely positioned and reliably connected eutectic solder layer with the substrate. This not only directly improves the first-pass yield of the packaging process, but also enhances the heat transfer efficiency from the chip to the substrate due to the improved accuracy of the soldering position and interface integrity, reducing the risk of increased thermal resistance and localized overheating caused by poor soldering.

[0031] In some preferred embodiments, the exhaust structure includes a plurality of interconnected exhaust channels 40, at least one exhaust channel 40 extending to the outside of the vertical chip 30.

[0032] In practice, multiple exhaust channels 40 form a more widely distributed exhaust network beneath the chip. Compared to a single or non-connected exhaust structure, this allows for the capture and collection of generated gases over a larger area. In particular, the interconnected nature of the network enables gas to flow and redistribute within the channels, significantly enhancing the robustness and reliability of the exhaust system.

[0033] Furthermore, since at least one exhaust channel 40 extends to the outside of the chip, it ensures that there is at least one definite connection point between the interconnected network of channels and the external environment, providing a final pressure relief channel for the internally collected gas. Therefore, this embodiment provides an efficient, reliable, and interference-resistant gas exhaust network, further consolidating and enhancing the ability to prevent chip misalignment, resulting in a wider process window and more stable yield in the eutectic process.

[0034] In some preferred embodiments, a plurality of exhaust grooves 40 are evenly distributed on the lower side of the vertical chip 30.

[0035] In practice, by evenly arranging multiple exhaust channels 40 on the underside of the chip, an exhaust channel inlet can be found nearby regardless of where the gas is generated under the chip. This design ensures the balance of gas exhaust force, avoiding chip tilting caused by local high-pressure areas. This allows the chip to descend smoothly and horizontally during the soldering process and contact the substrate, thereby forming a eutectic solder layer with uniform thickness and reasonable stress distribution. This not only prevents visible misalignment but also suppresses problems such as solder voids and increased thermal resistance caused by microscopic tilting, ultimately achieving higher consistency and better soldering quality.

[0036] In some preferred embodiments, at least one venting groove 40 is connected to the gap between the first electrode region 10 and the second electrode region 20.

[0037] In this specific implementation, at least one exhaust channel 40 is connected to the gap between the first electrode region 10 and the second electrode region 20, cleverly utilizing existing physical features of the packaging structure to enhance exhaust efficiency. The gap between the first electrode region 10 and the second electrode region 20 is typically an inherent physical separation area on the substrate for electrical isolation. Incorporating this gap as part of the exhaust system effectively provides a ready-made "highway" for the internal gas to access a wider space. When the exhaust channel 40 is connected to this gap, the gas no longer relies solely on slow diffusion towards the lateral edges of the chip; instead, it can rapidly enter this relatively spacious gap area through the channel and then be released from the gap to the external environment. This significantly shortens the gas exhaust path, reduces flow resistance, and thus enables faster pressure reduction beneath the chip. This embodiment, by optimizing the exhaust path, improves the gas exhaust speed and efficiency, further accelerating the pressure equalization process, thereby effectively suppressing chip misalignment even in a shorter process time.

[0038] In some preferred embodiments, flux dots 50 are evenly distributed among the plurality of venting grooves 40.

[0039] In practical implementation, during eutectic bonding, the flux plays a role in removing oxides from the solder and bonding surface, and promoting the spread of liquid solder. If the flux is concentrated in one place, it may lead to excessive gas generation in that area or excessive solder accumulation. In this embodiment, the flux dots 50 are evenly distributed between the venting channels 40, which means that the flux is also evenly distributed within the bonding area. This uniform distribution helps the eutectic reaction to proceed more consistently throughout the entire bottom area of ​​the chip, avoiding thermal stress and bonding voids caused by local reaction differences. More importantly, the evenly distributed dots and the network of venting channels 40 intertwine, allowing the gas generated by flux evaporation to be quickly captured and guided away by the nearest venting channel 40, preventing excessive gas accumulation in any local area. This synergistic design of "dot-like gas generation and network-like venting" achieves a dynamic balance between gas generation and emission. Therefore, this embodiment can achieve a more uniform and reliable eutectic bonding interface, and further improve the stability and consistency of preventing chip misalignment.

[0040] In some preferred embodiments, the vertical chip 30 is connected to the second electrode region 20 via a gold wire 60.

[0041] In practical implementation, the bottom electrode of the vertical chip 30 is typically connected to the first electrode region 10 (e.g., the negative electrode) via eutectic bonding, while the top electrode needs to be connected to the second electrode region 20 (e.g., the positive electrode) via another path to complete the circuit. Gold wire bonding 60 is a mature and reliable interconnect technology in semiconductor packaging. Using gold wire 60 to achieve this connection firstly provides excellent conductivity, ensuring efficient current transmission. Secondly, the gold wire 60 has a certain degree of flexibility, which can absorb and alleviate the thermal stress generated by the difference in thermal expansion coefficients between the chip and the substrate during temperature changes, preventing solder joint cracking or chip damage that may be caused by rigid connections, thereby improving the mechanical reliability and lifespan of the package.

[0042] In some preferred embodiments, the ceramic substrate is made of aluminum nitride.

[0043] In practice, aluminum nitride ceramic is an advanced ceramic material with extremely high thermal conductivity, far exceeding that of traditional alumina ceramic and even surpassing some metals. In high-power light source applications, the vertical chip 30 generates a large amount of heat during operation. This heat must be dissipated quickly and effectively; otherwise, the chip junction temperature will rise, leading to luminous efficiency degradation, wavelength drift, and even rapid failure. In this embodiment, using aluminum nitride as the substrate material means that the entire core heat dissipation path, from the chip through the eutectic bonding layer to the substrate, utilizes a high thermal conductivity material. The eutectic bonding layer itself already possesses excellent thermal conductivity; now, combined with the aluminum nitride substrate, it forms an extremely low thermal resistance channel from the chip to the external heat sink. This allows the heat generated by the chip to be conducted downwards to the substrate almost unimpeded and rapidly dissipated, thereby significantly reducing the chip's operating temperature.

[0044] This invention provides a packaging structure to improve the eutectic yield of a vertical chip 30. The structure includes a ceramic substrate and a vertical chip 30. The ceramic substrate includes a first electrode region 10 and a second electrode region 20 spaced apart. The surface of the first electrode region 10 has an exhaust structure. The vertical chip 30 is fixed to the first electrode region 10 via a eutectic bonding layer and connected to the second electrode region 20. The exhaust structure is located on the underside of the vertical chip 30 and extends at least partially to its outer side. This invention provides an effective exhaust channel for volatile gases generated during eutectic bonding by providing an exhaust structure on the surface of the first electrode region 10 located on the underside of the vertical chip 30 and extending to its outer side. This structure can promptly release the gas pressure accumulated under the chip, fundamentally suppressing chip misalignment during bonding, thereby significantly improving the yield of packaging production. Simultaneously, the stable bonding position ensures the integrity and uniformity of the eutectic bonding layer, enhances interface thermal conductivity, and thus improves the reliability and long-term service life of the device.

[0045] This utility model embodiment proposes a high-power light source, including the packaging structure described in any of the above embodiments for improving the eutectic yield of the vertical chip 30.

[0046] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0047] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0049] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0050] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0051] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0052] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.

[0053] The above description describes specific embodiments of this utility model, but the scope of protection of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the scope of protection of this utility model. Therefore, the scope of protection of this utility model should be determined by the scope of the claims.

Claims

1. A packaging structure for improving the yield of vertical chip eutectic bonding, characterized in that, include: A ceramic substrate includes a first electrode region and a second electrode region spaced apart, and the surface of the first electrode region is provided with an exhaust structure. A vertical chip is fixed to the first electrode region by a eutectic bonding layer and connected to the second electrode region; wherein the venting structure is located on the lower side of the vertical chip and extends at least partially to the outer side of the vertical chip.

2. The packaging structure for improving the yield of vertical chip eutectic bonding according to claim 1, characterized in that, The exhaust structure includes multiple interconnected exhaust channels, with at least one exhaust channel extending to the outside of the vertical chip.

3. The packaging structure for improving the yield of vertical chip eutectic bonding according to claim 2, characterized in that, Multiple exhaust slots are evenly distributed on the lower side of the vertical chip.

4. The packaging structure for improving the yield of vertical chip eutectic bonding according to claim 2, characterized in that, At least one exhaust groove is connected to the gap between the first electrode region and the second electrode region.

5. The packaging structure for improving the yield of vertical chip eutectic bonding according to claim 2, characterized in that, Flux dots are evenly distributed among multiple venting slots.

6. The packaging structure for improving the yield of vertical chip eutectic bonding according to claim 1, characterized in that, The vertical chip is connected to the second electrode region via gold wires.

7. The packaging structure for improving the yield of vertical chip eutectic bonding according to claim 1, characterized in that, The ceramic substrate is made of aluminum nitride.

8. A high-power light source, characterized in that, Including the packaging structure for improving vertical chip eutectic yield as described in any one of claims 1-7.

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