Semiconductor test structure

Abstract

The application relates to a semiconductor test structure, comprising a first substrate and a plurality of spaced-apart heavily doped regions, the first substrate comprising, in sequence along a direction parallel to a surface of the first substrate, a first test well region, a first diffusion region and a second test well region; the heavily doped regions comprising a first heavily doped region, a second heavily doped region and at least one to-be-tested heavily doped region between the first heavily doped region and the second heavily doped region, wherein the first heavily doped region is located in the first substrate above the first test well region, the second heavily doped region is located in the first substrate above the second test well region, and the to-be-tested heavily doped region is located in the first substrate above at least one of the first diffusion region and the second test well region. According to the electrical test results of different heavily doped regions, the diffusion offset of the first test well region is analyzed to realize online monitoring of the well region diffusion offset, and the failure analysis efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a semiconductor testing structure. Background Technology

[0002] In typical semiconductor products, the junction breakdown voltage (BV) of some platforms is far lower than the design value, failing to meet customer requirements. Therefore, failure analysis is necessary for samples exhibiting this problem to determine the specific reasons why the semiconductor products cannot meet the requirements.

[0003] Failure analysis (FA) results showed that the junction of the failed sample exhibited leakage current and a low breakdown voltage. The N+ doped regions above the N-type and P-type well regions were shorted together, and the critical dimension (CD) of the N-type well was excessively large. Since the size of the well region is related to factors such as the critical dimension (CD) during well photo development, annealing temperature, annealing time, and the energy, concentration, and angle of ion implantation, existing failure analysis methods struggle to directly monitor the well region offset, severely impacting the efficiency of semiconductor product failure analysis. Therefore, a method is needed to directly monitor the quality of semiconductor products by monitoring the well region offset. Utility Model Content

[0004] Therefore, it is necessary to provide a semiconductor test structure for online monitoring of diffusion offset in the well region, thereby improving the efficiency of failure analysis for semiconductor products.

[0005] This application provides a semiconductor test structure, including:

[0006] A first substrate, wherein the first substrate includes a first test well region, a first diffusion region and a second test well region arranged sequentially along a direction parallel to the surface of the first substrate;

[0007] Multiple heavily doped regions are arranged at intervals, including a first heavily doped region, a second heavily doped region, and at least one heavily doped region to be tested located between the first heavily doped region and the second heavily doped region. The first heavily doped region is located in a first substrate above the first test well region, the second heavily doped region is located in a first substrate above the second test well region, and the heavily doped region to be tested is located in a first substrate above at least one of the first diffusion region and the second test well region.

[0008] In one embodiment, the first heavily doped region, the heavily doped region to be tested, the first test well region, and the first diffusion region all have the same conductivity type, the second heavily doped region has the same conductivity type as the second test well region, and the first test well region has a different conductivity type than the second test well region.

[0009] In one embodiment, the semiconductor test structure further includes a plurality of isolation structures disposed between adjacent heavily doped regions and extending into the first test well region, the first diffusion region and the second test well region.

[0010] In one embodiment, the semiconductor test structure further includes:

[0011] Multiple first gates are disposed on a first substrate between two adjacent heavily doped regions to be tested, and on a first substrate between the heavily doped region to be tested and the second heavily doped region. Each of the first gates and the heavily doped regions located on both sides of the first gate constitute a MOS device unit.

[0012] In one embodiment, the first test well region, the first diffusion region, and all the heavily doped regions have the same conductivity type, and the conductivity type of the first test well region is different from that of the second test well region.

[0013] Accordingly, this application also provides a semiconductor test structure, including:

[0014] The second substrate includes a third test well region, a second diffusion region, and a fourth test well region arranged sequentially along a direction parallel to the surface of the second substrate.

[0015] A plurality of MOS devices, each MOS device including a source region and a drain region located within the second substrate and a second gate located on the second substrate, wherein the MOS devices are located above at least one of the second diffusion region and the fourth test well region;

[0016] The third doped region is located within the second substrate above the third test well region, and the third doped region is spaced apart from all the MOS devices.

[0017] In one embodiment, along the surface direction toward the second substrate, the orthogonal projection of the second gate coincides with the orthogonal projection of the source region, and the orthogonal projection of the second gate coincides with the orthogonal projection of the drain region.

[0018] In one embodiment, all the MOS devices share the same second gate.

[0019] In one embodiment, the second gate extends along a first direction, the source regions of all the MOS devices are arranged in a straight line along the first direction on one side of the second gate, and the drain regions of all the MOS devices are arranged in a straight line along the first direction on the side of the second gate away from the source regions; wherein, the first direction is a direction perpendicular to the boundary line between the third test well region and the second diffusion region.

[0020] In one embodiment, the source region, the drain region, the third heavily doped region, the third test well region, and the second diffusion region have the same conductivity type, and the fourth test well region has a different conductivity type than the second diffusion region.

[0021] An unexpected effect of this application is that multiple heavily doped regions are arranged at intervals within a first substrate, with the first heavily doped region located within the first substrate above the first test well region, and the second heavily doped region located within the first substrate above the second test well region. At least one heavily doped region to be tested is placed between the first and second heavily doped regions, such that the heavily doped region to be tested is located above at least one region of the first diffusion region and the second test well region. This allows for the analysis of the diffusion shift of the first test well region based on the electrical test results between different heavily doped regions, enabling online monitoring of the diffusion shift in the well region and improving the efficiency of failure analysis. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a top view schematic diagram of a semiconductor testing structure in a related technology.

[0024] Figure 2 This is a schematic cross-sectional view of a semiconductor testing structure in a related technology.

[0025] Figure 3 This is a schematic diagram of the current-voltage characteristic curve corresponding to the electrical test using a semiconductor test structure in a related technology.

[0026] Figure 4 This is a top view of a semiconductor test structure provided in one embodiment of this application.

[0027] Figure 5 for Figure 4The diagram shows a cross-sectional structure corresponding to the semiconductor test structure shown.

[0028] Figure 6 To adopt Figure 4 The diagram shows the current-voltage characteristic curves of the semiconductor test structure for electrical testing.

[0029] Figure 7 This is a top view of a semiconductor test structure provided in one embodiment of the present application, where a MOS device unit is included.

[0030] Figure 8 for Figure 7 The diagram shows a cross-sectional structure corresponding to the semiconductor test structure shown.

[0031] Figure 9a To adopt Figure 7 The changes in the PN junction characteristic curves when the first diffusion region in the semiconductor test structure diffuses into the y1 region are shown.

[0032] Figure 9b To adopt Figure 7 The leakage current changes when the first diffusion region in the semiconductor test structure diffuses into the y1 region.

[0033] Figure 9c To adopt Figure 7 The Vg-Id curve changes when the first diffusion region in the semiconductor test structure diffuses into the y1 region.

[0034] Figure 9d To adopt Figure 7 The changes in the PN junction characteristic curves when the first diffusion region in the semiconductor test structure diffuses into the y2 region are shown.

[0035] Figure 9e To adopt Figure 7 The leakage current changes when the first diffusion region in the semiconductor test structure diffuses into the y2 region.

[0036] Figure 9f To adopt Figure 7 The Vg-Id curve changes when the first diffusion region in the semiconductor test structure diffuses into the y2 region.

[0037] Figure 9g To adopt Figure 7 The changes in the PN junction characteristic curves when the first diffusion region in the semiconductor test structure diffuses into the y3 region are shown.

[0038] Figure 9h To adopt Figure 7The leakage current changes when the first diffusion region in the semiconductor test structure diffuses into the y3 region.

[0039] Figure 9i To adopt Figure 7 The Vg-Id curve changes when the first diffusion region in the semiconductor test structure diffuses into the y3 region.

[0040] Figure 10 This is a top view of a semiconductor test structure provided in one embodiment of the present application, where a MOS device is included.

[0041] Figure 11a for Figure 10 The diagram shows a cross-sectional view of the MOS device located above the third diffusion region in the semiconductor test structure shown.

[0042] Figure 11b for Figure 10 The diagram shows a cross-sectional view of the MOS device located above the third diffusion region and the fourth test well region in the semiconductor test structure shown.

[0043] Figure 11c for Figure 10 The diagram shows a cross-sectional view of the MOS device located above the fourth test well region in the semiconductor test structure shown.

[0044] Figure 12a for Figure 10 The diagram shows a semiconductor test structure in which the second diffusion region diffuses uniformly to the region where mos1 is located.

[0045] Figure 12b To adopt Figure 12a The leakage current change is shown when the second diffusion region in the semiconductor test structure is uniformly diffused to the region where mos1 is located.

[0046] Figure 12c To adopt Figure 12a The Vg-Id curve changes when the second diffusion region in the semiconductor test structure is uniformly diffused to the region where mos1 is located.

[0047] Figure 13a for Figure 10 The diagram shows a semiconductor test structure in which the second diffusion region diffuses non-uniformly into the source region of MOS1.

[0048] Figure 13b To adopt Figure 13a The diagram shows the change in the PN junction characteristic curve when the second diffusion region in the semiconductor test structure diffuses non-uniformly to the source region below mos1.

[0049] Figure 14a for Figure 10 The diagram shows a semiconductor test structure in which the second diffusion region diffuses non-uniformly into the drain region of MOS1.

[0050] Figure 14b To adopt Figure 14a The diagram shows the change in the PN junction characteristic curve when the second diffusion region in the semiconductor test structure diffuses non-uniformly to the drain region below mos1.

[0051] The reference numerals in the accompanying drawings include: 100-semiconductor substrate; 101-first doped region; 102-second doped region; 103-test region; 104-STI structure; X1-first well region; X2-diffusion region; X3-second well region; 200-first substrate; 201-heavily doped region; a-first heavily doped region; b-second heavily doped region; c-heavily doped region under test; 202-isolation structure; 210-first gate; Y1-first test well region; Y2-first diffusion region; Y3-second test well region; 300-second substrate; 301-source region; 302-drain region; 303-third heavily doped region; 310-second gate; 320-electrical connector; Z1-third test well region; Z2-second diffusion region; Z3-fourth test well region. Detailed Implementation

[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0057] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor test key provided in a related technology, wherein, Figure 2 for Figure 1 The diagram shows a cross-sectional view of the semiconductor test structure along the AB direction.

[0058] See Figure 1 and Figure 2 In a typical semiconductor testing structure, a first well region X1 and a second well region X3 are disposed within a semiconductor substrate 100, and a diffusion region X2 (the diffusion region X2 is the region formed by diffusion from the first well region X1 to the second well region X3) is included between the first well region X1 and the second well region X3. A first doped region 101 is disposed within the semiconductor substrate 100 above the first well region X1, a second doped region 102 is disposed within the semiconductor substrate 100 above the second well region X3, and at least one test region 103 is disposed within the semiconductor substrate 100 between the first doped region 101 and the second doped region 102, with the test region 103 located above at least one of the diffusion region X2 and the second well region X3. Optionally, the first doped region 101, the second doped region 102, and the test region 103 are all separated by an STI structure 104 (Shallow Trench Isolation).

[0059] It should be noted that the first doped region 101, the test region 103, the first well region X1, and the diffusion region X2 have the same conductivity type, the second doped region 102 and the second well region X3 have the same conductivity type, and the conductivity type of the first well region X1 is different from that of the second well region X3. For example, the first doped region 101 and the test region 103 are N+ doped regions, the first well region X1 is an N-type well region, the diffusion region X2 has an N-type conductivity type, the second doped region 102 is a P+ doped region, and the second well region X3 is a P-type well region; or, the first doped region 101 and the test region 103 are P+ doped regions, the first well region X1 is a P-type well region, the diffusion region X2 has a P-type conductivity type, the second doped region 102 is an N+ doped region, and the second well region X3 is an N-type well region.

[0060] Continue reading Figure 1 and Figure 2The process of using the semiconductor test structure described above to detect whether the breakdown voltage between the first doped region 101 and the first well region X1 to the test region 103 and the second well region X3 meets the design requirements includes: connecting the first doped region 101 to the power supply (VCC), and grounding the test region 103 and the second doped region 102 (GND), obtaining the current-voltage characteristic curve (IV Curve) of the semiconductor test structure, and determining whether the breakdown voltage of the semiconductor test structure meets the design requirements based on the obtained current-voltage characteristic curve.

[0061] For example, Figure 3 To adopt Figure 1 and Figure 2 This is a schematic diagram of the current-voltage characteristic curves obtained from electrical testing of the semiconductor test structure shown. (See attached diagram.) Figure 3 The orange line (Fail line) represents the current-voltage characteristic curve between the first doped region 101 and the test region 103 in the failed sample (Fail). The green line (Pass line) represents the current-voltage characteristic curve between the first doped region 101 and the test region 103 in the normal sample (Pass). Comparing the orange and green lines, it can be seen that there is leakage current in the region corresponding to the orange line, and the breakdown voltage corresponding to the orange line is significantly smaller than the breakdown voltage corresponding to the green line. This indicates that the first well region X1 in the failed sample has diffused, and the diffused region X2 has diffused into the semiconductor substrate 100 below the test region 103.

[0062] However, the aforementioned semiconductor test structures and corresponding test methods can only determine whether diffusion has occurred in the first well region, but cannot quantitatively monitor the diffusion offset of the first well region, which seriously affects the failure analysis efficiency of semiconductor products. Therefore, it is necessary to provide a semiconductor test structure for online monitoring of the diffusion offset of the well region, thereby improving the failure analysis efficiency of semiconductor products.

[0063] Figure 4 This is a top view schematic diagram of a semiconductor test structure provided in one embodiment of this application. Figure 5 for Figure 4 The diagram shows a cross-sectional view of the semiconductor test structure along the CD direction.

[0064] See Figure 4 and Figure 5One embodiment of this application provides a semiconductor test structure including a first substrate 200 and a plurality of heavily doped regions 201 spaced apart; wherein, the first substrate 200 includes a first test well region Y1, a first diffusion region Y2 and a second test well region Y3 arranged sequentially along a direction parallel to the surface of the first substrate 200; the heavily doped region 201 includes a first heavily doped region a, a second heavily doped region b, and at least one heavily doped region c to be tested located between the first heavily doped region a and the second heavily doped region b, wherein the first heavily doped region a is located in the first substrate 200 above the first test well region Y1, the second heavily doped region b is located in the first substrate 200 above the second test well region Y3, and the heavily doped region c to be tested is located in the first substrate 200 above at least one of the first diffusion region Y2 and the second test well region Y3.

[0065] The semiconductor test structure described above comprises multiple heavily doped regions arranged at intervals within a first substrate, with the first heavily doped region located above the first test well region within the first substrate, and the second heavily doped region located above the second test well region within the first substrate. At least one heavily doped region to be tested is positioned between the first and second heavily doped regions, such that the heavily doped region to be tested is located above at least one region of the first diffusion region and the second test well region. This allows for the analysis of the diffusion offset of the first test well region based on the electrical test results between different heavily doped regions, enabling online monitoring of the diffusion offset of the well region and improving the efficiency of failure analysis.

[0066] Continue reading Figure 4 and Figure 5 In one embodiment, the first heavily doped region a, the heavily doped region c to be tested, the first test well region Y1 and the first diffusion region Y2 have the same conductivity type, the second heavily doped region b has the same conductivity type as the second test well region Y3, and the first test well region Y1 has a different conductivity type than the second test well region Y3.

[0067] For example, Figure 4 and Figure 5 The illustration shows the case where the first heavily doped region a and all the heavily doped regions c to be tested are N+ doped regions. In this case, the first test well region Y1 is an N-type well, the first diffusion region Y2 has an N-type conductivity, the second heavily doped region b is a P+ doped region, and the second test well region Y3 is a P-type well. In other embodiments of this application, the first heavily doped region a and all the heavily doped regions c to be tested can also be P+ doped regions. Accordingly, the first test well region Y1 is a P-type well, the first diffusion region Y2 has a P-type conductivity, the second heavily doped region b is an N+ doped region, and the second test well region Y3 is an N-type well. Optionally, the first test well region Y1, the first diffusion region Y2, and the second test well region Y3 are all located within the first substrate 200.

[0068] It should be noted that in all embodiments mentioned in this application, the test well region is located in the low voltage region (LV). In other embodiments of this application, the arrangement of the test well region and the overall position of the semiconductor test structure can be reasonably set according to actual needs to meet different test requirements. This application does not impose any restrictions on this.

[0069] See Figure 5 In one embodiment, the semiconductor test structure further includes a plurality of isolation structures 202, which are disposed between adjacent heavily doped regions 201 and extend into the first test well region Y1, the first diffusion region Y2 and the second test well region Y3.

[0070] The following example illustrates the use of a scenario where four heavily doped regions are positioned between the first and second doped regions. Figure 4 and Figure 5 The diagram illustrates the specific process for detecting diffusion offset in the semiconductor test structure. (See attached document.) Figure 4 and Figure 5 Four heavily doped regions c to be tested are set between the first heavily doped region a and the second heavily doped region b (N1~N4 represent the connection ports of different heavily doped regions c to be tested). During the detection of diffusion offset using a semiconductor test structure, the first heavily doped region a is positively charged (i.e. connected to power supply VCC), and the second heavily doped region b and all the heavily doped regions c to be tested are grounded (GND). The change of the current-voltage characteristic curve between the first heavily doped region a and each heavily doped region c to be tested is obtained.

[0071] It should be noted that when the critical dimension (CD) of the first test well region Y1 meets the design rule, the PN junction formed between the first test well region Y1 and the second test well region Y3 is reverse cutoff, there is no leakage current between the PN junctions, and the corresponding breakdown voltage meets the design requirements. Therefore, the leakage current in which heavily doped region exists can be determined by the change in the volt-ampere characteristic curve between the first heavily doped region a and each heavily doped region c under test, thereby determining the specific location of the first diffusion region Y2, and then obtaining the diffusion offset of the first test well region Y1 (the diffusion offset of the first test well region Y1 is the cross-sectional width of the first diffusion region Y2).

[0072] Figure 6 To adopt Figure 4 and Figure 5 The diagram shows the current-voltage characteristic curves of the semiconductor test structure during electrical testing. N1 to N4 represent the changes in current-voltage characteristic curves for different heavily doped regions c under test. (See also...) Figures 4 to 6It can be seen that the breakdown voltage between the heavily doped region c corresponding to N1 and the first heavily doped region a is relatively small (only 0.4V), indicating that there is leakage current between the first heavily doped region a and the heavily doped region c corresponding to N1; while the breakdown voltage between the heavily doped regions c corresponding to N2, N3 and N4 and the first heavily doped region a is relatively large (all greater than or equal to 3V), which meets the design requirements for breakdown voltage. Therefore, there is no leakage current between the first heavily doped region a and the heavily doped regions c corresponding to N2, N3 and N4.

[0073] Based on the electrical test results described above, it is known that the first diffusion region Y2 extends from the first test well region Y1 into the first substrate 200 below the heavily doped region c corresponding to N1, and the first diffusion region Y2 does not extend into the first substrate 200 below the heavily doped regions c corresponding to N2, N3, and N4. Therefore, the semiconductor test structure provided in this application can quickly obtain the diffusion offset of the first test well region, realizing online monitoring of the well region diffusion offset and improving the efficiency of failure analysis.

[0074] Figure 7 This is a top view schematic diagram of a semiconductor test structure that includes a MOS device unit, as provided in one embodiment of this application. Figure 8 for Figure 7 The diagram shows a cross-sectional view of the semiconductor test structure along the EF direction. (See attached diagram.) Figure 7 and Figure 8 In one embodiment, the semiconductor test structure further includes a plurality of first gates 210, the first gates 210 being disposed on a first substrate 200 between two adjacent heavily doped regions c to be tested, and on a first substrate 200 between the heavily doped region c to be tested and the second heavily doped region b, and each first gate 210 and the heavily doped regions 201 located on both sides of the first gate 210 constitute a MOS device unit. Figure 7 and Figure 8 The structure enclosed by the rounded rectangle in the image is a MOS device unit.

[0075] It should be noted that, in the direction perpendicular to the surface of the first substrate 200, the orthographic projection of the first gate 210 and the orthographic projection of the heavily doped regions 201 on both sides of the first gate partially overlap, so as to ensure that the first gate 210 and the heavily doped regions 201 on both sides can form a MOS device unit, thereby ensuring the smooth progress of subsequent electrical tests.

[0076] exist Figure 7 and Figure 8In the semiconductor test structure shown, the first test well region Y1, the first diffusion region Y2, and all heavily doped regions 201 have the same conductivity type, and the conductivity type of the first test well region Y1 is different from that of the second test well region Y3. For example, the first test well region Y1 is an N-type well region, the first diffusion region has an N-type conductivity, all heavily doped regions 201 are N+ doped regions, and the second test well region Y3 is a P-type well region; or, the first test well region Y1 is a P-type well region, the first diffusion region has a P-type conductivity, all heavily doped regions 201 are P+ doped regions, and the second test well region Y3 is an N-type well region.

[0077] The following example illustrates the use of a scenario where five heavily doped regions are positioned between the first and second doped regions. Figure 7 and Figure 8 The detailed process of detecting diffusion offset using the semiconductor test structure shown is described. (See attached document.) Figure 7 and Figure 8 Five heavily doped regions c to be tested are set between the first heavily doped region a and the second heavily doped region b. First gates 210 are set on the first substrate 200 between adjacent heavily doped regions c and on the first substrate 200 between the heavily doped region c and its adjacent second heavily doped region b. At this time, five MOS device units are formed in the semiconductor test structure. For ease of distinction and explanation, the five MOS device units arranged in sequence along the direction away from the first heavily doped region a are named MOS1 to MOS5 respectively.

[0078] use Figure 7 and Figure 8 During the diffusion offset test of the semiconductor test structure shown, the specific location of the first diffusion region Y2 can be determined by testing the changes in the leakage current (Ioff) and the gate-source voltage (Vt) required to generate the channel for each MOS device cell, as well as the changes in the current-voltage characteristic curve corresponding to the PN junction. This allows for the determination of the diffusion offset of the first test well region Y1. Specifically, the method for determining the diffusion offset of the first test well region Y1 by testing the changes in the current-voltage characteristic curves corresponding to the PN junctions between different heavily doped regions 201 is described in [details omitted]. Figure 4 and Figure 5 The testing process for the corresponding semiconductor test structure has been described in detail, so it will not be repeated here.

[0079] Continue reading Figure 7 and Figure 8 In one embodiment, Figure 7 The D in the figure represents the heavily doped region 201 and Figure 8 The heavily doped region 201 corresponding to Drain in the middle represents the drain in different MOS device units. Figure 7 The S in the figure represents the heavily doped region 201 and Figure 8 The heavily doped region 201 corresponding to the Source in the text represents the source in different MOS device cells. Figure 7 and Figure 8 The first gate 210 in the text represents the gate in different MOS device units. Figure 7 The B in the figure represents the heavily doped region 201 and Figure 8 The heavily doped region 201 corresponding to Bulk in the middle represents the back gate of the MOS device cell.

[0080] In one embodiment, based on the semiconductor test structure described above, the process of testing the leakage current (Ioff) of each MOS device cell includes: setting the drain voltage in the MOS device cell to vary between 0 and VCC (i.e., Vd: 0~VCC), and grounding the back gate, source, and gate of the MOS device cell (i.e., Vg=Vs=Vb=0V), so that the MOS device cell is in the turn-off state, thereby obtaining the change of the leakage current Ioff of the current MOS device cell.

[0081] In one embodiment, based on the semiconductor test structure described above, the process of testing the gate-source voltage Vt required for each MOS device cell to just generate a channel includes: setting the gate voltage in the MOS device cell to vary between 0 and VCC (i.e., Vg: 0~VCC), grounding the back gate and source of the MOS device cell (i.e., Vs=Vb=0V), and setting the drain voltage of the MOS device cell to 0.1V (i.e., Vd=0.1V), thereby obtaining the variation of the gate-source voltage Vt required for the current MOS device cell to just generate a channel.

[0082] Figure 9a , Figure 9b and Figure 9c To adopt Figure 7 and Figure 8 This diagram illustrates one set of results from electrical testing of the semiconductor test structure shown. (See attached image.) Figures 9a to 9c It can be seen that leakage current exists in MOS1 (i.e., the MOS device cell closest to the first doped region a). Figure 9a The SB IV characteristic curve corresponding to MOS1 is higher than the IV characteristic curves corresponding to other MOS device units, and the DB IV curves, Ioff, and VG-Id IV curves of all MOS device units are normal. It can be seen that the first diffusion region Y2 has diffused to Figure 8 Within the region represented by y1 (i.e., the diffusion offset of the first test well region Y1 is the cross-sectional width corresponding to the region represented by y1).

[0083] Figure 9d , Figure 9e and Figure 9f To adopt Figure 7 and Figure 8 This diagram illustrates one set of results from electrical testing of the semiconductor test structure shown. (See attached image.) Figures 9d to 9f It can be seen that MOS1 has a low Vt and leakage Ioff, and the DB-IV curves of all MOS device cells are normal. This indicates that the first diffusion region Y2 has diffused to Figure 8 Within the region represented by y2 (i.e., the diffusion offset of the first test trap region Y1 is the sum of the cross-sectional widths corresponding to the regions represented by y1 and y2), the diffusion offset is the sum of the cross-sectional widths of the regions represented by y1 and y2.

[0084] Figure 9g , Figure 9h and Figure 9i To adopt Figure 7 and Figure 8 This diagram illustrates one set of results from electrical testing of the semiconductor test structure shown. (See attached image.) Figures 9g to 9i It can be seen that MOS1 has a small Vt, leakage Ioff, and leakage in the PN junction, indicating that the first diffusion region Y2 has diffused to Figure 8 Within the region represented by y3 (i.e., the diffusion offset of the first test trap region Y1 is the sum of the cross-sectional widths corresponding to the three regions represented by y1, y2 and y3 respectively).

[0085] Based on the electrical test results described above, it is evident that monitoring the changes in the PN junction, Ioff, and Vt of each MOS device unit can improve the testing accuracy of the diffusion offset in the first test well region Y1. Therefore, the semiconductor test structure provided in this application not only allows for rapid acquisition of the diffusion offset in the first test well region, enabling online monitoring of the diffusion offset, but also improves the testing accuracy of the diffusion offset by incorporating MOS device units within the semiconductor test structure. This enhances both the efficiency and accuracy of failure analysis results.

[0086] Figure 10 This is a top view schematic diagram of a semiconductor test structure that includes a MOS device, as provided in one embodiment of this application. Figure 11a for Figure 10 The diagram shows a cross-sectional view of the semiconductor test structure along the OP direction. Figure 11b for Figure 10 The diagram shows a cross-sectional view of the semiconductor test structure along the QR direction. Figure 11c for Figure 10 The diagram shows a cross-sectional view of the semiconductor test structure along the ST direction.

[0087] See Figure 10 , Figures 11a to 11c One embodiment of this application provides a semiconductor test structure including a second substrate 300, a third heavily doped region 303, and multiple MOS devices. Figure 10 The structure framed by the rounded rectangle is one of the MOS devices. The second substrate 300 includes a third test well region Z1, a second diffusion region Z2, and a fourth test well region Z3 arranged sequentially along a direction parallel to the surface of the second substrate 300. The MOS device includes a source region 301 and a drain region 302 located in the second substrate 300, and a second gate 310 located on the second substrate 300. The MOS device is located above at least one of the second diffusion region Z2 and the fourth test well region Z3. The third heavily doped region 303 is located in the second substrate 300 above the third test well region Z1, and the third heavily doped region 303 is spaced apart from all the MOS devices.

[0088] As described above, the semiconductor test structure has multiple source regions and multiple drain regions in the second substrate, and a second gate is formed on the second substrate to form multiple MOS devices including a second gate, source region and drain region in the semiconductor test structure. The diffusion offset of the third test well region can be obtained through the electrical test results of each MOS device, realizing online monitoring of the diffusion offset of the well region and improving the failure analysis efficiency.

[0089] See Figure 10 and Figure 11a In one embodiment, along the surface direction toward the second substrate 300, the orthographic projection of the second gate 310 partially coincides with the orthographic projection of the source region 301, and the orthographic projection of the second gate 310 partially coincides with the orthographic projection of the drain region 302, so as to ensure that the MOS device formed by the second gate 310, the source region 301 and the drain region 302 can operate normally, thereby ensuring that the semiconductor test structure can meet the test requirements of the well region diffusion offset.

[0090] Continue reading Figure 10 In one embodiment, all MOS devices share the same second gate 310. In one embodiment, the second gate 310 extends along a first direction (the first direction is perpendicular to the boundary line between the third test well region Z1 and the second diffusion region Z2), the source regions 301 of all MOS devices are arranged in a linear interval along the first direction on one side of the second gate 310, and the drain regions 302 of all MOS devices are arranged in a linear interval along the first direction on the side of the second gate 310 away from the source regions 301.

[0091] In one embodiment, the source region, drain region, third heavily doped region, third test well region, and second diffusion region have the same conductivity type, and the fourth test well region has a different conductivity type than the second diffusion region. For example, see [reference needed]. Figure 10 , Figures 11a to 11c In this embodiment, the source region 301, drain region 302, and third heavily doped region 303 are all N+ doped regions. The third test well region Z1 is an N-type well region, the second diffusion region Z2 has an N-type conductivity, and the fourth test well region Z3 is a P-type well region. In other embodiments of this application, the source region, drain region, and third heavily doped region can also be P+ doped regions. Accordingly, the third test well region is a P-type well region, the second diffusion region has a P-type conductivity, and the fourth test well region is an N-type well region.

[0092] The following example, using a semiconductor test structure with five MOS devices, illustrates in detail the use of... Figure 10 The detailed process of detecting diffusion offset using the semiconductor test structure shown is described. (See attached document.) Figure 10 The semiconductor test structure is equipped with five MOS devices. For ease of differentiation and explanation, the five MOS devices are arranged sequentially along the direction away from the third doped region 303 and named mos1~mos5 respectively.

[0093] In one embodiment, Figure 10 The drain region 302 represented by D in the figure and Figures 11a to 11c The drain region 302 corresponding to Drain in the middle represents the drain in different MOS devices. Figure 10 The source pole region 301 represented by S in the figure is... Figures 11a to 11c The source region 301 corresponding to Source in the text represents the source in different MOS devices. Figure 10 , Figures 11a to 11c The second gate 310 in the text represents the gate in different MOS devices. Figure 10 The third doped region 303, represented by B in the figure, represents the back gate of the MOS device.

[0094] use Figure 10 , Figures 11a to 11c During the diffusion offset test of the semiconductor test structure shown, the specific location of the second diffusion region Z2 can be determined by measuring the changes in the leakage current (Ioff) and the gate-source voltage (Vt) required to form a channel for each MOS device cell, as well as the changes in the current-voltage characteristic curve of the PN junction. This allows for the determination of the diffusion offset of the third test well region Z1. The specific methods for measuring the changes in the leakage current (Ioff) and the gate-source voltage (Vt) required to form a channel for each MOS device are described in [the following text is incomplete and requires further context]. Figure 7 and Figure 8 The testing process for the corresponding semiconductor test structure has been described in detail, so it will not be repeated here.

[0095] Figure 12a for Figure 10 The diagram shows the structure of the semiconductor test structure after diffusion. Figure 12b and Figure 12c To adopt Figure 12a This diagram illustrates the results of electrical testing on the semiconductor test structure shown. (See attached image.) Figure 12b and Figure 12c It can be seen that leakage current exists in MOS1 (i.e., the MOS device closest to the third doped region 303), and the Vt of MOS1 is smaller than that of other MOS devices. Therefore, in Figure 12a In the semiconductor test structure shown, the second diffusion region Z2 has been uniformly diffused into the second substrate 300 below the MOS device corresponding to mos1 (that is, the diffusion offset of the third test well region Z1 is the cross-sectional width of the MOS device corresponding to mos1).

[0096] Figure 13a for Figure 10 The diagram shows one of the structures of the semiconductor test structure after diffusion. Figure 13b To adopt Figure 13a This diagram illustrates the results of electrical testing on the semiconductor test structure shown. (See attached image.) Figure 13a and Figure 13b It can be seen that, Figure 13b There is leakage current between the source and back gate (SB) of MOS1, and no leakage current between the drain and back gate (DB) of MOS1. It can be seen that the second diffusion region Z2 has diffused to below the source region 301 of the MOS device corresponding to MOS1, and the second diffusion region Z2 has not diffused to below the drain region 302 of the MOS device corresponding to MOS1. At this time, the diffusion offset of the third test well region Z1 is the cross-sectional width of the source region 301 corresponding to MOS1, and the diffusion of the third test well region Z1 is non-uniform.

[0097] Figure 14a for Figure 10 The diagram shows one of the structures of the semiconductor test structure after diffusion. Figure 14b To adopt Figure 14a This diagram illustrates the results of electrical testing on the semiconductor test structure shown. (See attached image.) Figure 14a and Figure 14b It can be seen that, Figure 14b There is leakage current between the drain and back gate (DB) of MOS1, and no leakage current between the source and back gate (SB) of MOS1. It can be seen that the second diffusion region Z2 has diffused to below the drain region 302 of the MOS device corresponding to MOS1, and the second diffusion region Z2 has not diffused to below the source region 301 of the MOS device corresponding to MOS1. At this time, the diffusion offset of the third test well region Z1 is the cross-sectional width of the drain region 302 corresponding to MOS1, and the diffusion of the third test well region Z1 is non-uniform.

[0098] Based on the electrical test results described above, it is evident that monitoring the changes in the PN junction, Ioff, and Vt of each MOS device can improve the testing accuracy of the diffusion offset in the third test well region Z1. Furthermore, the uniformity of diffusion in the third test well region Z1 can be determined based on the electrical test structure. Therefore, the semiconductor test structure provided in this application not only allows for rapid acquisition of the diffusion offset in the third test well region, enabling online monitoring of the diffusion offset, but also enhances the monitoring of diffusion uniformity by incorporating MOS devices within the semiconductor test structure. This improves both the efficiency and accuracy of failure analysis results.

[0099] An unexpected effect of this application is that multiple heavily doped regions are arranged at intervals within a first substrate, with the first heavily doped region located within the first substrate above the first test well region, and the second heavily doped region located within the first substrate above the second test well region. At least one heavily doped region to be tested is placed between the first and second heavily doped regions, such that the heavily doped region to be tested is located above at least one region of the first diffusion region and the second test well region. This allows for the analysis of the diffusion shift of the first test well region based on the electrical test results between different heavily doped regions, enabling online monitoring of the diffusion shift in the well region and improving the efficiency of failure analysis.

[0100] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A semiconductor testing structure, characterized in that, include: A first substrate, wherein the first substrate includes a first test well region, a first diffusion region and a second test well region arranged sequentially along a direction parallel to the surface of the first substrate; Multiple heavily doped regions are arranged at intervals, including a first heavily doped region, a second heavily doped region, and at least one heavily doped region to be tested located between the first heavily doped region and the second heavily doped region. The first heavily doped region is located in a first substrate above the first test well region, the second heavily doped region is located in a first substrate above the second test well region, and the heavily doped region to be tested is located in a first substrate above at least one of the first diffusion region and the second test well region.

2. The semiconductor test structure according to claim 1, characterized in that, The first heavily doped region, the heavily doped region to be tested, the first test well region, and the first diffusion region all have the same conductivity type. The second heavily doped region has the same conductivity type as the second test well region, and the first test well region has a different conductivity type than the second test well region.

3. The semiconductor test structure according to claim 2, characterized in that, The semiconductor test structure also includes multiple isolation structures, which are disposed between adjacent heavily doped regions and extend into the first test well region, the first diffusion region, and the second test well region.

4. The semiconductor test structure according to claim 1, characterized in that, The semiconductor testing structure also includes: Multiple first gates are disposed on a first substrate between two adjacent heavily doped regions to be tested, and on a first substrate between the heavily doped region to be tested and the second heavily doped region. Each of the first gates and the heavily doped regions located on both sides of the first gate constitute a MOS device unit.

5. The semiconductor test structure according to claim 4, characterized in that, The first test well region, the first diffusion region, and all the heavily doped regions have the same conductivity type, and the conductivity type of the first test well region is different from that of the second test well region.

6. A semiconductor testing structure, characterized in that, include: The second substrate includes a third test well region, a second diffusion region, and a fourth test well region arranged sequentially along a direction parallel to the surface of the second substrate. A plurality of MOS devices, each MOS device including a source region and a drain region located within the second substrate and a second gate located on the second substrate, wherein the MOS devices are located above at least one of the second diffusion region and the fourth test well region; The third doped region is located within the second substrate above the third test well region, and the third doped region is spaced apart from all the MOS devices.

7. The semiconductor test structure according to claim 6, characterized in that, Along the surface direction toward the second substrate, the orthogonal projection of the second gate coincides with the orthogonal projection of the source region, and the orthogonal projection of the second gate coincides with the orthogonal projection of the drain region.

8. The semiconductor test structure according to claim 6, characterized in that, All of the MOS devices share the same second gate.

9. The semiconductor test structure according to claim 8, characterized in that, The second gate extends along a first direction, and the source regions of all the MOS devices are arranged in a straight line along the first direction on one side of the second gate. The drain regions of all the MOS devices are arranged in a straight line along the first direction on the side of the second gate away from the source regions. The first direction is perpendicular to the boundary line between the third test well region and the second diffusion region.

10. The semiconductor test structure according to claim 6, characterized in that, The source region, the drain region, the third heavily doped region, the third test well region, and the second diffusion region have the same conductivity type, and the fourth test well region has a different conductivity type than the second diffusion region.

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