SOP package chip test socket

Abstract

The utility model relates to the technical field of semiconductor test, especially a SOP package chip test seat, its technical scheme includes: the design of the original shielding chip body is changed to the design of shielding chip pin directly, makes the height of retaining wall only is influenced by the thickness of pin, and is not the thickness of chip whole, thereby reduces the processing difficulty, makes the height of retaining wall no longer is limited by chip thickness, size is more easily controlled, is suitable for high density pin package, is connected through the stiffener between a plurality of retaining walls and forms integrated structure, improves overall strength and stability significantly, thereby improves structural strength, and the stiffener design makes retaining wall form continuous support, reduces the vulnerability of separate step, controls the proportion of retaining wall height and width within 4:1, accords with the processing specification, thereby promotes the reliability of package, retaining wall protects pin directly, reduces stress concentration, improves the overall performance of package.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor testing technology, and in particular to a test socket for SOP packaged chips. Background Technology

[0002] To position the chip accurately within the test socket and ensure smooth and accurate testing, several baffles are arranged in rows on the bottom wall of the mounting slot of the test socket. During chip installation, these baffles are positioned close to the side wall of the chip body and between adjacent pins, serving a positioning function.

[0003] Traditional barrier designs typically directly obscure the chip body, which presents the following problems: the barrier height is greatly affected by the chip thickness, resulting in an imbalance between the barrier height and width, making manufacturing difficult; the structural strength is low, as each barrier in the old structure is an individual step, lacking overall support and easily damaged; and manufacturing is difficult. For example, with a pin pitch of 0.5mm, the barrier width is only 0.18mm and the height reaches 0.8mm, with a height-to-width ratio exceeding 4:1, which does not meet manufacturing recommendations.

[0004] In the prior art, patent CN217112615U discloses an integrated circuit packaging and testing device, but it mainly focuses on pin fixing and testing structure, and does not solve the structural strength and manufacturability issues in the barrier design. Therefore, there is an urgent need for a new barrier structure to optimize the packaging process.

[0005] In view of this, we propose an SOP-packaged chip test socket to solve the existing problems. Utility Model Content

[0006] The purpose of this invention is to provide a SOP packaged chip test socket to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: an SOP packaged chip test socket, including a test socket, a chip mounting groove is provided at the center of the upper surface of the test socket, a plurality of baffles are provided on both sides of the chip mounting groove, a pin mounting groove is provided between two adjacent baffles, and the multiple baffles are connected by reinforcing ribs to form an integrated structure, wherein the height to width ratio of the baffles is less than or equal to 4:1.

[0008] Furthermore, the retaining wall is in the shape of a pentagonal prism, with the base of the pentagonal prism perpendicular to the base of the chip mounting slot.

[0009] Furthermore, the pentagonal base of the pentagonal prism is formed by a rectangle missing a corner.

[0010] Furthermore, the lower side of the retaining wall faces the chip mounting slot, while the higher side of the retaining wall faces away from the chip mounting slot.

[0011] Furthermore, an edge stage is provided on the side of the pin mounting slot opposite to the chip mounting slot.

[0012] Furthermore, the edge platform is connected to the high side of the retaining wall, and the height of the edge platform is flush with that of the retaining wall.

[0013] Compared with the prior art, the beneficial effects of this utility model are:

[0014] This invention changes the original design of shielding the chip body to one that directly shields the chip pins. This makes the shield height only affected by the pin thickness, rather than the overall chip thickness, thus reducing manufacturing difficulty. The shield height is no longer limited by chip thickness, and the dimensions are easier to control, making it suitable for high-density pin packaging. Multiple shields are connected by reinforcing ribs to form an integrated structure, significantly improving overall strength and stability. The reinforcing rib design provides continuous support, reducing the vulnerability of individual steps. The height-to-width ratio of the shield is controlled within 4:1, conforming to manufacturing specifications and improving packaging reliability. The shields directly protect the pins, reducing stress concentration and improving overall packaging performance. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of an existing SOP packaged chip test socket;

[0016] Figure 2 A schematic diagram of the baffle structure of an existing SOP packaged chip test socket;

[0017] Figure 3 A schematic diagram of a chip mounted on an existing SOP-packaged chip test socket;

[0018] Figure 4 A schematic diagram of the baffle structure for mounting a chip in an existing SOP packaged chip test socket;

[0019] Figure 5 This is a schematic diagram of the structure of the SOP packaged chip test socket of this utility model;

[0020] Figure 6 This is a schematic diagram of the baffle structure of the SOP packaged chip test socket of this utility model;

[0021] Figure 7 This is a schematic diagram of the structure of the chip mounted in the SOP packaged chip test socket of this utility model;

[0022] Figure 8 This is a schematic diagram of the baffle structure for mounting the chip in the SOP packaged chip test socket of this utility model.

[0023] In the diagram: 10, Existing test socket; 20, Existing chip mounting slot; 30, Existing retainer; 40, Existing pin mounting slot; 00, Chip; 01, Pin; 1, Test socket; 2, Chip mounting slot; 3, Retainer; 4, Pin mounting slot; 5, Edge stage. Detailed Implementation

[0024] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments.

[0025] Example 1

[0026] like Figure 1 As shown, an existing chip mounting slot 20 is provided at the center of the upper surface of the existing test socket 10, and several existing retaining walls 30 are provided on both sides of the existing chip mounting slot 20.

[0027] like Figure 2 As shown, an existing pin mounting slot 40 is provided between two adjacent existing retaining walls 30.

[0028] like Figure 3 and Figure 4 As shown, when installing chip 00, the adjacent existing retaining wall 30 is close to the side wall of chip 00 and located between adjacent pins 01, which serves as a positioning function.

[0029] The height of the existing retainer wall 30 is greatly affected by the thickness of the chip 00, resulting in an imbalance between the height and width ratio of the existing retainer wall 30, making it difficult to manufacture; the structural strength is low, as each existing retainer wall 30 is an individual step, lacking overall support and easily damaged; and the manufacturing is difficult, for example, with a pin 01 pitch of 0.5mm, the width of the existing retainer wall 30 is only 0.18mm, and the height reaches 0.8mm, with a height-to-width ratio exceeding 4:1, which does not meet the manufacturing recommendations.

[0030] like Figure 5 As shown, an SOP packaged chip test socket includes a test socket 1, a chip mounting groove 2 is provided at the center of the upper surface of the test socket 1, and several baffles 3 are provided on both sides of the chip mounting groove 2.

[0031] like Figure 6 As shown, a pin mounting slot 4 is provided between two adjacent retaining walls 3. Multiple retaining walls 3 are connected by reinforcing ribs to form an integrated structure. The height-to-width ratio of the retaining wall 3 is less than or equal to 4:1. The retaining wall 3 is pentagonal in shape, and the base of the pentagonal prism is perpendicular to the base of the chip mounting slot 2. The pentagon of the base of the pentagonal prism is formed by a rectangle missing a corner. The lower side of the retaining wall 3 faces the chip mounting slot 2, and the higher side of the retaining wall 3 faces away from the chip mounting slot 2. An edge platform 5 is provided on the side of the pin mounting slot 4 facing away from the chip mounting slot 2. The edge platform 5 is connected to the higher side of the retaining wall 3, and the height of the edge platform 5 is flush with that of the retaining wall 3.

[0032] like Figure 7 and Figure 8 As shown, when installing chip 00, the adjacent retaining wall 3 is only located between the adjacent pin 01 and the respective pin mounting slot 4, and the retaining wall 3 can play a positioning role without being close to the side wall of chip 00 body.

[0033] For chip 00 with a pin pitch of 0.5mm, the width of retainer 3 is designed to be approximately 0.18mm. Since the height of retainer 3 is determined only by the thickness of pin 01, its height can be optimized to approximately 0.72mm or less. In this case, the ratio of the height to the width of retainer 3 is 0.72 / 0.18 = 4:1, which conforms to the machining recommendation that "the height of retainer 3 should be less than or equal to 4 times the width," effectively solving the machining difficulties and tool wear problems caused by excessive aspect ratio.

[0034] The working principle of a SOP packaged chip test socket based on Embodiment 1 is as follows:

[0035] During testing, the operator places chip 00 into the chip mounting slot 2 of test socket 1. As chip 00 falls, the side of its pin 01 contacts the positioning surface of the retainer 3, and under the guidance of gravity and a slight external force, slides into the accurate mounting position. Because retainer 3 directly positions pin 01 and is at a suitable height, interference with the chip 00 body is avoided. Simultaneously, the reinforcing ribs connecting each retainer ensure that the retainer 3 structure will not break or deform due to stress during repeated insertions, removals, and tests, thus guaranteeing long-term stability and positioning accuracy.

[0036] Therefore, the aspect ratio of the retaining wall 3 is effectively controlled, reducing the manufacturing difficulty and cost of using milling and other machining processes, and making the processing feasible. The integrated reinforcing rib design makes the retaining wall 3 a solid whole, significantly extending its service life and making the structure robust and durable. Direct positioning of pin 01 avoids positioning errors caused by the size tolerance of chip 00, improving the accuracy and consistency of testing, and making the positioning precise and reliable.

[0037] The above specific embodiments are merely several preferred embodiments of this utility model. Based on the technical solution of this utility model and the relevant teachings of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.

Claims

1. A test socket for SOP packaged chips, comprising a test socket (1), wherein a chip mounting groove (2) is provided at the center of the upper surface of the test socket (1), and a plurality of baffles (3) are provided on both sides of the chip mounting groove (2), characterized in that: Pin mounting slots (4) are provided between two adjacent retaining walls (3). Multiple retaining walls (3) are connected by reinforcing ribs to form an integrated structure. The height to width ratio of the retaining wall (3) is less than or equal to 4:

1.

2. The SOP packaged chip test socket according to claim 1, characterized in that: The retaining wall (3) is in the shape of a pentagonal prism, and the bottom surface of the pentagonal prism is perpendicular to the bottom surface of the chip mounting slot (2).

3. A test socket for an SOP-packaged chip according to claim 2, characterized in that: The pentagonal base of a pentagonal prism is formed by a rectangle missing a corner.

4. A test socket for an SOP-packaged chip according to claim 1, characterized in that: The lower side of the retaining wall (3) faces the chip mounting slot (2), and the higher side of the retaining wall (3) faces away from the chip mounting slot (2).

5. A test socket for an SOP-packaged chip according to claim 1, characterized in that: The pin mounting slot (4) has an edge platform (5) on the side opposite to the chip mounting slot (2).

6. A test socket for an SOP-packaged chip according to claim 5, characterized in that: The edge platform (5) is connected to the high side of the retaining wall (3), and the height of the edge platform (5) is flush with that of the retaining wall (3).

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