3D-IC interlayer low thermal stress micro-channel heat dissipation structure based on needle ribs and semi-elliptical concave cavities
Patent Information
- Application Number
- CN202521362817.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2035-06-30
AI Technical Summary
[0004]本实用新型的目的是提供一种基于针肋与半椭圆凹穴协同的3D-IC层间低热应力微通道散热结构，旨在解决或改善上述技术问题
[0017]与现有技术相比，本实用新型提供一种基于针肋与半椭圆凹穴协同的3D-IC层间低热应力微通道散热结构具有以下有益效果：在3D-IC芯片层间直接构建微通道结构，使堆叠芯片产生的热量可通过最短热路径传递至散热器，通过冷却液完成外部散热；针肋与半椭圆凹穴协同散热，扩展了传热面积并破坏边界层发展，生成的涡旋扰动诱导中心主流流体产生混沌对流，有效缩减了近壁的层流滞止区，平衡通道内的流动阻力，提高散热效率；针肋设置在凹穴上游，有助于减小凹穴处涡旋区面积，减小沿程阻力系数，减少能量损失；通道壁与针肋结构共同为3D-IC芯片间信号传输的TSV提供了热-力协同设计空间；圆台形TSV便于金属导体的填充以及其更均匀的应力分布；半椭圆凹穴光滑曲率设计可以减少污染物附着概率，自洁能力较强，同时其应力分布均匀。
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Abstract
Description
Technical Field
[0001] This invention belongs to the technical field of semiconductor chip and integrated circuit heat dissipation, and particularly relates to a 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses. Background Technology
[0002] With the advancement of technology, Moore's Law is also facing the constraints of physical limits. Problems such as quantum effects and short-channel effects are becoming increasingly serious, slowing down the improvement of single-chip computing power. Relying solely on Moore's Law is no longer sufficient to enhance chip performance. With the advent of the AI era, the demand for computing power and multifunctionality in emerging intelligent products is becoming increasingly urgent, making advanced packaging technology a new engine for integrated circuits.
[0003] Three-dimensional integrated circuits (3D-ICs) are a semiconductor technology that achieves high-density integration, low power consumption, and diverse functions by vertically stacking multiple layers of chips or wafers and utilizing advanced interconnect technologies (such as through-silicon vias (TSVs) and microbumps). However, the vertical stacking of integrated circuits causes a surge in power density between stacked chip layers, resulting in a non-linear temperature rise trend in the chip's operating temperature. Simultaneously, due to the differences in the coefficient of thermal expansion (CTE) of different materials, thermal stress accumulates significantly under rapidly rising temperatures, leading to typical failure problems such as crack propagation around the through-silicon vias (TSVs). Utility Model Content
[0004] The purpose of this invention is to provide a 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses, aiming to solve or improve the above-mentioned technical problems.
[0005] To achieve the above objectives, this utility model provides the following solution:
[0006] A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of ribs and semi-elliptical recesses includes a heat dissipation structure body (1), chips (2) are disposed on the upper and lower surfaces of the heat dissipation structure body, the heat dissipation structure body is a cuboid structure, the cuboid structure is provided with several parallel microchannels (3) for cooling working fluid to flow along the length of the cuboid, the several microchannels are equidistantly distributed along the width of the cuboid; the adjacent microchannels (3) are separated by channel walls; each microchannel has multiple semi-elliptical recesses (4) on the left and right sidewalls (i.e. the sidewalls corresponding to the channel walls), the multiple semi-elliptical recesses are evenly spaced along the length of the sidewalls, and the semi-elliptical recesses on the left and right sides are respectively opposite each other, each pair of left and right is opposite each other. Two semi-elliptical recesses are denoted as recesses. The length direction of the cuboid corresponds to the full long axis of the semi-elliptical recess, the width direction of the cuboid corresponds to the short half axis of the semi-elliptical recess, and the height direction of the cuboid corresponds to the semi-elliptical concave cylinder. A needle rib (5) is set at the position of each recess in the microchannel (3). The length direction of the needle rib is consistent with the height direction of the cuboid, and the position of the needle rib is close to the upstream of the recess (i.e., the upstream corresponding to the flow of the cooling working fluid). A through-silicon via (TSV) (6) is provided at the position of the channel wall. The length of the through-silicon via (TSV) extends through the height of the cuboid until there are micro-bumps (7) on the upper and lower surfaces of the cuboid, i.e., there are micro-bumps (7) on the upper and lower surfaces of the heat dissipation structure body. The micro-bumps are used to realize the electrical interconnection between the chip (2) and the heat dissipation structure body (1).
[0007] Alternatively, through-silicon vias (TSVs) can be provided in different pin ribs as needed, and corresponding micro-protrusions (7) can be provided on the upper and lower surfaces of the heat dissipation structure body; the through-silicon vias (TSVs) are located inside the pin ribs.
[0008] The needle rib is a type of needle with a cross-section that is circular, teardrop-shaped, rhomboid, elliptical, or trapezoidal.
[0009] The through-silicon via (TSV) is encapsulated by a metal conductor (61), a diffusion barrier layer (62), and a dielectric isolation layer (63) arranged sequentially from the center outwards.
[0010] The through-silicon via (TSV) is truncated cone-shaped, and the corresponding metal conductor is also truncated cone-shaped. The height of the truncated cone is along the height direction of the cuboid structure. The side of the truncated cone-shaped metal conductor is successively wrapped by a diffusion barrier layer and a dielectric isolation layer.
[0011] The width of the microchannel itself (i.e., the width of the microchannel without the semi-elliptical recess) is 100 μm, the corresponding channel wall width is 100 μm, and the microchannel height is 200 μm.
[0012] The semi-elliptical cavity has a semi-major axis of 100μm, a semi-minor axis of 10-60μm, a height of 200μm, a dimension of 25-30μm in the direction of the needle rib cross section, a needle rib height of the same as the microchannel height, and a spacing of 400μm between adjacent needle ribs along the length of the microchannel.
[0013] In a through-silicon via (TSV), the diameters of the upper and lower surfaces of the metal conductor are 10-20 μm, with the lower surface diameter being smaller than the upper surface diameter. The diffusion barrier layer has a thickness of 5-50 nm, and the dielectric isolation layer has a thickness of 0.1-1 μm.
[0014] One end of the microchannel is the inlet, and the other end is the outlet. The working fluid is deionized water.
[0015] The heat dissipation structure body is made of silicon.
[0016] The metal conductor is copper or tungsten, the diffusion barrier layer is titanium nitride or tantalum nitride, and the dielectric isolation layer is silicon dioxide or silicon nitride.
[0017] Compared with existing technologies, this utility model provides a low thermal stress microchannel heat dissipation structure for 3D-IC interlayer based on the synergy of pin ribs and semi-elliptical recesses, which has the following advantages: The microchannel structure is directly constructed between 3D-IC chip layers, allowing the heat generated by stacked chips to be transferred to the heat sink via the shortest thermal path, and external heat dissipation is achieved through coolant; the synergistic heat dissipation of pin ribs and semi-elliptical recesses expands the heat transfer area and disrupts boundary layer development. The generated vortex disturbance induces chaotic convection in the central mainstream fluid, effectively reducing the laminar stagnation zone near the wall, balancing the flow resistance within the channel, and improving heat dissipation efficiency; the pin ribs are located upstream of the recesses, helping to reduce the vortex area at the recesses, reduce the friction coefficient, and reduce energy loss; the channel wall and pin rib structure together provide a thermal-mechanical synergistic design space for the TSV (Transmission Channel Vessel) for signal transmission between 3D-IC chips; the frustum-shaped TSV facilitates the filling of metal conductors and their more uniform stress distribution; the smooth curvature design of the semi-elliptical recesses reduces the probability of contaminant adhesion, has strong self-cleaning ability, and its stress distribution is uniform. Attached Figure Description
[0018] Figure 1 This is a three-dimensional schematic diagram of the microchannel heat dissipation structure of this utility model.
[0019] Figure 2 This is a partial schematic diagram of the microchannel heat dissipation structure of this utility model.
[0020] Figure 3 This is a side sectional view of the microchannel heat dissipation structure of this utility model.
[0021] Figure 4 This is a cross-sectional view of the TSV microchannel heat dissipation structure of this utility model.
[0022] Figure 5 This is a schematic diagram of the elliptical needle rib structure of the microchannel heat dissipation structure of this utility model.
[0023] Figure 6 This is a schematic diagram of the water droplet needle rib structure of the microchannel heat dissipation structure of this utility model.
[0024] Figure 7 This is a schematic diagram of the trapezoidal needle rib structure of the microchannel heat dissipation structure of this utility model.
[0025] Figure 8 This is a schematic diagram of the prismatic needle rib structure of the microchannel heat dissipation structure of this utility model.
[0026] In the figure: 1. Chip; 2. Microchannel heat dissipation structure body; 3. Microchannel; 4. Semi-elliptical cavity; 5. Pin rib; 6. TSV structure; 61. Metal conductor; 62. Diffusion barrier layer; 63. Dielectric isolation layer; 7. Microbump. Detailed Implementation
[0027] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0028] In the description of this utility model, technical terms such as "middle," "upper," "lower," "upstream," "length," "width," and "height" are based on the orientation or positional relationship shown in the accompanying drawings. These terms are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element must have a specific orientation or be constructed and operated in a specific manner. Therefore, they should not be construed as limitations on the embodiments of this application.
[0029] like Figure 1 , 2As shown in Figure 3, Example 1 provides a 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses. The structure includes a heat dissipation structure body (2), with a chip (1) disposed on the upper and lower sides of the heat dissipation structure body. The structure is provided with several microchannels (3) for the cooling working fluid to flow along the length direction. The microchannels (3) are equidistantly distributed along the width direction, and adjacent channels are isolated by channel walls. Since the length dimension of the microchannel is significantly larger than its width dimension, the improvement in the overall heat conduction efficiency of the heat sink by a single microstructure is significantly limited. Therefore, each microchannel consists of 24 sets of semi-elliptical recesses (4) disposed on both sides of the channel wall and 24 corresponding circular needle ribs (5) arranged in the middle of the channel, near the upstream of the recesses along the length direction. The circular needle ribs (5) and the semi-elliptical recesses (4) work together to dissipate heat, expanding the heat transfer area and disrupting boundary layer development. The generated vortex disturbance induces chaotic convection in the central mainstream fluid, effectively reducing the laminar stagnation zone near the wall, balancing the flow resistance within the channel, and improving heat dissipation efficiency. The significance of arranging the needle rib (5) upstream of the cavity (4) is to disrupt the flow boundary layer, enhance the heat transfer efficiency between the channel wall and the fluid, reduce the vortex area at the semi-elliptical cavity, reduce the friction coefficient, and reduce energy loss.
[0030] The channel wall and the pin ribs (5) have several through-silicon vias (TSVs) evenly distributed along the length direction and penetrating the upper and lower surfaces of the heat dissipation structure body (2). Simultaneously, microbumps (7) enable interconnection between the chip (1) and the heat dissipation structure (2). This structure is directly constructed between the 3D-IC chip layers, allowing the heat generated by the stacked chips to be transferred to the heat sink via the shortest thermal path. The microchannel (3) has a width of 100 μm, a channel wall width of 100 μm, and a height of 200 μm. The semi-elliptical recess (4) has a semi-major axis of 100 μm, a semi-minor axis of 50 μm, and a height of 200 μm. The diameter of the circular pin ribs must be within a certain length to ensure sufficient area for the TSVs; therefore, the pin rib (5) diameter is 30 μm, and the length-direction spacing between adjacent pin ribs (5) is 400 μm. One end of the channel is an inlet, and the other end is an outlet; the working fluid is deionized water. The heat dissipation structure body is made of silicon.
[0031] like Figure 4As shown, this embodiment 1 provides a 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of pin ribs and semi-elliptical recesses. The through-silicon via (TSV) (6) consists of a metal conductor (61), a diffusion barrier layer (62), and a dielectric isolation layer (63). In this embodiment, the metal conductor (61) is copper, the diffusion barrier layer (62) is titanium nitride, and the dielectric isolation layer (63) is silicon dioxide. Due to the difference in the coefficient of thermal expansion (CTE) of different materials, under high-temperature conditions, the difference in the coefficient of thermal expansion between the insulating layer and the silicon substrate will cause the metal core to expand under constraint, thereby inducing thermal stress. At the same time, based on the feasibility requirements of the via filling process, the metal conductor (61) is frustum-shaped and is sequentially wrapped by the annular diffusion barrier layer (62) and the dielectric isolation layer (63). In this embodiment, the upper surface diameter of the metal conductor (61) is 10 μm, the lower surface diameter is 8 μm, the thickness of the diffusion barrier layer (62) is 5 nm, and the thickness of the dielectric isolation layer (63) is 0.5 μm.
[0032] In this embodiment 1, the heat flux density on both the upper and lower surfaces of the heat dissipation structure is set to 75 W / cm². 2 At a flow rate of 2.8 m / s, the initial temperature is 293.15 K. Compared with the traditional rectangular channel heat dissipation structure, the maximum temperature on the top and bottom surfaces of this heat dissipation structure is reduced by 12.9 K, the average temperature is reduced by 9.85 K, and the maximum thermal stress around the TSV, i.e. the maximum von Mises equivalent stress, is reduced by 34.32 MPa.
[0033] like Figure 5 , 6 As shown in Figures 7 and 8, Examples 2, 3, 4, and 5 respectively adopted elliptical, teardrop-shaped, trapezoidal, and rhomboid needle ribs. The different shapes of the needle ribs will affect the position of the mainstream separation point, thereby affecting the area of the downstream vortex region and the pressure drop of the channel, while having little effect on the temperature and thermal stress of the structure.
[0034] In summary, those skilled in the art should understand that the embodiments of this utility model are not limited to the foregoing examples, and the foregoing examples and description are only used to illustrate its design principles. Several modifications and improvements can be made to this utility model without departing from its essence and scope, and all such changes should fall within the legal protection scope defined by the claims and their equivalents.
Claims
1. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses, characterized in that, The device includes a heat dissipation structure body (1), chips (2) on the upper and lower surfaces of the heat dissipation structure body, the heat dissipation structure body being a cuboid structure, the cuboid structure having several parallel microchannels (3) for cooling working fluid to flow along the length of the cuboid, the microchannels being equidistantly distributed along the width of the cuboid; the space between adjacent microchannels (3) is a channel wall; each microchannel has multiple semi-elliptical recesses (4) on the sidewalls on the left and right sides, i.e., the sidewalls corresponding to the channel walls, multiple semi-elliptical recesses are evenly spaced along the length of the sidewalls, and the semi-elliptical recesses on the left and right sides are respectively opposite each other, each pair of two semi-elliptical recesses opposite each other is denoted as . The recess is the full long axis of the semi-elliptical recess along the length of the cuboid, the short half axis along the width of the cuboid, and the semi-elliptical concave cylinder along the height of the cuboid. A needle rib (5) is set at the position of each recess in the microchannel (3). The length direction of the needle rib is consistent with the height direction of the cuboid, and the position of the needle rib is close to the upstream of the recess. A through-silicon via (TSV) (6) is provided at the position of the channel wall. The length of the through-silicon via (TSV) extends through the height of the cuboid until there are micro-bumps (7) on the upper and lower surfaces of the cuboid, that is, there are micro-bumps (7) on the upper and lower surfaces of the heat dissipation structure body. The micro-bumps are used to realize the electrical interconnection between the chip (2) and the heat dissipation structure body (1).
2. The 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 1, characterized in that, Depending on the requirements, through-silicon vias (TSVs) are also provided in different pin ribs, and corresponding micro-protrusions (7) are also provided on the upper and lower surfaces of the heat dissipation structure body; the through-silicon vias (TSVs) are located inside the pin ribs.
3. The 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 1, characterized in that, The needle rib is a type of needle with a cross-section that is circular, teardrop-shaped, rhomboid, elliptical, or trapezoidal.
4. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 1, characterized in that, The through-silicon via (TSV) is encapsulated by a metal conductor (61), a diffusion barrier layer (62), and a dielectric isolation layer (63) arranged sequentially from the center outwards.
5. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 4, characterized in that, The through-silicon via (TSV) is truncated cone-shaped, and the corresponding metal conductor is also truncated cone-shaped. The height of the truncated cone is along the height direction of the cuboid structure. The side of the truncated cone-shaped metal conductor is successively wrapped by a diffusion barrier layer and a dielectric isolation layer.
6. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 1, characterized in that, The width of the microchannel itself, i.e. the portion without the semi-elliptical recess, is 100 μm, the corresponding channel wall width is 100 μm, and the microchannel height is 200 μm.
7. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 1, characterized in that, The semi-elliptical cavity has a semi-major axis of 100μm, a semi-minor axis of 10-60μm, a height of 200μm, a dimension of 25-30μm in the direction of the needle rib cross section, a needle rib height of the same as the microchannel height, and a spacing of 400μm between adjacent needle ribs along the length of the microchannel.
8. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 1, characterized in that, In a through-silicon via (TSV), the diameters of the upper and lower surfaces of the metal conductor are 10-20 μm, with the lower surface diameter being smaller than the upper surface diameter. The diffusion barrier layer has a thickness of 5-50 nm, and the dielectric isolation layer has a thickness of 0.1-1 μm.
9. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 1, characterized in that, One end of the microchannel is the inlet, and the other end is the outlet. The working fluid is deionized water.
10. A 3D-IC interlayer low thermal stress microchannel heat dissipation structure based on the synergy of needle ribs and semi-elliptical recesses as described in claim 4, characterized in that, The material of the heat dissipation structure body is silicon; The metal conductor is copper or tungsten, the diffusion barrier layer is titanium nitride or tantalum nitride, and the dielectric isolation layer is silicon dioxide or silicon nitride.