Packaging structure

Abstract

The application provides a packaging structure, comprising a bridge chip, a rewiring layer, the rewiring layer comprising a metal layer, the rewiring layer being arranged above the bridge chip and electrically connected with the bridge chip, a first chip arranged above the rewiring layer and electrically connected with the bridge chip through the rewiring layer, and a second chip arranged above the rewiring layer and electrically connected with the bridge chip through the rewiring layer, wherein the rewiring layer between the first chip and the second chip forms an intermediate region, at least one metal layer is arranged in the intermediate region, and each metal layer comprises at least one aperture. The application has the advantages that the exhaust performance of the rewiring layer between the chips above the bridge chip is improved, the popcorn structure of the rewiring layer in the region due to the accumulation of water vapor is avoided, the combination degree of the lines and the dielectric material in the rewiring layer is improved, and the structural strength of the product is improved.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a packaging structure. Background Technology

[0002] In semiconductor packaging, bridge chips are key components for achieving high-density interconnects and multi-chip integration, especially widely used in 2.5D / 3D advanced packaging technologies. Existing technologies embed bridge chips within silicon interposers, connecting multiple chips (such as CPUs, GPUs, HBMs, etc.) above them via through-silicon vias (TSVs) and microbumps. This provides high-bandwidth, low-latency inter-chip interconnects, replacing traditional PCB traces.

[0003] Figure 1 A schematic diagram of a prior art packaging structure is shown. Figure 2 As shown Figure 1 The diagram shows a top view of a prior art packaging structure. Figure 3 As shown Figure 1 The diagram shows a top view of the metal and circuit layers of a prior art packaging structure. Figure 1-3 As shown, the redistribution layer 902 is disposed above the bridging chip 901, and the first chip 903 and the second chip 904 are respectively disposed above the redistribution layer 902. The first chip 903 and the second chip 904 are electrically connected to the bridging chip 901 through the redistribution layer 902. The first molding layer 905 covers the upper surfaces of the first chip 903, the second chip 904, and the redistribution layer 902, and the second molding layer 906 covers the bridging chip 901; wherein, as... Figure 2 and Figure 3 As shown, a plate-shaped metal layer 902a is provided in the redistribution layer 902 of the central region A located below the first chip 903 and the second chip 904. The metal layer 902a is used to improve the structural strength of the package structure. A drawback of the prior art is that because the metal layer 902a covers the central region A, moisture generated during the manufacturing process due to heating cannot be fully discharged, resulting in a popcorn-like structure beneath the metal layer 902a. This popcorn-like structure can easily lead to cracks or delamination in the package structure, affecting product performance and yield.

[0004] In summary, there is a need in the art to provide a packaging structure that can overcome the shortcomings of the prior art. Utility Model Content

[0005] This application provides a packaging structure that can solve the problems of the prior art. The objective of this application is achieved through the following technical solution.

[0006] One embodiment of this application provides a packaging structure including a bridging chip; a redistribution layer including a metal layer, the redistribution layer being disposed above the bridging chip and electrically connected to the bridging chip; a first chip disposed above the redistribution layer and electrically connected to the bridging chip via the redistribution layer; and a second chip disposed above the redistribution layer and electrically connected to the bridging chip via the redistribution layer; wherein the redistribution layer located between the first chip and the second chip forms an intermediate region, at least one metal layer is disposed in the intermediate region, and each metal layer includes at least one aperture.

[0007] In some alternative implementations, according to the packaging structure provided by one of the above embodiments of this application, the first chip is communicatively connected to the second chip through a redistribution layer and a bridging chip.

[0008] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes a first molding layer that covers the first chip and the second chip.

[0009] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the metal layer is a dummy circuit layer, and the metal layer is electrically isolated from the bridge chip, the first chip, and the second chip layer.

[0010] In some optional embodiments, according to the packaging structure provided by one embodiment of the present application, the redistribution layer further includes a circuit layer, and at least one circuit layer is provided below the first chip and the second chip layers respectively, and the first chip and the second chip are respectively communicatively connected to the bridging chip through the circuit layer.

[0011] In some alternative embodiments, the packaging structure provided according to one embodiment of this application above is electrically isolated between the metal layer and the circuit layer.

[0012] In some alternative embodiments, the packaging structure provided according to one embodiment of this application above has the same number of metal layers in the intermediate region as the number of circuit layers beneath the first chip and the second chip respectively.

[0013] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application, wherein the apertures are holes, and the difference between the metal coverage of each metal layer and the metal coverage of the circuit layer located on the same layer as the metal layer is within 5%.

[0014] In some alternative embodiments, the encapsulation structure provided according to one of the above embodiments of this application has pores in the shape of holes or slits.

[0015] In some alternative embodiments, the packaging structure provided according to one embodiment of this application has a patterned metal layer.

[0016] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second molding layer, the second molding layer including conductive pillars, the second molding layer covering the bridging chip, a redistribution layer disposed above the second molding layer, and the conductive pillars penetrating the second molding layer and electrically connected to the second redistribution layer.

[0017] The advantages of the packaging structure according to the embodiments of this application are: improved ventilation performance of the redistribution layer between chips above the bridging chip; avoidance of popcorn structure caused by moisture accumulation in the redistribution layer in this area; improved bonding between the lines and dielectric materials in the redistribution layer; improved structural strength of the product; and improved product yield and reduced cost. Attached Figure Description

[0018] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0019] Figure 1 A schematic diagram of a prior art packaging structure is shown;

[0020] Figure 2 As shown Figure 1 A schematic diagram of region A in a prior art packaging structure is shown;

[0021] Figure 3 As shown Figure 1 A top view of the metal and circuit layers of a prior art packaging structure is shown.

[0022] Figure 4 A schematic diagram of a packaging structure according to an embodiment of this application is shown;

[0023] Figure 5 As shown Figure 4 A schematic diagram of the area marked B in the packaging structure according to an embodiment of this application;

[0024] Figure 6 As shown Figure 4 The diagram shown is a top view of the metal layer and circuit layer of a packaging structure according to an embodiment of this application;

[0025] Figure 7-1 , Figure 7-2 and Figure 7-3 A schematic diagram of the manufacturing process of a packaging structure according to an embodiment of this application is shown;

[0026] Figure 8 A top view schematic diagram of the metal layer and apertures of a packaging structure according to an embodiment of this application is shown.

[0027] Labels and component names: 1-Bridging chip, 2-Rewiring layer, 3-First chip, 4-Second chip, 5-First molding layer, 6-Second molding layer, 7-Second electrical connector, 11-First electrical connector, 12-First insulating layer, 21-Intermediate area, 22-Circuit layer, 23-Metal layer, 24-Vacuum, 25-Conductive via, 31-Third electrical connector, 41-Fourth electrical connector, 61-Conductive pillar, 110-Carrier plate, 102-Release film, 103-First dielectric layer. 104-Conductive post, 105-Bridge chip, 105a-First electrical connector, 106-Circuit layer, 106a-Second electrical connector, 107-Metal layer, 108-Aperture, 109-Second dielectric layer, 110-Filling material, 111-Third electrical connector, 112-First molding layer, 113-Electronic component, 901-Bridge chip, 902-Rewiring layer, 903-First chip, 904-Second chip, 905-First molding layer, 902a-Metal layer. Detailed Implementation

[0028] The specific embodiments of this application are described below with reference to the accompanying drawings and examples. Through the content described in this specification, those skilled in the art can clearly and completely understand the technical solution, the technical problem solved, and the resulting technical effects of this application. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, for ease of description, only the parts related to this application are shown in the accompanying drawings.

[0029] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0030] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0031] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0032] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0033] The electrical connectors mentioned in this article can be pads / solder pads, bumps, or combinations thereof. Bumps can be, for example, gold bumps (typically rectangular, made of gold), solder bumps (typically round, made of copper and tin), or pillar bumps (typically octagonal or polygonal, made of copper and tin or lead and tin).

[0034] The dielectric layer / dielectric material / substrate mentioned in this article may include organic and / or inorganic materials. Organic materials may include, for example, polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc. Inorganic materials may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0035] The carrier plate in this article can be circular or square; its material can be organic: polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), and / or, inorganic: silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0036] The molding compound described in this article can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0037] The electrical connectors mentioned in this article can be pads or bumps. Among them, bumps can be, for example, gold bumps (usually rectangular, made of gold), solder bumps (usually round, made of copper and tin), or pillar bumps (usually octagonal or polygonal, made of copper and tin or lead and tin).

[0038] The redistribution layer described herein can be a redistribution layer composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies, and this disclosure does not specifically limit this. For example, redistribution layers can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0039] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Figure 4 A schematic diagram of a packaging structure according to an embodiment of this application is shown. Figure 5 As shown Figure 4 The diagram shown illustrates the area labeled B in the encapsulation structure according to one embodiment of this application. Figure 6 As shown Figure 4 The diagram shown is a top view of the metal layer and circuit layer of a package structure according to an embodiment of this application. Figure 4 , Figure 5 and Figure 6As shown, the package structure includes a bridging chip 1; a redistribution layer 2, which includes a metal layer 23, and is disposed above the bridging chip 1 and electrically connected to it; a first chip 3, which is disposed above the redistribution layer 2 and electrically connected to the bridging chip 1 via the redistribution layer 2; and a second chip 4, which is disposed above the redistribution layer 2 and electrically connected to the bridging chip 1 via the redistribution layer 2. The redistribution layer 2 located between the first chip 3 and the second chip 4 forms an intermediate region 21, and at least one metal layer 23 is disposed in the intermediate region 21. Each metal layer 23 includes at least one pore 24. The pore 24 is used to drain moisture generated in the intermediate region 21 during the manufacturing process.

[0041] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the first chip 3 is communicatively connected to the second chip 4 through the redistribution layer 2 and the bridging chip 1.

[0042] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a first molding layer 5, which covers the first chip 3 and the second chip 4.

[0043] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the metal layer 23 is a dummy circuit layer, and the metal layer 23 is electrically isolated from the bridge chip 1, the first chip 3 and the second chip 4.

[0044] In some optional embodiments, according to the packaging structure provided by one embodiment of the present application, the redistribution layer 2 further includes a circuit layer 22, and at least one circuit layer 22 is provided below the first chip 3 and the second chip 4, respectively, and the first chip 3 and the second chip 4 are respectively connected to the bridging chip 1 through the circuit layer 22.

[0045] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application is wherein the metal layer 23 is electrically isolated from the circuit layer 22.

[0046] In some optional embodiments, according to the packaging structure provided by one embodiment of this application, the number of metal layers 23 in the intermediate region 21 is the same as the number of circuit layers 22 below the first chip 3 and the second chip 4 respectively. In a side view, the circuit layers 22 and metal layers 23 located on the same layer have approximately the same height and are essentially on the same plane; adjacent circuit layers 22 can be electrically connected through conductive vias 25.

[0047] In some alternative embodiments, according to the packaging structure provided by one embodiment of this application, the aperture 24 is a hole, and the difference between the metal coverage of each metal layer 23 and the metal coverage of the circuit layer 22 located on the same layer as the metal layer 23 is within 5%. Metal coverage refers to the ratio between the area occupied by metal or wiring in the metal layer 23 or circuit layer 22 and the total area of ​​the metal layer 23 or circuit layer 22.

[0048] In some alternative embodiments, the encapsulation structure provided according to one embodiment of this application, wherein the aperture 24 is in the shape of a hole or a slit. For example: Figure 8 As shown, in one embodiment, the pores 24 on the metal layer 23 are square holes with a side length of 30 micrometers, and the spacing between the pores is about 30 micrometers.

[0049] In some alternative embodiments, the packaging structure provided according to one embodiment of this application, wherein, as... Figure 6 As shown, the metal layer 23 has a patterned shape.

[0050] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second molding layer 6, the second molding layer 6 including conductive pillars 61, the second molding layer 6 covering the bridging chip 1, the redistribution layer 2 being disposed above the second molding layer 6, and the conductive pillars 61 penetrating the second molding layer 6 and being electrically connected to the second redistribution layer.

[0051] In some optional embodiments, according to the packaging structure provided by one embodiment of the present application, the bridging chip 1 includes a first electrical connector 11 and a first insulating layer 12. In a side view, the first electrical connector 11 and the first insulating layer 12 are both located on the top of the bridging chip 1. The first electrical connector 11 extends upward from the first insulating layer 12, and the redistribution layer 2 is electrically connected to the first electrical connector 11.

[0052] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second electrical connector 7 disposed below the second molding layer 6, and the second electrical connector 7 is electrically connected to the second rewiring layer 2 via a conductive post 61.

[0053] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the first chip 3 includes a third electrical connector 31, the second chip 4 includes a fourth electrical connector 41, the first chip 3 is electrically connected to the redistribution layer 2 through the third electrical connector 31, and the second chip 4 is electrically connected to the redistribution layer 2 through the fourth electrical connector 41.

[0054] Figure 7-1 , Figure 7-2 and Figure 7-3 A schematic diagram illustrating the manufacturing process of a packaging structure according to an embodiment of this application is shown. Figure 7-1 , Figure 7-2 and Figure 7-3 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0055] Step 1001: Provide a carrier plate 101, and place a release film 102 on the carrier plate 101;

[0056] Step 1002: A first dielectric layer 103 is disposed above the release film 102, and a conductive pillar 104 is disposed above the first dielectric layer 103, with the bottom of the conductive pillar 104 passing through the first dielectric layer 103.

[0057] Step 1003: A bridging chip 105 is disposed above the first dielectric layer 103; wherein the top of the bridging chip 105 is provided with a first electrical connector 105a;

[0058] Step 1004: Use the first molding seal 112 to cover the conductive pillar 104 and the bridging chip 105, and grind the top of the first molding seal 112 so that the top of the conductive pillar 104 and the first electrical connector 105a are exposed from the upper surface of the first molding seal 112.

[0059] Step 1005: A circuit layer 106 and a metal layer 107 are provided above the first mold sealing layer 112; wherein, the circuit layer 106 is connected to the conductive post 104 and the first electrical connector 105a respectively, and the metal layer 107 is provided with a hole 108.

[0060] Step 1006: Cover the circuit layer 106 and the metal layer 107 with the second dielectric layer 109, and place the electronic component 113 above the second dielectric layer 109; wherein the electronic component 113 and the circuit layer 106 are electrically connected through the second electrical connector 106a, and the metal layer 107 is located below the space between adjacent electronic components 113.

[0061] Step 1007: Fill the space between the electronic component 113 and the second dielectric layer 109 with the filler material 110;

[0062] Step 1008: Use the second sealing layer 114 to cover the upper surface of the electronic component 113, the filler material 110, and the second dielectric layer 109;

[0063] Step 1009: Remove carrier plate 101 and release film 102; and

[0064] Step 1010: A third electrical connector 111 is disposed below the first dielectric layer 103; wherein the third electrical connector 111 is electrically connected to the conductive post 104.

[0065] Those skilled in the art will understand that the structure in this application, which involves creating pores in the metal layer to expel moisture, can be applied not only to fanout platforms but also to structures such as 2.5D interposers and embedded multi-chip interconnect bridges (EMIBs).

[0066] The advantages of the packaging structure according to the embodiments of this application are: improved ventilation performance of the redistribution layer between chips above the bridging chip; avoidance of popcorn structure caused by moisture accumulation in the redistribution layer in this area; improved bonding between the lines and dielectric materials in the redistribution layer; improved structural strength of the product; and improved product yield and reduced cost.

[0067] Although this application has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to limit the application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the scope of protection of this application as defined by the claims. Differences may exist between the technical representation in this application and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The specification and illustrations should be considered illustrative rather than restrictive, and modifications can be made to suit the purpose and spirit of this application, all of which are within the scope of the claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be rearranged, subdivided, or arranged to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the application.

Claims

1. A packaging structure, characterized in that, include: Bridge chip; A redistribution layer, the redistribution layer including a metal layer, the redistribution layer being disposed above the bridge chip and electrically connected to the bridge chip; A first chip is disposed above the redistribution layer and is electrically connected to the bridging chip through the redistribution layer. The second chip is disposed above the redistribution layer and is electrically connected to the bridging chip through the redistribution layer. The redistribution layer located between the first chip and the second chip forms an intermediate region, and at least one metal layer is disposed in the intermediate region, each of the metal layers including at least one aperture.

2. The packaging structure according to claim 1, characterized in that, The first chip communicates with the second chip through the redistribution layer and the bridging chip.

3. The packaging structure according to claim 1, characterized in that, The packaging structure further includes a first molding layer, which covers the first chip and the second chip.

4. The packaging structure according to claim 1, characterized in that, The packaging structure further includes a second molding layer, which includes conductive pillars and covers the bridging chip. The redistribution layer is disposed above the second molding layer, and the conductive pillars penetrate the second molding layer and are electrically connected to the second redistribution layer.

5. The packaging structure according to claim 1, characterized in that, The metal layer is a dummy circuit layer, and the metal layer is electrically isolated from the bridge chip, the first chip, and the second chip layer.

6. The packaging structure according to claim 1, characterized in that, The rewiring layer further includes a circuit layer. At least one circuit layer is provided below the first chip and the second chip layers respectively. The first chip and the second chip are respectively connected to the bridging chip through the circuit layer.

7. The packaging structure according to claim 6, characterized in that, The metal layer is electrically isolated from the circuit layer.

8. The packaging structure according to claim 6, characterized in that, The number of metal layers in the intermediate region is the same as the number of circuit layers below the first chip and the second chip, respectively.

9. The packaging structure according to claim 6, characterized in that, The pores are holes, and the difference between the metal coverage of each metal layer and the metal coverage of the circuit layer located on the same layer as the metal layer is within 5%.

10. The packaging structure according to claim 1, characterized in that, The pores are in the shape of holes or slits.

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