Semiconductor structure and electronic device

Abstract

The present disclosure relates to a semiconductor structure and an electronic device, the semiconductor structure comprising a substrate and a storage IO module, the substrate comprising a wiring layer, the storage IO module being arranged on the substrate and comprising a plurality of stacked storage chips and an IO chip arranged between the storage chips and the substrate, the storage chips and the IO chip being electrically connected to the wiring layer. Thus, the IO chip and the plurality of storage chips can be stacked, and thus, compared with a structure in the related art in which the plurality of storage chips are tiled on the outer periphery of a logic chip and the IO chip is arranged between the storage chips and the logic chip, the semiconductor structure provided by the present disclosure has the plurality of storage chips and the IO chip stacked and integrated, which can not only improve the storage density by the plurality of stacked storage chips, but also reduce the packaging volume of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and electronic device. Background Technology

[0002] In related technologies, the mainstream approach to connecting GDDR (Graphics Double Data Rate Synchronous Dynamic Random Access Memory) chips and logic chips in semiconductor structures is to directly solder them onto a PCB (Printed Circuit Board). This means GDDR chips are directly soldered onto the PCB surrounding the GPU using SMT (Surface Mount Technology), forming a flat layout. With the development of AI technology, the overall storage capacity requirements of semiconductor structures are increasing. However, in the aforementioned semiconductor structures, individual GDDR chips have low storage density. Furthermore, multiple GDDR chips require multiple input / output chips around the GPU, resulting in low storage density and large package size, making them unsuitable for scenarios with high storage density and small package size requirements. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor structure and an electronic device that has high storage density and small package size, which can be adapted to scenarios with high storage density requirements and small size, so as to at least partially solve the related technical problems.

[0004] To achieve the above objectives, according to a first aspect of this disclosure, a semiconductor structure is provided, comprising: a substrate including a wiring layer; a memory I / O module disposed on the substrate, including a plurality of stacked memory chips and an I / O chip disposed between the memory chips and the substrate, wherein the memory chips and the I / O chip are electrically connected to the wiring layer.

[0005] Optionally, each of the memory chips is provided with a connection portion, and the memory chip is electrically connected to the wiring layer through the connection portion.

[0006] Optionally, in the stacking direction, the IO chip and each of the memory chips stacked on the upper layer are staggered, and the connection portion of the memory chip is located at the staggered position.

[0007] Optionally, a plurality of the memory chips are electrically connected to the wiring layer via leads; and / or The I / O chip is electrically connected to the wiring layer via bumps.

[0008] Optionally, at least some of the adjacent memory chips are electrically connected to the connection portion via leads.

[0009] Optionally, the semiconductor structure further includes a package for encapsulating the plurality of memory chips and the input / output units.

[0010] Optionally, the semiconductor structure further includes a logic chip disposed on the substrate; the storage I / O module is disposed on both sides of the logic chip and is electrically connected to the logic chip through the wiring layer.

[0011] Optionally, there are multiple storage I / O modules, and in the first direction, the multiple storage I / O modules are respectively located on both sides of the logic chip.

[0012] Optionally, the memory chip is a GDDR chip, and / or The logic chip is a GPU chip.

[0013] According to a second aspect of this disclosure, an electronic device is provided, comprising the semiconductor structure described above.

[0014] The semiconductor structure disclosed herein, through the above technical solution, includes a substrate and a memory I / O module. The memory I / O module includes multiple stacked memory chips, with I / O chips positioned between the memory chips and the substrate. This allows for the stacking of I / O chips and multiple memory chips. Compared to related technologies where multiple memory chips are laid flat around a logic chip with I / O chips positioned between them, the semiconductor structure provided in this disclosure integrates multiple memory chips and I / O chips. This not only increases storage density through the stacked memory chips but also reduces the package size of the semiconductor structure. Therefore, the semiconductor structure provided in this disclosure is suitable for scenarios requiring high storage density and small package size.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the accompanying drawings...

[0017] Figure 1 This is a top view of the semiconductor structure provided in this application.

[0018] Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure provided in this application.

[0019] Figure 3 A schematic diagram of a cross-section of a semiconductor structure in related technologies.

[0020] Explanation of reference numerals in the attached figures 1-Substrate; 2-Wiring layer; 3-Storage I / O module; 31-Storage chip; 32-I / O chip; 33-Connection part; 4-Logic chip; 5-Lead; 6-Bump; 7-Package. Detailed Implementation

[0021] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0022] In this disclosure, unless otherwise stated, directional terms such as "first direction" are used for reference. Figure 1 In the X direction, the "second direction" can be referenced. Figure 1 In the Y direction, the "stack direction" can be referenced. Figure 2 In the Z-direction, "inner" and "outer" refer to the contours of the corresponding components themselves. The terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not indicate sequence or importance. When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0023] In related technologies, the mainstream approach to connecting GDDR (Graphics Double Data Rate Synchronous Dynamic Random Access Memory) chips and logic chips in semiconductor structures is to directly solder them onto a PCB (Printed Circuit Board). This means that GDDR chips are directly soldered onto the PCB surrounding the GPU using SMT (Surface Mount Technology), forming a flat layout. For example... Figure 3As shown, multiple GDDR memory chips 31 are disposed on at least one side of a logic chip 4. The GDDR memory chips 31 and the logic chip 4 are electrically connected to the wiring layer of the substrate 1, and multiple I / O chips are disposed between the multiple GDDR memory chips 31 and the logic chip 4. However, in the above semiconductor structure, the storage density of a single GDDR chip is low, and the area on the substrate 1 is limited. The flat arrangement of multiple GDDR memory chips 31 and I / O chips 32 limits both the storage density of the semiconductor structure and increases the package size of the semiconductor structure. As a result, the semiconductor structure in the related technology is difficult to adapt to scenarios with high storage density requirements and small package size requirements, such as 8K content creation, local large model inference, and industrial-grade 3D rendering.

[0024] To achieve the above objectives, such as Figure 1 and Figure 2 As shown, according to a first aspect of the present disclosure, a semiconductor structure is provided, including: a substrate 1 and a memory I / O module 3, wherein the substrate 1 includes a wiring layer 2, the memory I / O module 3 is disposed on the substrate 1, the memory I / O module 3 includes a plurality of stacked memory chips 31 and I / O chips 32 disposed between the memory chips 31 and the substrate 1, and the memory chips 31 and I / O chips 32 are electrically connected to the wiring layer 2.

[0025] The semiconductor structure disclosed herein includes a substrate 1 and a memory I / O module 3. The memory I / O module 3 includes multiple stacked memory chips 31, and I / O chips 32 are disposed between the memory chips 31 and the substrate 1. Thus, the I / O chips 32 and multiple memory chips 31 can be stacked. Compared with the related technology, where multiple memory chips 31 are laid flat on the periphery of a logic chip 4 and I / O chips are disposed between the memory chips 31 and the logic chip 4, the semiconductor structure provided herein integrates multiple memory chips 31 and I / O chips 32. This not only increases the storage density by stacking multiple memory chips 31, but also reduces the area occupied on the substrate 1 by integrating the memory chips 31 and I / O chips 32. This allows more memory I / O modules 3 to be arranged on the same area of ​​the substrate 1. Furthermore, the stacking of I / O chips 32 and multiple memory chips 31 further reduces the package size of the semiconductor structure, enabling the semiconductor structure to adapt to scenarios with high storage density and small package size requirements.

[0026] It is understood that the aforementioned substrate 1 can be a packaging substrate, which includes multiple wiring layers 2, insulating layers and solder mask layers. Each wiring layer 2 is electrically connected through vias. The wiring layer 2 is used to transmit current and signals. The wiring layer 2 can be copper foil. The insulating layer is usually disposed between adjacent wiring layers 2 to isolate the wiring layer 2 and control the signal impedance. The solder mask layer is usually disposed on both sides of the packaging substrate.

[0027] In some feasible implementations, each memory chip 31 is provided with a connection portion 33, through which the memory chip 31 is electrically connected to the wiring layer 2. The connection portion 33 may include an RDL (Redistribution Layer), which, by creating a patterned metal layer on top of the dielectric layer, rearranges the chip's input / output (I / O) ports. It can extend I / O contacts originally located at the edges or perimeter of the chip to the chip's surface through semiconductor processes, expanding the layout to new, more spacious areas and forming a planar array arrangement, thereby increasing connection density and reducing packaging complexity.

[0028] In some feasible implementations, the capacity of a single memory chip 31 is fixed, and the total capacity can be directly increased by adding more memory chips 31. For example, the capacity of a single memory chip 31 is 2-3 GB (gigabytes). Figure 1 In this configuration, there are four storage chips 31, resulting in a total storage capacity of 8-12GB for a single storage I / O module 3. Of course, the 2-3GB capacity of the storage chips 31 is illustrative; in other implementations, the capacity of the storage chips 31 can be 4GB, 6GB, or 8GB, etc. That is, the capacity of the storage chips 31 can be selected according to specific operating requirements.

[0029] In some feasible embodiments, the I / O chip and the memory chips 31 stacked on top of it are staggered in the stacking direction, and the connection portion 33 of the memory chip 31 is located at the staggered position. For example... Figure 2 As shown, the stacking direction can be referenced. Figure 2In the Z direction, a storage I / O module 3 includes four storage chips 31. The lowest storage chip 31 is located on the I / O chip 32. The I / O chip 32 is electrically connected to the substrate 1. The lowest storage chip 31 and the I / O chip 32 are staggered. The lowest storage chip 31 is electrically connected to the wiring layer 2 of the substrate 1 through a corresponding connection part 33. The next lower storage chip 31 is located above the lowest storage chip 31. The next lower storage chip 31 is staggered with the lowest storage chip 31. At this time, the connection part 33 of the next lower storage chip 31 can be located at the staggered position, so as to facilitate the electrical connection of the next lower storage chip 31 to the wiring layer 2 of the substrate 1 through the connection part 33. Of course, a second-upper-layer memory chip 31 is provided above the second-lower-layer memory chip 31. The second-upper-layer memory chip 31 and the second-lower-layer memory chip 31 are arranged in a staggered manner. The connection portion 33 of the second-upper-layer memory chip 31 can be provided at the staggered position, so as to facilitate the electrical connection of the second-upper-layer memory chip 31 to the wiring layer 2 of the substrate 1 through the corresponding connection portion 33. Similarly, a top-layer memory chip 31 is provided above the second-upper-layer memory chip 31. The second-upper-layer memory chip 31 and the top-layer memory chip 31 are arranged in a staggered manner. The connection portion 33 of the top-layer memory chip 31 is located at the staggered position, so as to facilitate the electrical connection of the top-layer memory chip 31 to the wiring layer 2 of the substrate 1 through the corresponding connection portion 33.

[0030] It is understandable that the staggered arrangement of the four memory chips 31 in the stacking direction described above can be as follows: Figure 2 As shown, there is a partial overlap between adjacent upper-layer and lower-layer memory chips 31, and the upper-layer memory chips 31 have partially suspended misaligned areas. Here, the misaligned areas of the four memory chips 31 are located on the same side, forming a stepped misaligned arrangement along one side. That is, the misaligned areas of the four memory chips 31 are all located on the same side, which allows for a more flexible arrangement of the memory chips 31. Compared with a neat and symmetrical arrangement, it can accommodate more chips and make better use of the space in the suspended areas of the memory chips 31. For example, the side of the upper-layer memory chip 31 facing the substrate 1 of two adjacent memory chips 31 can be processed to form a connection part 33, so that the upper-layer memory chip 31 can be electrically connected to the substrate 1 through the connection part 33. In addition, it can provide more flexibility and space for wiring. The gaps formed after the misalignment of the memory chips 31 can be used to plan the routing of signal lines, power lines or ground lines more rationally, reducing wiring difficulty. At the same time, it is also conducive to achieving shorter signal paths and reducing signal delay. Of course, when multiple memory chips 31 are packaged, a stepped staggered arrangement is formed along one side, which can reduce the requirement for precise alignment of multiple memory chips 31, and reduce the packaging process difficulty and cost.

[0031] Of course, it is understandable that, such as Figure 2The structure shown above, in which the four memory chips 31 are staggered in the stacking direction, is schematic. In other embodiments, the four memory chips 31 may also have a partially overlapping area between adjacent upper and lower memory chips 31, and there may be suspended staggered areas on both sides of the upper memory chip 31. That is, the size of the upper memory chip 31 is larger than that of the lower memory chip 31, thereby forming a staggered area on the two sides of the upper memory chip 31. In other words, the upper memory chip 31 may be provided with two connecting parts 33 to connect with the wiring layer 2 of the substrate 1.

[0032] In some feasible implementations, the IO chip 32 can be electrically connected to the wiring layer 2 via bumps 6, and the memory chip 31 can be electrically connected to the wiring layer 2 via leads 5. For example... Figure 2 As shown, the IO chip 32 is electrically connected to the wiring layer 2 of the substrate 1 via bumps 6. This connection allows the IO chip 32 to have a shorter and lower impedance signal transmission path, reducing signal reflection and loss, and ensuring high-speed and stable data transmission. Furthermore, the bump connection provides a larger contact area, which is beneficial for the stable transmission of power and ground signals of the IO chip 32. In addition, there are four memory chips 31 arranged in a staggered manner. The bottom-layer memory chip 31 is also staggered with its corresponding IO chip 32. Each memory chip 31 has a connection portion 33 at the suspended staggered position. The connection portion 33 is electrically connected to the wiring layer 2 of the substrate 1 via leads 5. The wire bonding method is relatively flexible, allowing for more free adjustment of the wiring according to the layout of the memory chip 31 and the signal direction, which helps optimize the signal topology and reduce crosstalk between signals. Furthermore, by rationally planning the length and direction of the leads, signal delay can be reduced, signal integrity improved, and efficient data transmission of the memory chip 31 ensured. In addition, the memory chip 31 is electrically connected to the wiring layer 2 of the substrate 1 via the lead 5, which can reduce the production cost of the semiconductor structure.

[0033] It is understandable that when the aforementioned IO chip 32 is connected to the substrate 1 via the bump 6, the bump 6 can be a copper ball bump or a copper pillar bump.

[0034] To facilitate the electrical connection between the memory chip 31 and the substrate 1, multiple RDL layers can be provided on the substrate 1 to cooperate with the corresponding memory chip 31, so that the memory chip 31 and the wiring layer 2 of the substrate 1 can be electrically connected through the lead 5.

[0035] In some feasible implementations, at least partially adjacent memory chips 31 are electrically connected via leads 5. For example... Figure 2 As shown, Figure 2The number of memory chips 31 is four. The connection portions 33 of the next lower layer memory chip 31 and the next upper layer memory chip 31 are electrically connected by leads, and the connection portions 33 of the next upper layer memory chip 31 and the top layer memory chip 31 are electrically connected by leads 5. In this way, the transmission distance of data and control signals between adjacent memory chips 31 can be shortened. Compared with transmission through a bypass via the substrate 1, direct connection by leads 5 can reduce signal transmission delay, reduce signal attenuation and distortion during transmission, and improve the speed and accuracy of data transmission. In addition, the shorter leads 5 can also effectively reduce electromagnetic radiation and signal interference. That is, the connection of leads 5 between adjacent memory chips 31 can also reduce mutual interference between signal components, ensure signal integrity, and thus improve the stability and reliability of the semiconductor structure.

[0036] Optionally, the semiconductor structure also includes a package 7 for encapsulating multiple memory chips 31 and I / O chips 32. For example... Figure 2 As shown, the I / O chip 32 and the four memory chips 31 are encapsulated by a package 7. The package 7 secures the I / O chip 32 and the four memory chips 31 into a single unit, reducing phase shifts caused by vibration and impact between the I / O chip 32 and the memory chips 31, and lowering the risk of lead wire or solder joint breakage. Furthermore, the package 7 prevents the I / O chip 32 and the memory chips 31 from directly contacting the external environment, reducing interference from the external environment and improving the reliability of the I / O chip 32 and the memory chips 31. Of course, the package 7 also allows the I / O chip 32 and the multiple memory chips 31 to be directly connected to the substrate 1 via leads and bumps, eliminating the need for long-distance wiring through the PCB board, thereby reducing signal transmission speed and signal delay between the I / O chip 32 and the memory chips 31.

[0037] It is understood that the number of storage chips 31 is four as an illustration. In other embodiments, the number of storage chips 31 can be selected according to specific operating conditions. For example, the number of storage chips 31 can be eight or twelve.

[0038] In addition, to further improve the integration of the semiconductor structure, in some feasible embodiments, the semiconductor structure also includes a logic chip 4, which is disposed on the substrate 1, and the storage I / O module 3 is disposed on both sides of the logic chip 4 and electrically connected to the logic chip 4 through the wiring layer 2.

[0039] In some feasible implementations, memory chip 31 can be a GDDR chip, and logic chip 4 can be a GPU chip. For example... Figure 1As shown, the storage I / O module 3 includes an I / O chip 32 and four stacked storage chips 31. The I / O chip 32 can be an I / O chip, the storage chip 31 can be a GDDR chip, and the logic chip 4 can be a GPU chip. The GPU chip and the multiple stacked storage chips 31 are all disposed on the substrate 1, and the GPU chip is electrically connected to the wiring layer 2 of the substrate 1. The multiple stacked storage chips 31 are electrically connected to the wiring layer 2 of the substrate 1 through bumps and leads, thereby realizing the interconnection between the GDDR chip and the GPU chip.

[0040] Optionally, there are multiple storage I / O modules 3, and in the first direction, the multiple storage I / O modules 3 are respectively located on both sides of the logic chip 4. Figure 1 As shown, the first direction can be referenced. Figure 1 In the X-direction, there are six storage I / O modules 3. Each storage I / O module 3 includes a corresponding I / O chip 32 and four storage chips 31 stacked on top of the I / O chip 32. Three storage I / O modules 3 form a group, located on opposite sides of the logic chip 4. Specifically, three storage I / O modules 3 are located on the first side of the logic chip 4 in the first direction, and another three are located on the opposite second side. By placing multiple storage I / O modules 3 on both sides of the logic chip 4, the trace lengths from the storage chips 31 in each storage I / O module 3 to the logic chip 4 are made similar, thereby reducing signal timing deviations and ensuring synchronous operation of the storage chips 31 in the multiple storage I / O modules 3.

[0041] Of course, to further reduce the signal timing deviation between the I / O chip 32 and memory chip 31 in the storage I / O module 3 and the logic chip 4, the storage I / O module 3 located on one side of the logic chip 4 and the storage I / O module 3 located on the other side of the logic chip 4 can be arranged symmetrically about the logic chip 4. In this way, by symmetrically arranging the storage I / O modules 3 about the logic chip 4, the trace lengths from the memory chip 31 to the logic chip 4 in the storage I / O module 3 can be equal or approximately equal, thereby reducing signal timing deviation. It should be noted that the equal trace lengths here refer to the consistent physical dimensions of the actual wiring.

[0042] It is understood that the above-mentioned multiple storage I / O modules 3 located on both sides of the logic chip 4 in the first direction are schematic. In other embodiments, such as when the timing deviation requirement is low, the multiple storage I / O modules 3 may be set on only one side of the logic chip 4.

[0043] Furthermore, the aforementioned symmetrical arrangement of the storage I / O module 3 on one side of the logic chip 4 and the storage I / O module 3 on the other side of the logic chip 4 is also illustrative. In other embodiments, the storage I / O modules 3 on both sides of the logic chip 4 can also be arranged asymmetrically. For example, the number of storage I / O modules 3 on both sides of the logic chip 4 can be different, and the trace lengths from the storage I / O modules 3 on both sides of the logic chip 4 to the logic chip 4 can be unequal.

[0044] Optionally, in the first direction, multiple storage I / O modules 3 located on the same side of the logic chip 4 are spaced apart along the second direction, wherein the first direction and the second direction are perpendicular to each other. Figure 1 As shown, the number of storage I / O modules 3 is six, with the first direction reference... Figure 1 In the X direction, the second direction is for reference. Figure 1 In the Y direction, in the first direction, three storage I / O modules 3 are grouped together and located on both sides of the logic chip 4. The three storage I / O modules 3 on the same side are spaced apart along the second direction. In this way, the space outside the logic chip 4 can be fully utilized to arrange the storage I / O modules 3 in a reasonable manner, so as to avoid the layout crowding caused by the dense arrangement of local chips, which can lead to local overheating. At the same time, the regular arrangement can also reduce the wiring complexity of the semiconductor structure, reduce the design workload, reduce manufacturing errors, and improve the yield.

[0045] In some feasible implementations, to improve the reliability of the semiconductor structure, the semiconductor structure may also include a reinforcing ring located around the periphery of multiple memory I / O modules 3. For example, a logic chip 4 and multiple memory I / O modules 3 located on both sides of the logic chip 4 in a first direction are provided on a substrate 1. A reinforcing ring is provided on the substrate 1. The reinforcing ring can be a rectangular ring, which is fitted around the periphery of the multiple memory I / O modules. The height of the reinforcing ring in the thickness direction is higher than that of the logic chip and the memory chip. Thus, by setting the reinforcing ring, the thermal stress caused by the difference in the coefficients of thermal expansion between the logic chip and the memory chip can be offset, avoiding substrate warping, solder joint cracking, or edge chipping of the semiconductor structure. Of course, by setting the reinforcing ring, a physical barrier can also be formed for the logic chip and the memory chip, preventing dust, moisture, and other contaminants from penetrating the semiconductor structure and improving the reliability of the semiconductor structure.

[0046] According to a second aspect of this disclosure, an electronic device is provided, comprising the aforementioned semiconductor structure. The electronic device may include a PCB board, and the semiconductor structure is electrically connected to the PCB board via a ball grid array. It is understood that the electronic device may include, but is not limited to, personal computers, servers, computing devices, intelligent vehicles, etc. Furthermore, it is understood that this electronic device also possesses all the advantages of the aforementioned semiconductor structure, which will not be elaborated upon here.

[0047] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0048] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0049] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, including wiring layer, A storage I / O module is disposed on the substrate and includes a plurality of stacked storage chips and an I / O chip disposed between the storage chips and the substrate. The storage chips and the I / O chip are electrically connected to the wiring layer.

2. The semiconductor structure according to claim 1, characterized in that, Each of the memory chips is provided with a connection portion, and the memory chip is electrically connected to the wiring layer through the connection portion.

3. The semiconductor structure according to claim 2, characterized in that, In the stacking direction, the IO chip and each of the memory chips stacked on the upper layer are staggered, and the connection portion of the memory chip is located at the staggered position.

4. The semiconductor structure according to claim 2, characterized in that, Multiple memory chips are electrically connected to the wiring layer via leads; and / or The IO chip is electrically connected to the wiring layer via bumps.

5. The semiconductor structure according to claim 4, characterized in that, The connection portion is electrically connected to at least some of the adjacent memory chips via leads.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a package for encapsulating a plurality of the memory chips and the I / O chips.

7. The semiconductor structure according to any one of claims 1-6, characterized in that, The semiconductor structure also includes a logic chip disposed on the substrate; the storage I / O module is disposed on both sides of the logic chip and is electrically connected to the logic chip through the wiring layer.

8. The semiconductor structure according to claim 7, characterized in that, The number of storage I / O modules is multiple, and in the first direction, the multiple storage I / O modules are respectively located on both sides of the logic chip.

9. The semiconductor structure according to claim 7, characterized in that, The memory chip is a GDDR chip, and / or The logic chip is a GPU chip.

10. An electronic device, characterized in that, Includes the semiconductor structure described in any one of claims 1-9.

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