Packaging substrate and packaging structure

Abstract

The utility model relates to a kind of packaging substrate and packaging structure, it relates to semiconductor technical field, at least one conductive layer in the packaging substrate simultaneously has first conductive structure and second conductive structure, in the layer, first conductive structure includes first busbar conductive part, second conductive structure includes second busbar conductive part, the opposite surface of first conductive structure and second conductive structure is uneven, at this time, the facing area of first busbar conductive part and second busbar conductive part in second direction is less than the total facing area of first conductive structure and second conductive structure. Compared with traditional structure, since the total facing area of first conductive structure and second conductive structure is larger, so the effective coupling area of first conductive structure and second conductive structure increases, in the case that original structure is basically unchanged, the capacitive mutual coupling between first conductive structure and second conductive structure is improved, the impedance of conductive network is reduced, and the integrity of conductive network is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging substrate and packaging structure. Background Technology

[0002] In integrated circuit packaging, power integrity (PI) is a core element to ensure the stable operation of the chip power supply system. Its core objective is to maintain the voltage fluctuation of the power distribution network (PDN) within the tolerance range and to provide a low-noise power supply environment for high-speed signal transmission.

[0003] During the packaging process, decoupling capacitors are connected to reduce the impedance of the power network. However, the area of ​​the packaging substrate is limited, making it impossible to achieve the integrity of all power networks. Utility Model Content

[0004] Therefore, it is necessary to provide a packaging substrate and packaging structure for improving the integrity of the power network of the packaging substrate.

[0005] To achieve the above objectives, on the one hand, this utility model provides a packaging substrate, comprising:

[0006] A multilayer conductive layer, wherein the conductive layer has a first conductive structure and / or a second conductive structure;

[0007] At least one conductive layer simultaneously has both the first conductive structure and the second conductive structure; in the conductive layer simultaneously having both the first conductive structure and the second conductive structure, the first conductive structure includes a first busbar conductive portion, the second conductive structure includes a second busbar conductive portion, the first busbar conductive portion and the second busbar conductive portion extend in a first direction, and the first busbar conductive portion and the second busbar conductive portion are disposed opposite to each other in a second direction, the first direction and the second direction being parallel to and intersecting the conductive layer;

[0008] The opposing surfaces of the first conductive structure and the second conductive structure are uneven; the area of ​​the first and second current-carrying conductive portions facing each other in the second direction is smaller than the total area of ​​the first and second conductive structures facing each other.

[0009] In one embodiment, in the conductive layer having both the first conductive structure and the second conductive structure, the first conductive structure further includes a plurality of first forked conductive portions, the plurality of first forked conductive portions being connected to the first busbar conductive portion, the first forked conductive portions being located on the side of the first busbar conductive portion closer to the second conductive structure, and the plurality of first forked conductive portions extending in the second direction and arranged in the first direction;

[0010] The second conductive structure further includes a plurality of second forked conductive parts, which are connected to the second bus conductive part. The second forked conductive parts are located on the side of the second bus conductive part closer to the first conductive structure. The plurality of second forked conductive parts extend in the second direction and are arranged in the first direction.

[0011] The first fork-guided electrical unit and the second fork-guided electrical unit are arranged alternately in the first direction.

[0012] In one embodiment, a clearance area and a non-clearance area are provided between the first conductive structure and the second conductive structure;

[0013] At least a portion of the avoidance zone is not equipped with the first fork guide electric section and / or the second fork guide electric section;

[0014] The first fork conductor and the second fork conductor in the non-avoidance zone are arranged opposite to each other in the first direction.

[0015] In one embodiment, the first fork guide electrical part and the second fork guide electrical part are provided in the avoidance area, and the first fork guide electrical part and the second fork guide electrical part in the avoidance area are arranged opposite to each other in the second direction, and the length of the first fork guide electrical part and the second fork guide electrical part in the avoidance area in the second direction is N;

[0016] The lengths of the first fork conductor and the second fork conductor in the non-avoidance zone in the second direction are M, where N < M.

[0017] In one embodiment, the width of the first fork conductor and the second fork conductor disposed in the avoidance area in the first direction is L;

[0018] The width of the first fork conductor and the second fork conductor in the non-avoidance zone in the first direction is S, where L > S.

[0019] In one embodiment, the first fork conductor and the second fork conductor are not provided in the avoidance area, and the first bus conductor and the second bus conductor in the avoidance area are uneven.

[0020] In one embodiment, in the first direction, the first fork conductor and the second fork conductor are opposite to each other in an uneven manner.

[0021] In one embodiment, in the conductive layer having both the first conductive structure and the second conductive structure, the first conductive structure further includes a first conductive portion, which is located on the side of the first busbar conductive portion closer to the second busbar conductive portion, and the surface of the first conductive portion facing the second busbar conductive portion is wavy, sawtooth, or fractal.

[0022] The second conductive structure further includes a second conductive portion, which is located on the side of the second busbar conductive portion close to the first busbar conductive portion. The surface of the second conductive portion facing the first busbar conductive portion has a wavy, sawtooth, or fractal shape.

[0023] In one embodiment, the packaging substrate further includes:

[0024] A capacitor is located on one side of the multilayer conductive layer; the first conductive structure and the second conductive structure are respectively connected to the capacitor through conductive vias.

[0025] On the other hand, this application also provides a packaging structure, including:

[0026] Any of the above-mentioned packaging substrates;

[0027] The chip is located on one side of the multilayer conductive layer of the packaging substrate; the chip is connected to the first conductive structure and the second conductive structure respectively through conductive vias.

[0028] Compared with existing technologies, the above technical solution has the following advantages:

[0029] The packaging substrate includes multiple conductive layers, each conductive layer having a first conductive structure and / or a second conductive structure. At least one conductive layer simultaneously has both a first conductive structure and a second conductive structure. In this layer, the first conductive structure includes a first bus conductive portion, and the second conductive structure includes a second bus conductive portion. The first and second bus conductive portions extend in a first direction and are positioned opposite each other in a second direction. The first and second directions are parallel to and intersect the conductive layers. The opposing surfaces of the first and second conductive structures are uneven. Therefore, the area of ​​the first and second bus conductive portions facing each other in the second direction is smaller than the total area of ​​the first and second conductive structures facing each other. Compared to traditional structures, because the total area of ​​the first and second conductive structures facing each other is larger, the effective coupling area of ​​the first and second conductive structures is increased. While maintaining the original structure essentially unchanged, this improves the capacitive coupling between the first and second conductive structures, reduces the impedance of the conductive network, and increases the integrity of the conductive network. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a traditional packaging substrate.

[0032] Figure 2 This application provides a schematic diagram of the structure of a packaging substrate.

[0033] Figure 3 A top view of a first conductive structure and a second conductive structure provided in an embodiment of this application;

[0034] Figure 4 A top view of the structure of a first fork guide electric section and a second fork guide electric section provided in an embodiment of this application;

[0035] Figure 5 A top view of a clearance area without a first fork guide electric unit and a second fork guide electric unit provided in an embodiment of this application;

[0036] Figure 6 A top view of another first fork guide electric section and a second fork guide electric section provided in an embodiment of this application;

[0037] Figure 7A top view of another embodiment of the first fork guide electric section and the second fork guide electric section provided in this application;

[0038] Figure 8 A top view schematic diagram of another first conductive structure and a second conductive structure provided in an embodiment of this application;

[0039] Figure 9 A top view schematic diagram of another first conductive structure and a second conductive structure provided in an embodiment of this application;

[0040] Figure 10 This is a schematic diagram of a packaging structure provided in an embodiment of this application;

[0041] Figure 11 This is a schematic diagram comparing the simulation structure of the power network of the traditional structure and the structure of this application.

[0042] Explanation of reference numerals in the attached figures: 01-Metal layer; 02-First dielectric layer; 03-Power network; 04-Ground network; 05-Decoupling capacitor; 11-Conductive layer; 12-First conductive structure; 121-First bus conductor; 122-First fork conductor; 123-First conductive part; 13-Second conductive structure; 131-Second bus conductor; 132-Second fork conductor; 133-Second conductive part; 14-Dielectric layer; 15-Capacitor; 16-Chip. Detailed Implementation

[0043] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0045] It should be understood that when a layer is referred to as "on," "adjacent to," or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other layers, there are no intervening layers.

[0046] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0047] Based on the background information, chip packaging is a technical process of encapsulating a semiconductor chip in a protective casing using specific processes. This achieves physical connection, mechanical support, heat dissipation protection, and environmental isolation between the chip and external circuits. Chip packaging connects the chip electrodes to external circuits via metal pins or solder balls, transmitting electrical signals and power. Furthermore, it isolates the chip from damage caused by external environments such as dust, moisture, and mechanical shocks. Additionally, it conducts heat generated during chip operation to the external environment. Moreover, it provides a standardized size and pin arrangement for the chip, facilitating its mounting onto circuit boards.

[0048] As chip operating frequencies reach the GHz level, the rapid changes in transient current (rise time less than 1 ns) and the increase in power density (>100W / cm²) make the impact of power supply noise on system performance increasingly significant. The essence of power supply noise is that the PDN impedance is too high at a specific frequency, causing voltage fluctuations when the current changes.

[0049] In packaging substrates, one existing technique for reducing substrate impedance and improving power integrity is to connect a decoupling capacitor in parallel between the power network and the ground network. This decoupling capacitor optimizes the impedance characteristics of the power distribution network, suppressing voltage fluctuations and noise. For example, refer to... Figure 1 , Figure 1This is a schematic diagram of a traditional packaging substrate. The packaging substrate includes multiple metal layers 01 and a first dielectric layer 02 located between the multiple metal layers 01. At least one of the metal layers 01 simultaneously houses a power network 03 and a ground network 04. Both the power network 03 and the ground network 04 are rectangular, and their adjacent surfaces are regular straight lines. In this case, due to the high impedance of the power distribution network, multiple decoupling capacitors 05 need to be connected in parallel between the power network 03 and the ground network 04. However, allocating a certain number of capacitors to a particular power network affects the number of capacitors in other networks, thus impacting the power integrity of those other networks, and the power integrity of the current power network still does not meet the requirements. Another existing technology to improve the power integrity of the substrate is to increase the number of layers in the packaging substrate, allocating the excess layers to the power network and ground network, increasing capacitive coupling, improving impedance characteristics, and improving power integrity. However, increasing the number of layers in the packaging substrate to improve power characteristics significantly increases the manufacturing cost of the packaging substrate.

[0050] Based on this, this application provides a packaging substrate and a packaging structure. The packaging substrate includes multiple conductive layers, each of which has a first conductive structure and / or a second conductive structure. At least one conductive layer simultaneously has both a first conductive structure and a second conductive structure. In this layer, the first conductive structure includes a first bus conductive portion, and the second conductive structure includes a second bus conductive portion. The first and second bus conductive portions extend in a first direction and are disposed opposite to each other in a second direction. The first and second directions are parallel to and intersect the conductive layers. The opposing surfaces of the first and second conductive structures are uneven. In this case, the area of ​​the first and second bus conductive portions facing each other in the second direction is smaller than the total area of ​​the first and second conductive structures facing each other. Compared with the conventional structure, since the total area of ​​the first and second conductive structures facing each other is larger, the effective coupling area of ​​the first and second conductive structures is increased. While maintaining the original structure basically unchanged, the capacitive coupling between the first and second conductive structures is improved, the impedance of the conductive network is reduced, and the integrity of the conductive network is increased.

[0051] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] refer to Figure 2 , Figure 2 This application provides a schematic diagram of the structure of a packaging substrate; the packaging substrate includes:

[0053] A multilayer conductive layer 11, wherein the conductive layer 11 has a first conductive structure 12 and / or a second conductive structure 13;

[0054] At least one conductive layer 11 has both a first conductive structure 12 and a second conductive structure 13. In the conductive layer 11 having both the first conductive structure 12 and the second conductive structure 13, the first conductive structure 12 includes a first current-carrying conductive portion 121, and the second conductive structure 13 includes a second current-carrying conductive portion 131. The first current-carrying conductive portion 121 and the second current-carrying conductive portion 131 extend in the first direction Y and are disposed opposite to each other in the second direction X. The first direction Y and the second direction X are parallel to the conductive layer 11 and intersect each other.

[0055] The opposing surfaces of the first conductive structure 12 and the second conductive structure 13 are uneven; the area of ​​the first busbar conductive part 121 and the second busbar conductive part 131 facing each other in the second direction X is smaller than the total area of ​​the first conductive structure 12 and the second conductive structure 13 facing each other.

[0056] Specifically, the packaging substrate may include multiple conductive layers 11. A dielectric layer 14 may be disposed between two adjacent conductive layers 11. The dielectric layer 14 can isolate the conductive layers 11 of different layers, ensuring accurate wiring in the conductive layers 11 and preventing short circuits. A first conductive structure 12 may be present in the same conductive layer 11, or a second conductive structure 13 may be present in the same conductive layer 11, or both a first conductive structure 12 and a second conductive structure 13 may be present in the same conductive layer 11. There is no specific limitation in this regard. When setting the conductive layers 11, the required conductive structures can be set in one conductive layer 11 according to different wiring requirements.

[0057] At least one conductive layer 11 has both a first conductive structure 12 and a second conductive structure 13. In the conductive layer 11, the first conductive structure 12 includes a first bus conductive portion 121, and the second conductive structure 13 includes a second bus conductive portion 131. The first bus conductive portion 121 and the second bus conductive portion 131 extend in a first direction Y. The first bus conductive portion 121 and the second bus conductive portion 131 are disposed opposite to each other in a second direction X. The second direction X and the first direction Y are parallel to and intersect the conductive layer 11. In this embodiment, the second direction X and the first direction Y can be perpendicular to each other and are not specifically limited. The second direction X and the first direction Y can also have an angle, for example, an acute angle.

[0058] It should be noted that in this embodiment, the first conductive structure 12 can be a partial conductive structure in the power network (VSS), and the second conductive structure 13 can be a partial conductive structure in the ground network (VDD). It should also be noted that the power network (VSS) or ground network (VDD) can be designed in the middle layer of the multilayer conductive layers 11 to ensure signal integrity. In this case, the facing area of ​​the first bus conductive portion 121 and the second bus conductive portion 131 in the second direction X is smaller than the total facing area of ​​the first conductive structure 12 and the second conductive structure 13. That is, the total facing area of ​​the first conductive structure 12 and the second conductive structure 13 in this application is larger than the facing area of ​​the conventional first conductive structure 12 and second conductive structure 13.

[0059] In this embodiment, compared with the traditional structure, the total facing area of ​​the first conductive structure 12 and the second conductive structure 13 is increased, which increases the effective coupling area of ​​the first conductive structure 12 and the second conductive structure 13. While keeping the original structure basically unchanged, the capacitive mutual coupling of the first conductive structure 12 and the second conductive structure 13 in the packaging substrate is improved, the impedance of the conductive network is reduced, and the integrity of the conductive network is increased.

[0060] In another embodiment of this application, reference is made to Figure 2 In the conductive layer 11 which has both a first conductive structure 12 and a second conductive structure 13, the first conductive structure 12 further includes a plurality of first forked conductive parts 122. The plurality of first forked conductive parts 122 are connected to the first busbar conductive part 121. The first forked conductive parts 122 are located on the side of the first busbar conductive part 121 close to the second conductive structure 13. The plurality of first forked conductive parts 122 extend in the second direction X and are arranged in the first direction Y.

[0061] The second conductive structure 13 also includes a plurality of second forked conductive parts 132, which are connected to the second bus conductor 131. The second forked conductive parts 132 are located on the side of the second bus conductor 131 close to the first conductive structure 12. The plurality of second forked conductive parts 132 extend in the second direction X and are arranged in the first direction Y.

[0062] The first fork electric guide unit 122 and the second fork electric guide unit 132 are arranged alternately in the first direction Y.

[0063] Specifically, the first conductive structure 12 may further include a plurality of first forked conductive sections 122 interconnected with the first busbar conductive section 121. It should be noted that the width of the first busbar conductive section 121 in the second direction X can be set relatively narrow, as long as the plurality of first forked conductive sections 122 can be connected. The plurality of first forked conductive sections 122 are arranged in the first direction Y and extend in the second direction X. The first forked conductive sections 122 are located on the side of the first busbar conductive section 121 closest to the second conductive structure 13. In this case, the first forked conductive sections 122 increase the side area of ​​the first conductive structure 12.

[0064] The second conductive structure 13 may further include a plurality of second forked conductive sections 132 interconnected with the second bus conductor 131. It should be noted that the width of the second bus conductor 131 in the second direction X can be relatively narrow, as long as the plurality of second forked conductive sections 132 can be connected. The plurality of second forked conductive sections 132 are arranged in the first direction Y and extend in the second direction X. The second forked conductive sections 132 are located on the side of the second bus conductor 131 closest to the first conductive structure 12. In this case, the second forked conductive sections 132 increase the side area of ​​the second conductive structure 13.

[0065] Since the first fork conductor 122 and the second fork conductor 132 are alternately arranged in the first direction Y, the first fork conductor 122 and the second fork conductor 132 have a facing area in the first direction Y. The traditional facing area is the facing area of ​​the first bus conductor 121 and the second bus conductor 131 in the second direction X. In this application, the total facing area of ​​the first conductive structure 12 and the second conductive structure 13 becomes the facing area of ​​the first fork conductor 122 and the second fork conductor 132. Obviously, the facing area of ​​the first bus conductor 121 and the second bus conductor 131 in the second direction X is smaller than the total facing area of ​​the first conductive structure 12 and the second conductive structure 13. In this application, the effective coupling area between the first conductive structure 12 and the second conductive structure 13 is increased. Since only the shape of the first conductive structure 12 is changed, the capacitive mutual coupling of the first conductive structure 12 and the second conductive structure 13 in the packaging substrate is improved while keeping the original structure basically unchanged, the impedance of the conductive network is reduced, and the integrity of the conductive network is increased.

[0066] It should be noted that the width of the first fork conductive part 122 in the first direction Y can be set to be narrower, and the width of the second fork conductive part 132 in the first direction Y can also be set to be narrower, thereby increasing the number of the first fork conductive part 122 and the second fork conductive part 132, and further increasing the effective coupling area between the first conductive structure 12 and the second conductive structure 13.

[0067] In this embodiment, the first conductive structure 12 and the second conductive structure 13 form an interdigitated shape, which increases the facing area of ​​the first conductive structure 12 and the second conductive structure 13, improves the capacitive mutual coupling of the first conductive structure 12 and the second conductive structure 13 in the packaging substrate, reduces the impedance of the conductive network, and increases the integrity of the conductive network in the packaging substrate.

[0068] In another embodiment of this application, reference is made to Figure 3 , Figure 3 This is a top view of a first conductive structure and a second conductive structure provided in an embodiment of this application; an avoidance area a and a non-avoidance area b are provided between the first conductive structure 12 and the second conductive structure 13;

[0069] At least a portion of the avoidance zone a is not equipped with the first fork guide electric section 122 and / or the second fork guide electric section 132;

[0070] The first fork guide electric unit 122 and the second fork guide electric unit 132 in the non-avoidance zone b are arranged opposite to each other in the first direction Y.

[0071] Specifically, a clearance area a and a non-clearance area b are provided between the first conductive structure 12 and the second conductive structure 13. Other structures, such as conductive vias, may exist between the first conductive structure 12 and the second conductive structure 13. In this case, in order to bypass the structure, the conductive layer 11 is provided with a clearance area a. At least a portion of the clearance area a is not provided with the first fork conductor 122, or at least a portion of the clearance area a is not provided with the second fork conductor 132, or at least a portion of the clearance area a is not provided with the first fork conductor 122 and the second fork conductor 132, thereby bypassing the area. No specific limitation is made in this regard.

[0072] In the non-avoidance area b, the first conductive structure 12 includes a first fork conductive part 122, and the second conductive structure 13 includes a second fork conductive part 132. The first fork conductive part 122 and the second fork conductive part 132 are arranged opposite to each other in the first direction Y to increase the facing area of ​​the first conductive structure 12 and the second conductive structure 13.

[0073] It should be noted that there are no specific restrictions on the positions of the avoidance area a and the non-avoidance area b; they can be located between the first conductive structure 12 and the second conductive structure 13.

[0074] In this embodiment, setting a clearance area a and a non-clearance area b between the first conductive structure 12 and the second conductive structure 13 can make the arrangement more adaptable to the structure, thereby reducing costs.

[0075] In another embodiment of this application, reference is made to Figure 3The first fork guide electric section 122 and the second fork guide electric section 132 are provided in the avoidance area a, and the first fork guide electric section 122 and the second fork guide electric section 132 in the avoidance area a are arranged opposite to each other in the second direction X, and the length of the first fork guide electric section 122 and the second fork guide electric section 132 in the second direction X is N.

[0076] The lengths of the first fork electric guide unit 122 and the second fork electric guide unit 132 in the non-avoidance zone b in the second direction X are M, where N < M.

[0077] Specifically, in the conductive layer 11 that simultaneously has a first conductive structure 12 and a second conductive structure 13, there may be other structures between the first conductive structure 12 and the second conductive structure 13. In this case, to bypass such structures, the length of the first fork conductive part 122 in the second direction X of the avoidance area a can be set to N, and the length of the first fork conductive part 122 in the second direction X of the non-avoidance area b can be set to M, where N < M. That is, the length of the first fork conductive part 122 in the avoidance area a is set shorter, thereby bypassing the area. Similarly, the length of the second fork conductive part 132 in the second direction X of the avoidance area a can be set to N, and the length of the second fork conductive part 132 in the second direction X of the non-avoidance area b can be set to M, where N < M. That is, the length of the second fork conductive part 132 in the avoidance area a is set shorter, thereby bypassing the area. At this time, the first fork conductive part 122 and the second fork conductive part 132 in the avoidance area a are arranged opposite each other in the second direction X.

[0078] In this embodiment, the lengths of the first fork conductor 122 and the second fork conductor 132 in the second direction X of the avoidance area a are set to be shorter, while the lengths of the first fork conductor 122 and the second fork conductor 132 in the second direction X of the non-avoidance area b are set to be longer. This can better adapt to the structural characteristics while satisfying the requirement of increasing the facing area and reducing the manufacturing cost.

[0079] In another embodiment of this application, reference is made to Figure 3 The width of the first fork guide electric unit 122 and the second fork guide electric unit 132 in the first direction Y in the avoidance zone a is L;

[0080] The width of the first fork guide electric section 122 and the second fork guide electric section 132 in the non-avoidance zone b in the first direction Y is S, where L > S.

[0081] Specifically, the first fork electric guide unit 122 and the second fork electric guide unit 132 in the avoidance zone a can be arranged opposite each other in the second direction X. At this time, at least a portion of the area between the first fork electric guide unit 122 and the second fork electric guide unit 132 can be provided with other structures.

[0082] The width L of the first fork conductor 122 and the second fork conductor 132 in the first direction Y of the avoidance zone a is greater than the width S of the first fork conductor 122 and the second fork conductor 132 in the first direction Y of the non-avoidance zone b, so that the first fork conductor 122 and the second fork conductor 132 in the avoidance zone a also have a larger facing area in the second direction X, thereby increasing the effective coupling area.

[0083] refer to Figure 4 , Figure 4 This is a top view of a first fork guide conductor and a second fork guide conductor provided in an embodiment of this application; the distance H between two adjacent first fork guide conductors 122 and second fork guide conductors 132 in the first direction Y ranges from 10μm to 20μm.

[0084] Specifically, in the first direction Y, the distance H between two adjacent first fork conductors 122 and second fork conductors 132 ranges from 10μm to 20μm, including endpoint values. For example, the distance H between two adjacent first fork conductors 122 and second fork conductors 132 may be 10μm, 14μm, 17μm, or 19μm, etc., without specific limitations. It should be noted that setting an appropriate distance between the power network (VSS) and the ground network (VDD) can ensure the integrity of the power network.

[0085] In another embodiment of this application, reference is made to Figure 5 , Figure 5 This is a top view of a clearance area without a first fork conductor and a second fork conductor provided in an embodiment of this application. The clearance area a does not have a first fork conductor 122 and a second fork conductor 132. The first bus conductor 121 and the second bus conductor 131 in the clearance area a are uneven opposite each other.

[0086] Specifically, when other structures within the avoidance zone a are large, the avoidance zone a may not be equipped with the first fork conductor 122 and the second fork conductor 132. Furthermore, an uneven surface will be provided directly opposite the first bus conductor 121 and the second bus conductor 131 in the avoidance zone a; for example, it can be wavy (e.g.,...). Figure 5 (as shown) or zigzag or fractal (not shown).

[0087] This further increases the facing area of ​​the first conductive structure 12 and the second conductive structure 13 in the avoidance area a, and increases the effective coupling area between the first conductive structure 12 and the second conductive structure 13.

[0088] In another embodiment of this application, reference is made to Figure 6 , Figure 6 This is a top view schematic diagram of another first fork guide electric section and a second fork guide electric section provided in an embodiment of this application; see reference. Figure 7 , Figure 7 This is a top view of another embodiment of the first fork guide conductor and the second fork guide conductor provided in this application; in the first direction Y, the first fork guide conductor 122 and the second fork guide conductor 132 are uneven opposite each other.

[0089] Specifically, to further increase the effective coupling area between the first conductive structure 12 and the second conductive structure 13, the first fork conductive part 122 and the second fork conductive part 132 are provided with uneven surfaces facing each other in the first direction Y. For example, the shape of the side of the first fork conductive part 122 facing the second fork conductive part 132 can be wavy (e.g., Figure 7 (as shown) or serrated (as shown) Figure 6 (as shown) or fractal (not shown), and the shape of the side of the second fork conductor 132 facing the first fork conductor 122 can also be wavy (as shown). Figure 7 (as shown) or serrated (as shown) Figure 6 (as shown) or fractal (not shown). It should be noted that the shape of the side of the first fork guiding the electric part 122 and the shape of the side of the second fork guiding the electric part 132 may be the same or different, and there is no specific limitation.

[0090] The sides of the first fork conductor 122 and the second fork conductor 132 are set in a wavy shape (e.g., Figure 7 (as shown) or serrated (as shown) Figure 6 As shown in the figure, or a fractal (not shown), the total facing area of ​​the first conductive structure 12 and the second conductive structure 13 can be further increased, thereby further increasing the effective coupling area of ​​the first conductive structure 12 and the second conductive structure 13. While keeping the original structure basically unchanged, the capacitive mutual coupling of the first conductive structure 12 and the second conductive structure 13 of the packaging substrate is improved, the impedance of the conductive network is reduced, and the integrity of the conductive network is increased.

[0091] In another embodiment of this application, reference is made to Figure 8 , Figure 8 This is a top view schematic diagram of another first conductive structure and a second conductive structure provided in an embodiment of this application; see reference. Figure 9 , Figure 9This is a top view of another first conductive structure and a second conductive structure provided in an embodiment of this application. In the conductive layer 11 which has both a first conductive structure 12 and a second conductive structure 13, the first conductive structure 12 further includes a first conductive portion 123. The first conductive portion 123 is located on the side of the first busbar conductive portion 121 that is close to the second busbar conductive portion 131. The surface of the first conductive portion 123 facing the second busbar conductive portion 131 has a wavy, sawtooth, or fractal shape.

[0092] The second conductive structure 13 also includes a second conductive part 133, which is located on the side of the second bus conductor 131 that is close to the first bus conductor 121. The surface of the second conductive part 133 facing the first bus conductor 121 is wavy, sawtooth, or fractal.

[0093] Specifically, the first conductive part 123 and the second conductive part 133 are arranged opposite to each other.

[0094] The surface of the first conductive part 123 facing the second bus conductive part 131 can be configured to be wavy (e.g., ...). Figure 9 (as shown) or serrated (as shown) Figure 8 (as shown) or fractal (not shown); the surface of the second conductive part 133 facing the first bus conductive part 121 can be configured as wavy (e.g., Figure 9 (as shown) or serrated (as shown) Figure 8 (as shown) or fractal (not shown). It should be noted that the relative surface shapes of the first conductive part 123 and the second conductive part 133 may be different, and no specific limitation is made in this regard.

[0095] At this time, by setting the opposing surfaces of the first conductive part 123 and the second conductive part 133 to be uneven, the facing area of ​​the first conductive structure 12 and the second conductive structure 13 can be increased, further increasing the effective coupling area of ​​the first conductive structure 12 and the second conductive structure 13. While keeping the original structure basically unchanged, the capacitive mutual coupling of the first conductive structure 12 and the second conductive structure 13 of the packaging substrate is improved, the impedance of the conductive network is reduced, and the integrity of the conductive network is increased.

[0096] It should be noted that the opposing surfaces of the first conductive part 123 and the second conductive part 133 can have the same shape. In this embodiment, the opposing surfaces of the first conductive part 123 and the second conductive part 133 have the same shape, which allows the shapes of the opposing surfaces to be complementary, thereby maximizing the facing area of ​​the first conductive structure 12 and the second conductive structure 13, and thus maximizing the effective coupling area.

[0097] In another embodiment of this application, reference is made to Figure 2 The packaging substrate also includes:

[0098] Capacitor 15 is located on one side of the multilayer conductive layer 11; the first conductive structure 12 and the second conductive structure 13 are respectively connected to capacitor 15 through conductive vias.

[0099] Specifically, the packaging substrate also includes a capacitor 15, which connects the first conductive structure 12 and the second conductive structure 13 through a conductive via. The conductive via can be a metal via. The first conductive structure 12 can be a power network, and the second conductive structure 13 can be a ground network. The capacitor 15 is connected in parallel between the power network and the ground network, which reduces the impedance of the power distribution network.

[0100] It should be noted that multiple capacitors 15 can be provided on the packaging substrate, and there is no specific limitation on the number of capacitors 15; the number can be set as needed. It should also be noted that multiple first conductive structures 12 and second conductive structures 13 can also be provided on the packaging substrate, and there is no specific limitation on the number of such structures.

[0101] In this embodiment, the capacitor 15 is connected in parallel between the first conductive structure 12 and the second conductive structure 13, which can further reduce the impedance of the power distribution network and effectively suppress high-frequency power noise.

[0102] In another embodiment of this application, reference is made to Figure 10 , Figure 10 This application provides a schematic diagram of a packaging structure according to an embodiment of the present application; the present application also provides a packaging structure, including:

[0103] Any of the above-mentioned packaging substrates;

[0104] Chip 16 is located on one side of multiple conductive layers 11 on the packaging substrate; chip 16 is connected to the first conductive structure 12 and the second conductive structure 13 respectively through conductive vias.

[0105] Specifically, the packaging substrate is the packaging substrate provided in any of the above embodiments. It should be noted that the design of the above packaging substrate can increase the effective coupling area, improve the capacitive mutual coupling of the packaging substrate, reduce impedance, and increase the integrity of the conductive network while keeping the original structure basically unchanged. In addition, the wavy and fractal surface settings can enhance the electromagnetic field coupling effect in the high-frequency band and improve its impedance characteristics.

[0106] A chip 16 is disposed on the multilayer conductive layer 11 of the packaging substrate. The chip 16 is connected to the first conductive structure 12 and the second conductive structure 13 through conductive vias. The chip 16 is the core functional carrier of the packaging substrate. Its function is not limited to its own circuit function, but also works with the packaging substrate to achieve packaging integration.

[0107] In this embodiment, since the packaging substrate of this application is used, the packaging structure also has the same effect as the packaging substrate, and their effects can be referred to each other.

[0108] Based on the above description, this application also provides a simulation comparison of the power network structures of the traditional structure and the structure of this application, for reference. Figure 11 , Figure 11 A schematic diagram comparing the simulation structure of the power network of the traditional structure and the structure of this application; Figure 11 As can be seen from the diagram, the impedance at the 1GHz frequency point using the structure of this application is lower than that of existing structures.

[0109] This application allows for flexible adjustment of shape parameters through electromagnetic field simulation, adapting to different packaging materials and process node requirements, and supporting application expansion from FC-BGA to interposer, thus offering greater adaptability.

[0110] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A packaging substrate, characterized in that, include: A multilayer conductive layer, wherein the conductive layer has a first conductive structure and / or a second conductive structure; At least one conductive layer simultaneously has both the first conductive structure and the second conductive structure; in the conductive layer simultaneously having both the first conductive structure and the second conductive structure, the first conductive structure includes a first busbar conductive portion, the second conductive structure includes a second busbar conductive portion, the first busbar conductive portion and the second busbar conductive portion extend in a first direction, and the first busbar conductive portion and the second busbar conductive portion are disposed opposite to each other in a second direction, the first direction and the second direction being parallel to and intersecting the conductive layer; The opposing surfaces of the first conductive structure and the second conductive structure are uneven; the area of ​​the first and second current-carrying conductive portions facing each other in the second direction is smaller than the total area of ​​the first and second conductive structures facing each other.

2. The packaging substrate according to claim 1, characterized in that, In the conductive layer having both the first conductive structure and the second conductive structure, the first conductive structure further includes a plurality of first forked conductive portions, the plurality of first forked conductive portions being connected to the first bus conductive portion, the first forked conductive portions being located on the side of the first bus conductive portion close to the second conductive structure, and the plurality of first forked conductive portions extending in the second direction and arranged in the first direction. The second conductive structure further includes a plurality of second forked conductive parts, which are connected to the second bus conductive part. The second forked conductive parts are located on the side of the second bus conductive part closer to the first conductive structure. The plurality of second forked conductive parts extend in the second direction and are arranged in the first direction. The first fork-guided electrical unit and the second fork-guided electrical unit are arranged alternately in the first direction.

3. The packaging substrate according to claim 2, characterized in that, A clearance area and a non-clearance area are provided between the first conductive structure and the second conductive structure; At least a portion of the avoidance zone is not equipped with the first fork guide electric section and / or the second fork guide electric section; The first fork conductor and the second fork conductor in the non-avoidance zone are arranged opposite to each other in the first direction.

4. The packaging substrate according to claim 3, characterized in that, The first fork guide electric part and the second fork guide electric part are provided in the avoidance area, and the first fork guide electric part and the second fork guide electric part in the avoidance area are arranged opposite to each other in the second direction. The length of the first fork guide electric part and the second fork guide electric part in the avoidance area in the second direction is N. The lengths of the first fork conductor and the second fork conductor in the non-avoidance zone in the second direction are M, where N < M.

5. The packaging substrate according to claim 3, characterized in that, The width of the first fork conductor and the second fork conductor in the avoidance zone in the first direction is L; The width of the first fork conductor and the second fork conductor in the non-avoidance zone in the first direction is S, where L > S.

6. The packaging substrate according to claim 3, characterized in that, The avoidance zone does not have the first fork conductor and the second fork conductor, and the first bus conductor and the second bus conductor in the avoidance zone are uneven.

7. The packaging substrate according to any one of claims 2-5, characterized in that, In the first direction, the first fork conductor and the second fork conductor are opposite each other in an uneven manner.

8. The packaging substrate according to claim 1, characterized in that, In the conductive layer that simultaneously has the first conductive structure and the second conductive structure, the first conductive structure further includes a first conductive portion, which is located on the side of the first busbar conductive portion close to the second busbar conductive portion, and the shape of the surface of the first conductive portion facing the second busbar conductive portion is wavy, sawtooth, or fractal. The second conductive structure further includes a second conductive portion, which is located on the side of the second busbar conductive portion close to the first busbar conductive portion. The surface of the second conductive portion facing the first busbar conductive portion has a wavy, sawtooth, or fractal shape.

9. The packaging substrate according to claim 1, characterized in that, The packaging substrate further includes: A capacitor is located on one side of the multilayer conductive layer; the first conductive structure and the second conductive structure are respectively connected to the capacitor through conductive vias.

10. A packaging structure, characterized in that, include: The packaging substrate as described in any one of claims 1-9; A chip, wherein the chip is located on one side of the multilayer conductive layer of the packaging substrate; The chip is connected to the first conductive structure and the second conductive structure respectively through conductive vias.

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