Packaging structure

Abstract

The utility model provides a kind of packaging structure, the packaging structure includes rewire layer;Bottom bump lower metal, it is different that the roughness of upper surface and lower surface of bottom bump lower metal is set on rewire layer and different, the roughness of side surface and lower surface of bottom bump lower metal, wherein, bottom bump lower metal is the raised structure formed after copper foil is shaped processing;Through hole, it is gradually wide from the direction of bottom bump lower metal that through hole is set in rewire layer and approaches to away;Seed layer, it is set between rewire layer and bottom bump lower metal and the upper surface of seed layer presents non-smooth structure.Copper foil is set on rewire layer, so that bottom bump lower metal is the raised structure formed after copper foil is shaped processing, to replace traditional electroplating process.Due to not needing to carry out electroplating operation, fundamentally avoid the defect caused by bubble production in electroplating process, effectively improve the electrical performance and reliability of device.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and specifically to a packaging structure. Background Technology

[0002] In the semiconductor manufacturing field, the bottom under-bump metallization (BUMB) layer in current fan-out multi-chip module (FOMCM) processes is typically fabricated using electroplating. However, the high cost of electroplating equipment and the expensive electroplating solutions significantly increase the overall expense of the packaging process. Furthermore, the need for electroplating solution analysis instruments for concentration monitoring further increases overall production costs. Additionally, electroplating technology can introduce air bubbles, which directly affect the electrical performance of the final product. Utility Model Content

[0003] This utility model proposes a packaging structure.

[0004] Firstly, this utility model proposes a packaging structure, including:

[0005] Rewire layer;

[0006] The bottom bump under metal is disposed on the redistribution layer, and the roughness of the upper surface and the lower surface of the bottom bump under metal are different. The roughness of the side surface of the bottom bump under metal is different from that of the lower surface. The bottom bump under metal is a raised structure formed by forming copper foil.

[0007] A through-hole is provided within the redistribution layer, and the through-hole gradually widens from the direction of approaching the metal under the bottom bump to moving away from the metal.

[0008] A seed layer is disposed between the redistribution layer and the metal under the bottom bump, and the upper surface of the seed layer has a non-smooth structure.

[0009] In some alternative implementations, the roughness of the upper surface of the metal under the bottom bump is greater than the roughness of the lower surface.

[0010] In some alternative implementations, the roughness of the side surface of the metal under the bottom bump is greater than the roughness of the bottom surface.

[0011] In some alternative implementations, the metal under the bottom bump is aligned with the through-hole.

[0012] In some alternative implementations, the width of the metal under the bottom bump is greater than the width of the through hole.

[0013] In some optional embodiments, the packaging structure further includes:

[0014] The first chip and the second chip are disposed below the redistribution layer and electrically connected to the metal under the bottom bump through the redistribution layer.

[0015] In some optional embodiments, the packaging structure further includes:

[0016] A molding layer is disposed below the redistribution layer and covers the first chip and the second chip.

[0017] In some alternative implementations, the width of the metal under the bottom bump is greater than or equal to 233 μm.

[0018] In some alternative implementations, the metal opening under the copper bottom bump is greater than or equal to 50 μm.

[0019] In some optional embodiments, the packaging structure further includes:

[0020] The top bump is under the metal, which is located below the redistribution layer and electrically connected to the redistribution layer.

[0021] To address the issue of air bubbles forming during the electroplating process for the under-bump metal layer in current fan-out multi-chip module manufacturing, which negatively impacts product electrical performance, this invention proposes a packaging structure. By directly placing copper foil on the redistribution layer, the under-bump metal layer is formed from the shaped copper foil, replacing the traditional electroplating process. Since electroplating is eliminated, the defects caused by air bubbles during electroplating are fundamentally avoided, effectively improving the electrical performance and reliability of the device. Furthermore, this method eliminates the need for expensive electroplating equipment and related facilities, significantly reducing overall production costs. Attached Figure Description

[0022] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0023] Figure 1 This is a schematic diagram of an existing BUBM (Bottom Under Bump Metallurgy) manufactured using electroplating technology.

[0024] Figure 2 This is a schematic diagram of the packaging structure 2a according to an embodiment of the present invention;

[0025] Figure 3 yes Figure 2 Enlarged view of the metal under the bottom bump;

[0026] Figure 4 yes Figure 2 Enlarged view of the seed layer;

[0027] Figures 5-29 This is a schematic diagram of the manufacturing steps of the packaging structure 2a according to an embodiment of the present invention.

[0028] Explanation of reference numerals / symbols in the attached diagram:

[0029] 101-Under-bottom-bump metal; 102-Bubble; 201-Reconnection layer; 202-Under-bottom-bump metal; 203-Through-hole; 204-Seed layer; 205-Solder ball; 206-First chip; 207-Second chip; 208-Molding layer; 209-Carrier board; 210-Cover layer; 211-Under-top-bump metal; 212-Copper foil; 213-Photoresist; 2011-Dielectric layer; 2012-Metal layer; 2021-Top surface; 2022-Bottom surface; 2023-Side surface; 2041-Top surface. Detailed Implementation

[0030] The specific embodiments of this utility model will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this utility model and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0031] It should be readily understood that the meanings of "on," "above," and "on top of" in this utility model should be interpreted in the broadest sense, such that "on" not only means "directly on something," but also means "on something" including intermediate components or layers existing between the two.

[0032] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0033] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0034] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0035] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the implementation conditions of this utility model and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this utility model, should still fall within the scope of the technical content disclosed in this utility model. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this utility model.

[0036] It should also be noted that the longitudinal section corresponding to the embodiment of this utility model can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0037] Furthermore, where there is no conflict, the embodiments and features described in these embodiments can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] refer to Figure 1, Figure 1 This is a schematic diagram of the structure of an existing BUBM manufactured using electroplating technology.

[0039] like Figure 1 As shown, multiple air bubbles 102 are easily generated in the metal 101 under the bottom bump formed by electroplating. These air bubbles may adversely affect the electrical performance of the product. Furthermore, the electroplating equipment is expensive, and the electroplating solution materials required are costly, significantly increasing the overall expenditure of the packaging process. In addition, electroplating solution analysis instruments are required for concentration detection, which further increases the overall production cost.

[0040] refer to Figure 2 , Figure 3 and Figure 4 , Figure 2 This is a schematic diagram of the packaging structure 2a according to an embodiment of the present invention; Figure 3 yes Figure 2 Enlarged view of the metal under the bottom bump; Figure 4 yes Figure 2 A magnified view of the seed layer.

[0041] The packaging structure 2a of this utility model may include a redistribution layer 201, a bottom bump under-metal 202, a through-hole 203, and a seed layer 204.

[0042] The bottom bump under metal 202 is disposed on the redistribution layer 201, and the roughness of the upper surface 2021 and the lower surface 2022 of the bottom bump under metal 202 is different. The roughness of the side surface 2023 of the bottom bump under metal 202 is also different from that of the lower surface 2022. The bottom bump under metal 202 is a raised structure formed by forming copper foil. The through hole 203 is disposed in the redistribution layer 201 and gradually widens from the direction of approaching the bottom bump under metal 202. The seed layer 204 is disposed between the redistribution layer 201 and the bottom bump under metal 202, and the upper surface 2041 of the seed layer 204 has a non-smooth structure.

[0043] Here, copper foil can be directly placed on the redistribution layer 201, and then processed to obtain the under-bump metal 202, replacing the traditional electroplating process. Since electroplating is unnecessary, defects caused by bubbles during electroplating are fundamentally avoided, effectively improving the electrical performance and reliability of the device. At the same time, this method eliminates the need for expensive electroplating equipment and its supporting facilities, significantly reducing overall production costs.

[0044] Here, since the bottom bump under metal 202 is a raised structure formed by the molding process of copper foil, the upper surface of the copper foil will be etched during the processing of the copper foil, resulting in the upper surface 2021 and the lower surface 2022 of the bottom bump under metal 202 having different roughness.

[0045] This difference in surface roughness helps to enhance the bonding force between the upper surface 2021 of the metal under the bottom bump 202 and the solder ball 205, thereby improving the reliability and stability of the interface connection.

[0046] Here, when removing excess copper foil to form the under-bump metal 202, for example, when removing excess copper layer by etching process, its side surface 2023 will be subjected to a certain degree of lateral etching, which will eventually make the roughness of the side surface 2023 and the bottom surface 2022 of the under-bump metal 20 different.

[0047] Here, the via 203 is disposed within the redistribution layer 201, and the via 203 gradually widens from the direction of approaching to the bottom bump under metal 202. This makes the via 203 narrower near the bottom bump under metal 202, which helps to improve the alignment accuracy between this area and the bottom bump under metal 202. On the other hand, it gradually widens in the direction of moving away from the bottom bump under metal 202 and toward the redistribution layer 201, thereby increasing the contact area between the via 203 and the redistribution layer 201, which is beneficial to improving the current carrying capacity and structural stability.

[0048] The seed layer 204 is disposed between the redistribution layer 201 and the bottom bump under metal 202, and the upper surface 2041 of the seed layer 204 has a non-smooth structure. In this way, the interfacial bonding force between the seed layer 204 and the bottom bump under metal 202 can be enhanced, thereby improving the stability and reliability of the overall structure.

[0049] In some alternative implementations, refer to Figure 3 The roughness of the upper surface 2021 of the metal 202 under the bottom bump is greater than the roughness of the lower surface 2022.

[0050] Here, during the process of processing the copper foil to form the bottom bump under metal 202, the upper surface of the copper foil is etched, that is, the upper surface 2021 of the bottom bump under metal 202 is etched. The roughness of the upper surface 2021 of the bottom bump under metal 202 after processing is greater than the roughness of the lower surface 2022.

[0051] In some alternative implementations, refer to Figure 3 The roughness of the side surface 2023 of the metal 202 under the bottom bump is greater than the roughness of the bottom surface 2022.

[0052] Here, when removing excess copper foil to form the under-bump metal 202, for example, when removing excess copper layer by etching process, its side surface 2023 will be subjected to a certain degree of lateral etching, which will make the roughness of the side surface 2023 of the under-bump metal 202 greater than the roughness of the bottom surface 2022.

[0053] In some alternative implementations, the metal under the bottom bump 202 is aligned with the through hole 203.

[0054] Thus, the alignment of the bottom bump under metal 202 with the through hole 203 ensures that current is efficiently conducted from the redistribution layer 201 to the bottom bump under metal 202 through the through hole 203, reducing resistance and signal loss. In addition, the alignment helps to improve the mechanical bonding strength between the bottom bump under metal 202 and the through hole 203, preventing structural weaknesses or failures caused by misalignment during manufacturing or actual use.

[0055] In some alternative implementations, the width of the metal under the bottom bump 202 is greater than the width of the through hole 203.

[0056] Thus, the under-bump metal 202 is wider than the via 203, which can provide a larger alignment tolerance for photolithography or deposition processes, avoid poor contact between the via 203 and the under-bump metal 202 due to slight misalignment, and the wider under-bump metal 202 provides a larger contact area, which is beneficial for current conduction from the via 203 to the under-bump metal 202.

[0057] In some alternative implementations, the width of the metal under the bottom bump 202 is greater than or equal to 233 μm.

[0058] In some alternative implementations, the opening in the metal 202 under the bottom bump is greater than or equal to 50 μm.

[0059] In some alternative implementations, the package structure also includes solder balls 205 disposed on the underside metal 202 of the bottom bump.

[0060] In this way, an efficient electrical connection between the package structure 2a and the external circuit is achieved.

[0061] In some alternative embodiments, the package structure 2a further includes a first chip 206 and a second chip 207, disposed below the redistribution layer 201 and electrically connected to the under-bump metal 202 through the redistribution layer 201.

[0062] In this way, the first chip 206 and the second chip 207 can transmit signals and supply power through the same rewiring layer, which improves the packaging integration and wiring flexibility.

[0063] In some alternative embodiments, the packaging structure 2a further includes a molding layer 208 disposed below the redistribution layer 201 and covering the first chip 206 and the second chip 207.

[0064] Thus, the encapsulation layer 208 not only provides effective physical protection for the first chip 206 and the second chip 207, preventing them from being damaged by the external environment or mechanical stress, but also helps to improve the mechanical strength and overall stability of the entire packaging structure.

[0065] In some alternative implementations, the thickness of the metal under the bottom bump 202 is greater than the thickness of the seed layer 204.

[0066] In this way, the metal under the bottom bump 202 can provide stronger mechanical support and connection strength, which helps to improve the reliability of the overall packaging structure.

[0067] In some alternative implementations, the package structure 2a also includes a top bump under-metal 211 disposed below the redistribution layer 201.

[0068] In some alternative implementations, the first chip 206 and the second chip 207 are electrically connected to the redistribution layer 201 via the under-bump metal 211.

[0069] Thus, the metal 211 under the top bump is located between the redistribution layer 201 and the first chip 206 and the second chip 207, playing a key role in achieving a good electrical connection between the chip and the redistribution layer.

[0070] The above describes the packaging structure 2a of one embodiment of the present invention.

[0071] Figures 5-29 This is a schematic diagram of the manufacturing steps of the packaging structure 2a according to an embodiment of the present invention.

[0072] refer to Figure 5 , providing carrier board 209.

[0073] refer to Figure 6 A cover layer 210 is provided on the carrier plate 209.

[0074] refer to Figure 7 A dielectric layer 2011 is formed on the cover layer 210 and the desired pattern of the via 203 is formed.

[0075] For example, a dielectric layer 2011 can be formed on the capping layer 210 using physical vapor deposition (PVD) technology.

[0076] refer to Figure 8 Metal is deposited on the surface of dielectric layer 2011 and at the predetermined pattern of via 203 to form the desired via 203.

[0077] refer to Figure 9 On the surface of via 203 and dielectric layer 2011, a new dielectric layer 2011 is deposited, forming the pattern required for the internal circuitry of redistribution layer 201.

[0078] refer to Figure 10 Metal is deposited on the surface of the new dielectric layer 2011 and at the predetermined pattern of the internal circuitry to form the internal circuitry (metal layer 2012) of the redistribution layer 201.

[0079] refer to Figure 11 ,exist Figure 10 On top of that, a new dielectric layer 2011 is deposited, and the pattern required for the internal circuitry of the redistribution layer 201 is formed.

[0080] refer to Figure 12 ,exist Figure 11 Metal is deposited on the surface of the dielectric layer 2011 and at the predetermined pattern of the internal circuitry to form the internal circuitry of the redistribution layer 201 (new metal layer 2012).

[0081] refer to Figure 13 ,exist Figure 12 On top of this, a new dielectric layer 2011 is deposited, and the desired pattern of the metal 211 under the top bump is formed.

[0082] refer to Figure 14 ,exist Figure 12 Metal is deposited on the surface of the dielectric layer 2011 and at a predetermined pattern of the top bump under metal 211 to form the top bump under metal 211.

[0083] Thus, a redistribution layer 201 and a top bump under-metal 211 are obtained through multiple dielectric layers and multiple metal layers 2012.

[0084] refer to Figure 15 A first chip 206 and a second chip 207 are disposed above the metal 211 under the top protrusion.

[0085] refer to Figure 16 A mold sealing layer 208 is set to cover the first chip 206 and the second chip 207.

[0086] refer to Figure 17 ,right Figure 16 The resulting structure is flipped.

[0087] refer to Figure 18 Seed layer 204 is provided on redistribution layer 201 and via 203.

[0088] refer to Figure 19A copper foil 212 is provided, and the bottom of the copper foil 212 is scanned with infrared light to make the bottom of the copper foil 212 molten.

[0089] refer to Figure 20 The copper foil 212 is pressed together with the seed layer 204 by hot pressing, and the copper foil 212 is then cured.

[0090] Here, the upper surface 2041 of the seed layer 204 can be bombarded with plasma to increase the roughness of the upper surface 2041, thereby enhancing the bonding force between the seed layer 204 and the copper foil 212 and achieving a stronger connection.

[0091] refer to Figure 21 The upper surface of copper foil 212 is subjected to soft copper etching or surface cleaning treatment.

[0092] This treatment effectively removes the oxide layer, organic contaminants, and other impurities from the surface of copper foil 212, thereby improving its surface activity and cleanliness. Simultaneously, this process slightly roughens the surface of copper foil 212, which enhances the adhesion and electrical connection performance between subsequent materials (such as photoresist) and the copper foil, thus improving the overall structural stability and reliability.

[0093] refer to Figure 22 Photoresist 213 is coated on the surface of copper foil 212.

[0094] refer to Figure 23 The photoresist 213 is exposed.

[0095] refer to Figure 24 The photoresist 213 is developed to remove unexposed portions, thereby forming a predetermined pattern on the surface of the copper foil 212 that corresponds to the metal under the bottom bump 202.

[0096] refer to Figure 25 The etching process removes excess copper foil 212 and seed layer 204 to obtain the under-bump metal 202 and the seed layer 204 located below the under-bump metal 202.

[0097] refer to Figure 26 The photoresist on the metal 202 under the bottom bump is peeled off.

[0098] refer to Figure 27 Solder balls 205 are provided on the metal 202 under the bottom bump.

[0099] refer to Figure 28 ,right Figure 27 The resulting structure is flipped over, and the molding layer 208 is ground so that the upper surface of the molding layer 208 is flush with the surface of the first chip 206.

[0100] refer to Figure 29 ,right Figure 27 The resulting structure is flipped and cut to form a single encapsulation structure 2a.

[0101] Although the present invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of the invention. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation of the invention and actual implementation due to variables in the manufacturing process, etc. Other embodiments of the invention may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the invention.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: Rewire layer; The bottom bump under metal is disposed on the redistribution layer, and the roughness of the upper surface and the lower surface of the bottom bump under metal are different. The roughness of the side surface of the bottom bump under metal is different from that of the lower surface. The bottom bump under metal is a raised structure formed by forming copper foil. A through-hole is provided within the redistribution layer, and the through-hole gradually widens from the direction of approaching the metal under the bottom bump to moving away from the metal. A seed layer is disposed between the redistribution layer and the metal under the bottom bump, and the upper surface of the seed layer has a non-smooth structure.

2. The packaging structure according to claim 1, characterized in that, The roughness of the upper surface of the metal under the bottom bump is greater than the roughness of the lower surface.

3. The packaging structure according to claim 1, characterized in that, The roughness of the side surface of the metal under the bottom bump is greater than the roughness of the bottom surface.

4. The packaging structure according to claim 1, characterized in that, The metal under the bottom bump is aligned with the through hole.

5. The packaging structure according to claim 1, characterized in that, The width of the metal under the bottom bump is greater than the width of the through hole.

6. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: The first chip and the second chip are disposed below the redistribution layer and electrically connected to the metal under the bottom bump through the redistribution layer.

7. The packaging structure according to claim 6, characterized in that, The packaging structure further includes: A molding layer is disposed below the redistribution layer and covers the first chip and the second chip.

8. The packaging structure according to claim 1, characterized in that, The width of the metal under the bottom bump is greater than or equal to 233 μm.

9. The packaging structure according to claim 1, characterized in that, The metal opening under the bottom bump is greater than or equal to 50 μm.

10. The packaging structure according to claim 6, characterized in that, The packaging structure further includes: The top bump is under the metal, which is located below the redistribution layer and electrically connected to the redistribution layer.

Images