Electronic package
Patent Information
- Application Number
- CN202521842203.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2025-08-05
- Filing Date
- 2025-08-28
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2035-08-28
AI Technical Summary
[0004]但，现有半导体封装件1中，该半导体晶片11与该功能晶片12进行信号传输时会有杂讯产生，导致传输信号模糊、失真等问题发生
[0019]由上可知，本申请的电子封装件主要通过该功能组件的配置，可消除杂讯，以避免传输信号模糊、失真等问题发生，因而能有效提升该电子封装件的信号传输良率。同时，由于该功能组件结合于中介板且邻近该电子元件，故可有效提升信号传输效能。
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Figure CN224805461U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor packaging technology, and more particularly to an electronic package that improves signal transmission yield. Background Technology
[0002] To ensure the continued miniaturization and versatility of electronic products and communication equipment, semiconductor packaging needs to evolve towards smaller dimensions to facilitate multi-pin connections, high-speed operation, and high functionality. For example, in advanced process packaging, commonly used packaging types include fan-out wiring combined with embedded component processes.
[0003] Figure 1 This is a cross-sectional schematic diagram of an existing semiconductor package 1. Figure 1 As shown, a conventional semiconductor package 1 includes: a cover layer 15, a functional chip 12 embedded in the cover layer 15, a plurality of conductive pillars 13 embedded in the cover layer 15, a circuit structure 10 disposed on the upper surface of the cover layer 15, a plurality of semiconductor chips 11 disposed on the circuit structure 10, a package layer 18 covering the semiconductor chips 11, a wiring structure 14 disposed on the lower surface of the cover layer 15, and a plurality of solder balls 17 disposed on the wiring structure 14, wherein any two semiconductor chips 11 are communicatively connected to the functional chip 12 through the circuit structure 10, and the circuit structure 10 is electrically connected to the wiring structure 14 through the conductive pillars 13.
[0004] However, in the existing semiconductor package 1, noise is generated when the semiconductor chip 11 and the functional chip 12 transmit signals, which leads to problems such as blurred and distorted transmitted signals.
[0005] Therefore, overcoming the problems of the existing technologies has become a pressing issue for the industry. Utility Model Content
[0006] In view of the various deficiencies of the prior art, this application provides an electronic package, including: an interposer having a circuit layer; an electronic component disposed on the interposer and electrically connected to the circuit layer; and a functional component combined with the interposer and including a capacitor structure and an inductor circuit, wherein the capacitor structure is electrically connected to the inductor circuit, and the inductor circuit is electrically connected to the circuit layer.
[0007] The aforementioned electronic package also includes a substrate for supporting the interposer.
[0008] In the aforementioned electronic package, the interposer includes a cover layer, a circuit structure formed on the cover layer and including the circuit layer, and bridging elements and multiple conductive posts disposed in the cover layer.
[0009] In the aforementioned electronic package, a plurality of electronic components are disposed on the interposer, so that the bridging element electrically bridges the plurality of electronic components via the circuit layer.
[0010] In the aforementioned electronic package, the capacitor structure is embedded in the encapsulation layer.
[0011] In the aforementioned electronic package, the inductor circuit is formed in the circuit structure and is fabricated simultaneously with the circuit layer.
[0012] In the aforementioned electronic package, the inductor circuit is in the form of a planar spiral or a three-dimensional spiral.
[0013] In the aforementioned electronic package, the functional component is a balanced-to-unbalanced converter, which includes at least two capacitor structures and at least two inductor lines.
[0014] In the aforementioned electronic package, the capacitor structure is in the form of a modular element.
[0015] In the aforementioned electronic package, the interposer has opposing first and second sides and includes a dielectric layer and a circuit layer bonded to the dielectric layer.
[0016] In the aforementioned electronic package, the electronic component is disposed on the first side of the interposer and electrically connected to the circuit layer.
[0017] In the aforementioned electronic package, the capacitor structure is disposed on the second side of the interposer plate.
[0018] In the aforementioned electronic package, the inductor circuit is formed in the dielectric layer of the interposer and is fabricated simultaneously with the circuit layer.
[0019] As can be seen from the above, the electronic package of this application can eliminate noise through the configuration of this functional component, thereby avoiding problems such as signal blurring and distortion, and thus effectively improving the signal transmission yield of the electronic package. At the same time, since this functional component is integrated into the interposer and is adjacent to the electronic component, it can effectively improve the signal transmission performance.
[0020] Furthermore, the electronic package can be manufactured using existing semiconductor packaging process materials and equipment, thus eliminating the need to develop new processes or purchase new equipment, thereby avoiding significant additional costs. Therefore, the electronic package of this application not only reduces the production cost of the final product but also greatly improves feasibility. Attached Figure Description
[0021] Figure 1 This is a cross-sectional schematic diagram of an existing semiconductor package.
[0022] Figure 2 This is a cross-sectional schematic diagram of the first embodiment of the electronic package of this application.
[0023] Figure 3 This is a partial top view of the inductor circuit of the electronic package of this application.
[0024] Figure 4 This is a circuit diagram of the functional components of the electronic package of this application.
[0025] Figure 5 This is a cross-sectional schematic diagram of a second embodiment of the electronic package of this application.
[0026] Explanation of reference numerals in the attached figures
[0027] 1 Semiconductor package
[0028] 10. Circuit Structure
[0029] 11 Semiconductor wafers
[0030] 12-functional chip
[0031] 13 Conductive pillars
[0032] 14 Wiring Structure
[0033] 15 Coating Layers
[0034] 17 Solder balls
[0035] 18 Encapsulation Layer
[0036] 2,3 Electronic packages
[0037] Intermediate Board 21, 31
[0038] 211 Coating Layer
[0039] 212 Line Structure
[0040] 2120, 310 dielectric layers
[0041] 2121,311 Line Layer
[0042] 213 Bridging element
[0043] 214 Conductive Post
[0044] 215,312 Conductive components
[0045] 22,32 Electronic components
[0046] 220 conductive bump
[0047] 221 base rubber
[0048] 23,33 Functional Components
[0049] 231,331 Capacitor Structure
[0050] 232,332 Inductor Circuits
[0051] 24,34 base plate
[0052] 240 Conductive Components
[0053] 31a First side
[0054] 31b Second side
[0055] S1 Single-ended signal
[0056] S2 differential signal. Detailed Implementation
[0057] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0058] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0059] Figure 2 This is a cross-sectional schematic diagram of the first embodiment of the electronic package 2 of this application.
[0060] like Figure 2 As shown, the electronic package 2 includes: an interposer 21, at least one electronic component 22, at least one functional component 23, and a substrate 24.
[0061] The interposer 21 is, for example, in the form of a Local Silicon Interconnect (LSI), which includes a cover layer 211, a circuit structure 212 formed on at least one surface of the cover layer 211, a bridging element 213 disposed in the cover layer, and a plurality of conductive pillars 214.
[0062] The covering layer 211 is an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid such as epoxy resin.
[0063] In this embodiment, the circuit structure 212 is disposed on the two opposite surfaces of the covering layer 211 and includes a dielectric layer 2120 and a circuit layer 2121 bonded to the dielectric layer 2120, such as a redistribution layer (RDL) specification.
[0064] Furthermore, the material forming the circuit layer 2121 is copper, and the material forming the dielectric layer 2120 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0065] The bridging element 213 is embedded in the cladding layer 211 and electrically connected to the circuit structure 212, wherein the bridging element 213 is of wafer specification.
[0066] The conductive post 214 is embedded in the covering layer 211 and electrically connected to the circuit structure 212, and the material forming the conductive post 214 is a metal such as copper or solder.
[0067] The electronic component 22 is disposed on the intermediate plate 21 and electrically connected to the circuit structure 212 and the bridging component 213.
[0068] In this embodiment, the electronic component 22 is a semiconductor wafer, which is electrically connected to the circuit structure 212 on one surface of the interposer 21 via multiple conductive bumps 220 in a flip-chip manner, and then the conductive bumps 220 are covered with a primer 221. Furthermore, multiple conductive elements 215, such as solder balls or copper bumps, can be formed on the circuit structure 212 on the other surface of the interposer 21.
[0069] In this embodiment, the intermediate board 21 is provided with a plurality of electronic components 22, such as memory chips, graphics processing units (GPUs), etc., so that the bridging element 213 electrically bridges the plurality of electronic components 22 via the circuit structure 212.
[0070] The functional component 23 is integrated into the intermediate board 21 and electrically connected to the circuit structure 212. The functional component 23 includes a capacitor structure 231 and an inductor line 232 electrically connected to the capacitor structure 231.
[0071] In this embodiment, the capacitor structure 231 is in the form of a module element, such as a deep trench capacitor (DTC), which is embedded in the cladding layer 211 and electrically connected to the circuit layer 2121. The inductor line 232 is in the form of a circuit, such as... Figure 3The spiral shape shown is formed in the dielectric layer 2120 of the circuit structure 212 and electrically connected to the capacitor structure 231.
[0072] It should be understood that the inductor 232 can be fabricated simultaneously with the circuit layer 2121 forming the circuit structure 212, and it can present as follows: Figure 3 The planar spiral shape shown can also be formed between multiple circuit layers 2121 to form a three-dimensional spiral shape.
[0073] In this embodiment, the functional component 23 is a balun, which includes at least two capacitor structures 231 and at least two inductor lines 232. For example, Figure 4 The partial circuit diagram shown is designed so that when a single-ended signal S1 is input, it can be output as two differential signals S2 after passing through the inductor line 232(L) and capacitor structure 231(C) of the balun.
[0074] The substrate 24 is used to support the interposer 21. After the electronic component 22 is placed on the interposer 21, it can be placed on the substrate 24 through the plurality of conductive elements 215 to form a wafer-on-a-substrate (CoWoS) structure. In addition, the bottom surface of the substrate 24 is provided with a plurality of conductive elements 240, such as solder balls, so that the electronic package 2 can be electrically connected to an external device, such as a circuit board, through the plurality of conductive elements 240.
[0075] Therefore, the electronic package 2 of this application can eliminate noise by combining the functional component 23 with the intermediate board 21, so as to avoid problems such as blurred or distorted transmitted signals, and thus effectively improve the signal transmission yield of the electronic package 2.
[0076] Figure 5 This is a cross-sectional schematic diagram of the second embodiment of the electronic package 3 of this application. The difference between this embodiment and the first embodiment lies in the packaging method, so the similarities will not be described again below.
[0077] like Figure 5 As shown, the electronic package 3 includes: an interposer 31, a plurality of electronic components 32, at least one functional component 33, and a substrate 34.
[0078] The interposer 31 is, for example, in the form of a redistribution layer (RDL Interposer), which includes a dielectric layer 310 and a circuit layer 311 bonded to the dielectric layer 310.
[0079] The intermediate board 31 has a first side 31a and a second side 31b, and a plurality of conductive elements 312 electrically connected to the circuit layer 311 are embedded on the second side 31b.
[0080] The plurality of electronic components 32 are disposed on the first side 31a of the intermediate plate 31 and electrically connected to the circuit layer 311.
[0081] The functional component 33 is combined with the intermediary plate 31 to serve as a balanced-to-unbalanced converter (Balun), and includes a plurality of (at least two) capacitor structures 331 and a plurality of (at least two) inductor lines 332. The plurality of capacitor structures 331 are disposed on the second side 31b of the intermediary plate 31 (on the same side as the plurality of conductive elements 312) and electrically connected to the plurality of inductor lines 332. The plurality of inductor lines 332 are formed in the dielectric layer 310 of the intermediary plate 31 and can be fabricated simultaneously with the line layer 311 and electrically connected to the line layer 311.
[0082] After the electronic component 32 is placed on the intermediate plate 31, it can be placed on the substrate 34 through the multiple conductive elements 312 to form a wafer-on-a-substrate (CoWoS) structure.
[0083] In summary, the electronic packages 2 and 3 of this application, through the configuration of the functional components 23 and 33, can eliminate noise to avoid problems such as signal blurring and distortion, thus effectively improving the signal transmission yield of the electronic packages 2 and 3. Furthermore, since the functional components 23 and 33 are integrated into the interposer 21 and 31 and are adjacent to the electronic components 22 and 32, signal transmission performance can be effectively improved.
[0084] Furthermore, the electronic package 2,3 can be manufactured using existing semiconductor packaging process materials and equipment, thus eliminating the need to develop new processes or purchase new equipment, thereby avoiding significant additional costs. Therefore, the electronic package 2,3 of this application not only reduces the production cost of the final product but also greatly improves feasibility.
[0085] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. An electronic package, characterized in that, include: Intermediate board, with circuit layer; Electronic components are disposed on the interposer and electrically connected to the circuit layer; as well as The functional component, combined with the interposer board, includes a capacitor structure and an inductor circuit, wherein the capacitor structure is electrically connected to the inductor circuit, and the inductor circuit is electrically connected to the circuit layer.
2. The electronic package as described in claim 1, characterized in that, The electronic package also includes a substrate for supporting the interposer.
3. The electronic package as described in claim 1, characterized in that, The interposer includes a cladding layer, a circuit structure formed on the cladding layer and including the circuit layer, and bridging elements and multiple conductive posts disposed in the cladding layer.
4. The electronic package as described in claim 3, characterized in that, The interposer is provided with multiple electronic components so that the bridging element electrically bridges the multiple electronic components through the circuit layer.
5. The electronic package as described in claim 3, characterized in that, The capacitor structure is embedded in the cladding layer.
6. The electronic package as described in claim 3, characterized in that, The inductor circuit is formed within the circuit structure and is fabricated simultaneously with the circuit layer.
7. The electronic package as claimed in claim 1, characterized in that, The inductor circuit is in the form of a planar spiral or a three-dimensional spiral.
8. The electronic package as claimed in claim 1, characterized in that, The functional component is a balun, which includes at least two capacitor structures and at least two inductor lines.
9. The electronic package as claimed in claim 1, characterized in that, The capacitor is structured as a modular component.
10. The electronic package as claimed in claim 1, characterized in that, The interposer has opposing first and second sides and includes a dielectric layer and a circuit layer bonded to the dielectric layer.
11. The electronic package as claimed in claim 10, characterized in that, The electronic component is located on the first side of the interposer and is electrically connected to the circuit layer.
12. The electronic package as claimed in claim 10, characterized in that, The capacitor structure is attached to the second side of the intermediate plate.
13. The electronic package as claimed in claim 10, characterized in that, The inductor circuit is formed in the dielectric layer of the interposer and is fabricated simultaneously with the circuit layer.