Semiconductor package structure

Abstract

The utility model provides a kind of semiconductor packaging structure, it is related to the technical field of semiconductor packaging.The semiconductor packaging structure includes substrate, first chip, metal sheet and second chip;Substrate includes first outer pin, central pad and second outer pin, first outer pin, central pad and second outer pin are sequentially spaced;First chip and second chip are spaced, and respectively connected to central pad;One end of metal sheet is connected first chip, the other end is connected first outer pin;Second chip and second outer pin are connected in conduction.The semiconductor packaging structure can guarantee that semiconductor packaging structure has excellent conductivity and heat dissipation, especially suitable for the packaging product of high-power MOSFET in car.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure. Background Technology

[0002] Shrink Small Outline Package (SSOP), a typical integrated circuit packaging form, is a miniaturized version of the Small Outline Package (SOP) packaging system, particularly suitable for high-density I / O chip packaging needs. However, current SSOP packaging technology generally employs a single-chip stacking architecture, which presents two major technical bottlenecks: firstly, the package's thermal resistance is relatively high; secondly, the manufacturing process is complex. Furthermore, the wire bonding interconnection method it uses easily introduces significant parasitic inductance effects, thus limiting the device's high-frequency performance. In high-density packaging applications, the heat dissipation challenges and signal integrity issues brought about by multi-chip integration must also be considered, further increasing the difficulty of implementing the packaging technology. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor packaging structure to ensure the conductivity and heat dissipation of the semiconductor packaging structure.

[0004] In a first aspect, the semiconductor packaging structure provided by this utility model includes: a substrate, a first chip, a metal sheet, and a second chip; The substrate includes a first external pin, a central pad, and a second external pin, wherein the first external pin, the central pad, and the second external pin are arranged at intervals in sequence. The first chip and the second chip are spaced apart and respectively connected to the central pad; One end of the metal sheet is connected to the first chip, and the other end is connected to the first external pin; The second chip is electrically connected to the second external pin.

[0005] In conjunction with the first aspect, this utility model provides a first possible implementation of the first aspect, wherein the first chip is connected to the central pad through a first conductive adhesive layer, one end of the metal sheet is connected to the first chip through a second conductive adhesive layer, and the other end of the metal sheet is connected to the first external pin through a third conductive adhesive layer.

[0006] In conjunction with the first possible implementation of the first aspect, the present invention provides a second possible implementation of the first aspect, wherein the first conductive adhesive layer, the second conductive adhesive layer and the third conductive adhesive layer are all sintered silver adhesive layers.

[0007] In conjunction with the first aspect, this utility model provides a third possible implementation of the first aspect, wherein the gate of the first chip is connected to the second chip via a first lead.

[0008] In conjunction with the first aspect, this utility model provides a fourth possible implementation of the first aspect, wherein the non-functional pads of the second chip are connected to the second external pins via a second lead.

[0009] In conjunction with the first aspect, this utility model provides a fifth possible implementation of the first aspect, wherein the substrate, the first chip, the metal sheet and the second chip are encapsulated in a plastic encapsulation.

[0010] In conjunction with the fifth possible implementation of the first aspect, this utility model provides a sixth possible implementation of the first aspect, wherein the central pad is provided with a groove, the groove is located between the first chip and the second chip, and the molding compound is filled and cured in the groove.

[0011] In conjunction with the first aspect, this utility model provides a seventh possible implementation of the first aspect, wherein the second chip is connected to the central pad through a non-conductive adhesive layer.

[0012] In conjunction with the seventh possible implementation of the first aspect, this utility model provides an eighth possible implementation of the first aspect, wherein the thickness of the non-conductive adhesive layer is 50 μm to 100 μm.

[0013] In conjunction with the first aspect, this utility model provides a ninth possible implementation of the first aspect, wherein both the first external pin and the second external pin are bent and flush with the mounting surface; The mounting surface is located on the side of the substrate opposite to the first chip and the second chip.

[0014] The present invention provides the following advantages: the substrate includes a first external pin, a central pad, and a second external pin, which are arranged sequentially at intervals. The first chip and the second chip are arranged at intervals and are respectively connected to the central pad. One end of the metal sheet is connected to the first chip and the other end is connected to the first external pin. The second chip is electrically connected to the second external pin. This ensures that the semiconductor packaging structure has excellent conductivity and heat dissipation, and is especially suitable for high-power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) packaging products in automobiles.

[0015] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this utility model, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A cross-sectional view of a semiconductor packaging structure provided in an embodiment of this utility model; Figure 2 A schematic diagram of a substrate for a semiconductor packaging structure provided in an embodiment of this utility model; Figure 3 A schematic diagram of the substrate and the first chip of the semiconductor packaging structure provided in this embodiment of the utility model; Figure 4 A schematic diagram of the substrate, first chip, and metal sheet of the semiconductor packaging structure provided in this embodiment of the utility model; Figure 5 A schematic diagram of a semiconductor packaging structure, including a substrate, a first chip, a metal sheet, and a second chip, provided in an embodiment of this utility model. Figure 6 A schematic diagram of a semiconductor packaging structure provided in an embodiment of this utility model, comprising a substrate, a first chip, a metal sheet, a second chip, a first lead, and a second lead; Figure 7 A cross-sectional view of the semiconductor packaging structure provided in this embodiment of the present invention after processing the molding compound; Figure 8 This is a top view of a semiconductor packaging structure provided in an embodiment of the present invention.

[0018] Icons: 100-Substrate; 110-First external lead; 120-Central pad; 121-Groove; 130-Second external lead; 200-First chip; 201-First conductive adhesive layer; 300-Metal sheet; 301-Second conductive adhesive layer; 302-Third conductive adhesive layer; 400-Second chip; 401-Non-conductive adhesive layer; 500-First lead; 600-Second lead; 700-Encapsulation. Detailed Implementation

[0019] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0020] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this utility model. Furthermore, the terms "first," "second," and "third" are only used to describe differences in name and should not be construed as indicating or implying relative importance. Physical quantities in formulas, unless otherwise specified, should be understood as basic quantities of the International System of Units (SI) base units, or derived quantities derived from basic quantities through mathematical operations such as multiplication, division, differentiation, or integration.

[0021] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0022] like Figures 1 to 8 As shown, the semiconductor packaging structure provided in this embodiment of the present invention includes: a substrate 100, a first chip 200, a metal sheet 300, and a second chip 400; the substrate 100 includes a first external pin 110, a central pad 120, and a second external pin 130, which are arranged sequentially at intervals; the first chip 200 and the second chip 400 are arranged at intervals and are respectively connected to the central pad 120; one end of the metal sheet 300 is connected to the first chip 200, and the other end is connected to the first external pin 110; the second chip 400 is electrically connected to the second external pin 130.

[0023] The substrate 100 serves as the basic support component of the package structure, preferably a lead frame or a printed circuit board based on organic materials (such as a BT resin substrate). The substrate 100 has multiple conductive areas, including a first external pin 110, a central pad 120, and a second external pin 130, which are arranged sequentially at intervals. Specifically, the first external pin 110 is connected to the external circuitry of the package structure for transmitting electrical signals; the central pad 120 serves as a chip mounting area, supporting and electrically connecting the first chip 200 and the second chip 400; and the second external pin 130 is used to connect to the output terminal of the second chip 400.

[0024] The first chip 200 (which may include a MOSFET chip) and the second chip 400 (which may include a control chip) are fixedly connected to the central pad 120 by a soldering process, maintaining a certain spatial distance between them to avoid electrical short circuits or thermal interference. The first chip 200 and the second chip 400 can be the same type or different types of functional chips, such as logic chips, power devices, sensors, etc., to achieve multi-functional integrated packaging.

[0025] In an optional embodiment, the metal sheet 300 is a sheet-like structure made of conductive material, with one end connected to the electrode of the first chip 200 by welding or pressing, and the other end connected to the corresponding connection area of ​​the first external pin 110. The design of the metal sheet 300 can be optimized according to the package size and current carrying capacity, for example, by using materials with excellent conductivity such as copper or aluminum sheets. The output terminal of the second chip 400 is directly connected to the second external pin 130 via a wire or metal sheet to realize signal output. This connection method can be a bonding wire connection or a flip-chip connection to improve connection reliability and package density.

[0026] In this embodiment of the present invention, the first chip 200 is connected to the central pad 120 through the first conductive adhesive layer 201, one end of the metal sheet 300 is connected to the first chip 200 through the second conductive adhesive layer 301, and the other end of the metal sheet 300 is connected to the first external pin 110 through the third conductive adhesive layer 302.

[0027] See Figure 2 During processing, a first conductive adhesive layer 201 is first coated on the surface of the central pad 120 near the first external pin 110, and a third conductive adhesive layer 302 is coated on the surface of the first external pin 110; see [link to documentation]. Figure 3 The first chip 200 is bonded to the first conductive adhesive layer 201 while it is in a semi-cured state; see also Figure 4A second conductive adhesive layer 301 is coated on the first chip 200, and the metal sheet 300 is bonded and fixed while both the second conductive adhesive layer 301 and the third conductive adhesive layer 302 are in a semi-cured state.

[0028] Among them, the first conductive adhesive layer 201, the second conductive adhesive layer 301 and the third conductive adhesive layer 302 are all sintered silver adhesive layers. The semi-cured temperature of the sintered silver adhesive layer is about 200℃ and can be maintained for about 1.5h to 2h.

[0029] See Figure 6 and Figure 7 The gate of the first chip 200 is connected to the second chip 400 through the first lead 500.

[0030] The non-functional pads of the second chip 400 are connected to the second external pin 130 via the second lead 600.

[0031] like Figure 1 and Figure 7 The substrate 100, the first chip 200, the metal sheet 300, and the second chip 400 are encapsulated by the encapsulant 700.

[0032] The molding compound 700 is formed through injection molding and can be made of epoxy molding compound (EMC), which has good insulation properties and mechanical strength, effectively protecting the internal chip and connection structure from mechanical damage and environmental corrosion. After packaging, the first external pin 110 and the second external pin 130 extend to the outside of the molding compound 700 for electrical connection with an external circuit board (such as a PCB), enabling integrated application of the overall system.

[0033] like Figure 1 , Figure 5 , Figure 6 and Figure 7 As shown, the second chip 400 is connected to the central pad 120 through a non-conductive adhesive layer 401, wherein the thickness of the non-conductive adhesive layer 401 is 50μm to 100μm.

[0034] See Figures 1 to 8 The central pad 120 has a groove 121, which is located between the first chip 200 and the second chip 400. The molding compound 700 is filled and cured in the groove 121.

[0035] The groove 121 extends and separates the first chip 200 and the second chip 400. When the first conductive adhesive layer 201 and the non-conductive adhesive layer 401 are coated, excess adhesive can overflow into the groove 121, thereby preventing the first chip 200 and the second chip 400 from being contaminated due to excessive adhesive.

[0036] Furthermore, both the first external lead 110 and the second external lead 130 are bent and flush with the mounting surface; the mounting surface is located on the side of the substrate 100 opposite to the first chip 200 and the second chip 400. The resulting encapsulated body 700, formed by injection molding, yields... Figure 7 The semiconductor package structure shown can be bent to facilitate subsequent soldering of the first external lead 110 and the second external lead 130 onto the PCB board, resulting in the final product shown. Figure 1 The semiconductor package structure shown has the first external pin 110 and the second external pin 130 located outside the molded body 700, which are bent and flush. When soldered to the PCB board, the first chip 200 and the second chip 400 can be attached to the PCB board surface at the same time, and the central pad 120 can be attached to the PCB board surface or form a certain gap.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor packaging structure, characterized in that, include: Substrate (100), first chip (200), metal sheet (300), and second chip (400); The substrate (100) includes a first external pin (110), a central pad (120), and a second external pin (130), wherein the first external pin (110), the central pad (120), and the second external pin (130) are arranged at intervals in sequence; The first chip (200) and the second chip (400) are spaced apart and respectively connected to the central pad (120). One end of the metal sheet (300) is connected to the first chip (200), and the other end is connected to the first external pin (110). The second chip (400) is electrically connected to the second external pin (130).

2. The semiconductor packaging structure according to claim 1, characterized in that, The first chip (200) is connected to the central pad (120) through a first conductive adhesive layer (201), one end of the metal sheet (300) is connected to the first chip (200) through a second conductive adhesive layer (301), and the other end of the metal sheet (300) is connected to the first external pin (110) through a third conductive adhesive layer (302).

3. The semiconductor packaging structure according to claim 2, characterized in that, The first conductive adhesive layer (201), the second conductive adhesive layer (301), and the third conductive adhesive layer (302) are all made of sintered silver adhesive layer.

4. The semiconductor packaging structure according to claim 1, characterized in that, The gate of the first chip (200) is connected to the second chip (400) via a first lead (500).

5. The semiconductor packaging structure according to claim 1, characterized in that, The non-functional pads of the second chip (400) are connected to the second external pin (130) via the second lead (600).

6. The semiconductor packaging structure according to claim 1, characterized in that, The substrate (100), the first chip (200), the metal sheet (300) and the second chip (400) are encapsulated in a plastic encapsulation (700).

7. The semiconductor packaging structure according to claim 6, characterized in that, The central pad (120) has a groove (121) located between the first chip (200) and the second chip (400), and the molding compound (700) is filled and cured in the groove (121).

8. The semiconductor packaging structure according to claim 1, characterized in that, The second chip (400) is connected to the central pad (120) through a non-conductive adhesive layer (401).

9. The semiconductor packaging structure according to claim 8, characterized in that, The thickness of the non-conductive adhesive layer (401) is 50 μm to 100 μm.

10. The semiconductor packaging structure according to claim 1, characterized in that, Both the first external pin (110) and the second external pin (130) are bent and flush with the mounting surface; The mounting surface is located on the side of the substrate (100) opposite to the first chip (200) and the second chip (400).

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