Chip package structure

Abstract

A chip packaging structure comprises a substrate, a chip and a dummy chip, the chip is attached to the substrate, and the chip is provided with a plurality of pads adapted to be electrically connected with external lead structures. The chip has a sensitive area, and the dummy chip is attached to the chip and covers at least the sensitive area. The substrate, the chip and the dummy chip are externally covered with an encapsulation layer, and the side of the dummy chip away from the chip has a preset distance from the external surface of the encapsulation layer. The application adds the dummy chip between the sensitive area and the encapsulation layer, increases the physical interval between the sensitive area and the encapsulation layer without changing the original packaging thickness and process framework, reduces the stress intensity directly acting on the sensitive area, reduces the stress influence of the encapsulation layer, and keeps the frequency offset of the chip output within the tolerance range allowed by the terminal application. And thanks to the double buffering mechanism of the DAF adhesive layer and the polished surface, local stress concentration can be effectively avoided, the stress influence of the packaging on the chip is further reduced, and the performance of the chip is significantly improved.

Description

Technical Field

[0001] This application relates to the field of electronic packaging technology, and more particularly to a chip packaging structure. Background Technology

[0002] LQFP (Low-profile Quad Flat Package) is a thin quad flat packaging technology primarily used for large-scale or very large-scale integrated circuits. It features small pin pitch and fine leads, making it suitable for high-frequency applications and surface mount technology (SMT). During the injection molding and subsequent cooling processes, the molding compound (e.g., EMC, epoxy molding compound) undergoes significant shrinkage in LQFP packaging. Due to the differences in thermal expansion coefficients between the molding compound, the chip (silicon), and the lead frame (usually a copper alloy), residual stress is generated inside the chip, especially in specific areas.

[0003] The device characteristics of chips, such as the resonant frequency of crystals, the threshold voltage of transistors, and resistance values, are extremely sensitive to applied mechanical stress. Packaging stress can change the physical characteristics or electrical parameters of these devices, ultimately causing a shift in their output frequency, leading to product malfunction or performance degradation.

[0004] Therefore, how to improve the technical defects existing in the prior art has always been a problem that ordinary people skilled in the art need to solve. Utility Model Content

[0005] The purpose of this application is to provide a chip packaging structure that, for MCU chips with sensitive areas, can reduce the stress intensity directly acting on the sensitive areas, keeping the chip output frequency offset within the tolerance range allowed by the end application, resulting in better product performance.

[0006] The technical solution provided by this utility model is as follows:

[0007] A chip packaging structure, comprising:

[0008] Substrates, chips, and counterfeit chips;

[0009] The chip is attached to a substrate and has several pads for electrical connection to an external wire structure; the chip has a sensitive area, and the dummy chip is attached to the chip and at least covers the sensitive area;

[0010] The substrate, the chip, and the dummy chip are covered with a sealing layer, and the side of the dummy chip away from the chip is at a predetermined distance from the outer surface of the sealing layer.

[0011] In some embodiments, the thickness of the dummy film is greater than 100 μm, and the preset distance is greater than 100 μm.

[0012] In some implementations, the projected area of ​​the dummy chip on the chip is larger than the area of ​​the sensitive region of the chip, and the projected area of ​​the dummy chip on the chip is smaller than the area of ​​the chip.

[0013] In some implementations, the edge of the dummy chip's orthogonal projection onto the chip extends at least 50 μm beyond the edge of the sensitive region.

[0014] In some embodiments, the pads are connected to bonding wires, among which there are close-pitch bonding wires that are closest to the orthogonal projection of the dummy die on the chip, and the distance between the close-pitch bonding wires and the edge of the orthogonal projection of the dummy die on the chip is not less than 100 μm.

[0015] In some embodiments, a portion of the bonding wires is electrically connected to the substrate and the chip; another portion is electrically connected to the chip and the external conductive structure.

[0016] The external conductive structure includes a first conductive part and a second conductive part that are electrically connected. The first conductive part is electrically connected to the bonding wire and is encased in the sealing layer, while the second conductive part is exposed outside the sealing layer and is used to connect to an external circuit.

[0017] In some implementations, the thickness of the dummy piece is uniform throughout.

[0018] In some embodiments, the two end walls of the dummy sheet in the thickness direction have flat surfaces.

[0019] In some embodiments, the dummy chip is attached to the side of the chip away from the substrate by adhesive bonding.

[0020] In some embodiments, an adhesive layer is formed between the dummy chip and the chip, the adhesive layer having a thickness of 25 μm.

[0021] The technical advantages of this application are as follows:

[0022] 1. In this application, by adding a dummy chip between the sensitive area and the sealing layer, the physical spacing between the sensitive area and the sealing layer is increased, which significantly reduces the stress intensity directly acting on the sensitive area, reduces the influence of sealing layer stress, and keeps the chip output frequency offset within the tolerance range allowed by the end application.

[0023] 2. In this application, the thickness of the dummy chip is greater than 100μm, and the preset distance between the side of the dummy chip away from the chip and the outer surface of the encapsulation layer is greater than 100μm. Without changing the original packaging thickness and process framework, both the workability of the packaging is ensured and the best protection effect is achieved.

[0024] 3. In this application, the two end walls of the dummy chip in the thickness direction are flat surfaces, which can reduce the stress transfer efficiency between the encapsulation layer and the dummy chip, thereby effectively reducing the encapsulation stress on the chip and keeping the chip output frequency offset within the tolerance range allowed by the end application, thus improving product performance. Attached Figure Description

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0026] Figure 1 It is a chip packaging structure in existing technology;

[0027] Figure 2 This is a chip packaging structure provided in one embodiment of the present application;

[0028] Figure 3 This is a partial top view of a chip package structure provided in one embodiment of this application.

[0029] Explanation of icon numbers:

[0030] 100, Substrate; 200, Chip; 210, Pad; 220, Bonding wire; 221, Close-pitch bonding wire; 300, Dummy chip; 400, External conductor structure; 410, First conductive part; 420, Second conductive part; 500, Encapsulating layer; 600, Adhesive layer. Detailed Implementation

[0031] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the specific implementation methods of this application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0033] To keep the drawings concise, each drawing only schematically shows the parts relevant to this application, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some drawings, only one of the components with the same structure or function is schematically shown, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0034] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0035] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] In the embodiments shown in the accompanying drawings, the directional indications (such as up, down, left, right, front, and back) used to explain the structure and movement of the various components of this application are relative rather than absolute. These descriptions are appropriate when these components are in the positions shown in the drawings. If the description of the positions of these components changes, these directional indications also change accordingly.

[0037] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0038] See Figure 1 Currently, in LQFP packaging, the molding compound undergoes significant shrinkage during injection molding and subsequent cooling processes. Due to the differences in the coefficients of thermal expansion between the molding compound, the chip, and the lead frame, residual stress is generated inside the chip, especially in specific areas. The chip's device characteristics, such as the resonant frequency of the crystal, the threshold voltage of the transistor, and its resistance, are extremely sensitive to applied mechanical stress. Packaging stress can alter the physical characteristics or electrical parameters of these devices, ultimately causing a shift in their output frequency. This is especially true for MCU chips with sensitive areas, where the shift exceeds ±0.7%, exceeding the tolerance range allowed by the end application (within ±0.3%), leading to product malfunction or performance degradation.

[0039] For this, see 2 and Figure 3This application provides a chip 200 packaging structure, including a substrate 100, a chip 200, and a dummy die 300. The chip 200 is attached to the substrate 100 and has a plurality of pads 210 for electrical connection with an external wire structure 400 (lead frame). The chip 200 has a sensitive area, and the dummy die 300 is attached to the chip 200 and at least covers the sensitive area. The substrate 100, the chip 200, and the dummy die 300 are covered by an encapsulation layer 500, and the side of the dummy die 300 away from the chip 200 is at a predetermined distance 'a' from the outer surface of the encapsulation layer 500 (molded encapsulation layer).

[0040] This embodiment increases the physical spacing between the sensitive area and the sealing layer 500 by adding a dummy die 300 between the sensitive area and the sealing layer 500. This significantly reduces the stress intensity directly acting on the sensitive area and minimizes the stress impact on the sealing layer 500, keeping the output frequency offset of the chip 200 within the tolerance range allowed by the end application. In actual production, the dummy die 300 can be made of the same silicon wafer as the chip 200 or a dummy die of other isotropic materials. Thanks to the isotropy of the dummy die 300, local stress concentration can be effectively avoided, further reducing the stress impact on the packaged chip 200 and improving the fatigue life of the chip 200.

[0041] Specifically, the thickness of the dummy wafer 300 is greater than 100μm, and the aforementioned preset distance a is also greater than 100μm, in order to ensure the workability of the encapsulation, specifically the fluidity and reliability of the molding process.

[0042] Of course, in actual production, the specific thickness of the dummy chip 300 should be flexibly set according to different chip 200 and packaging requirements. While achieving the best protection effect, the smallest possible value should be selected, neither increasing the thickness of the package form too much (or even not increasing it at all) nor increasing the packaging cost too much. For example, the thickness of the main chip 200 in an LQFP64 package is about 280μm, and the preferred thickness of the dummy chip 300 is 160μm. This will not be elaborated further, as it is all within the scope of protection of this application.

[0043] Specifically, the dummy wafer 300 has a projected area on the chip 200 that is larger than the area of ​​the sensitive region to ensure that the dummy wafer 300 completely covers the sensitive region. In actual production, the edge of the projected area of ​​the dummy wafer 300 on the chip 200 preferably extends at least 50 μm beyond the edge of the sensitive region. Simultaneously, the projected area of ​​the dummy wafer 300 on the chip 200 is smaller than the area of ​​the chip 200, which also aims to ensure the workability of the package. The shape of the dummy wafer can be regular or irregular; no restrictions are placed here, and all are within the scope of protection of this application.

[0044] Specifically, the pad 210 is connected to a bonding wire 220, among which the bonding wire 220 has a close-pitch bonding wire 221 that is closest to the orthogonal projection of the dummy die 300 on the chip 200. The distance b between the close-pitch bonding wire 221 and the edge of the orthogonal projection of the dummy die 300 on the chip 200 is not less than 100μm, so as to avoid interfering with the wire bonding.

[0045] In actual production, a portion of the bonding wires 220 electrically connects the substrate 100 and the chip 200; another portion electrically connects the chip 200 and an external conductive structure. The external conductive structure includes a first conductive portion 410 and a second conductive portion 420 that are electrically connected. The first conductive portion 410 is electrically connected to the bonding wires 220 and is encapsulated within the sealing layer 500, while the second conductive portion 420 is exposed outside the sealing layer 500 and is used to connect to external circuits.

[0046] Preferably, the thickness of the dummy chip 300 is uniform throughout, ensuring a uniform overall stress distribution and avoiding localized stress concentration, thereby achieving the best protective effect. Furthermore, the two end walls of the dummy chip 300 in the thickness direction have flat surfaces, specifically polished to ensure a smooth surface. This reduces the stress transfer efficiency between the sealing layer 500 and the dummy chip 300, effectively reducing the stress on the chip 200 from the sealing layer 500. This keeps the output frequency offset of the chip 200 within the tolerance range allowed by the end application, improving product performance.

[0047] Specifically, the dummy chip 300 is attached to the side of the chip 200 away from the substrate 100 by adhesive bonding, for example, by using DAF (Die Attach Film) bonding, forming a continuous adhesive interface (adhesive layer 600) between the dummy chip 300 and the chip 200.

[0048] DAF (Dielectric Acid Bonding Adhesive) is a key material used in semiconductor packaging, primarily for high-reliability bonding of chip 200 to substrate 100 or lead frame. DAF is typically based on epoxy resin and manufactured into a thin film using a special process, with a thickness as low as 5μm, suitable for ultra-thin chip 200 (<100μm, even <50μm) packaging. DAF offers high precision and consistency; compared to traditional fluidized die-attach adhesive (DAP), it avoids issues such as adhesive overflow and uneven thickness, resulting in higher process precision and improved chip 200 performance.

[0049] In actual production, the thickness of the adhesive layer 600 is preferably 25μm, which can simultaneously take into account the buffering performance and process cost, and the structural design is more reasonable and practical.

[0050] In contrast, the chip 200 is attached to the substrate 100 by adhesive bonding, such as using DAF (Die Attach Film), forming a continuous adhesive interface (adhesive layer 600) between the substrate 100 and the chip 200.

[0051] The chip packaging structure provided in the above embodiments can reduce the stress intensity in the sensitive areas of chip 200 by 30%-60%, without significantly increasing or even changing the original packaging thickness and process framework, which is beneficial for packaging miniaturization and low packaging cost. Furthermore, this embodiment effectively improves the fatigue life of chip 200 through a DAF adhesive layer combined with a polished surface dual buffering mechanism.

[0052] In actual production, the pads 210 on the surface of chip 200 are used as alignment marks to ensure that the dummy chip 300 accurately covers the sensitive areas. That is, the existing pads 210 on chip 200 are used as reference points for visual or mechanical alignment, making reasonable use of the original structure without the need for additional markings, saving product area and manufacturing processes, resulting in high structural utilization. Furthermore, the size and position of the pads 210 are precisely defined during wafer photolithography, with high accuracy (within ±1μm), ensuring that the dummy chip 300 completely covers the sensitive areas.

[0053] Furthermore, the chip packaging structure may also include a heat dissipation structure, with one end of the heat dissipation structure contacting the chip 200 and the other end passing through the sealing layer 500 and exposed to the air. Alternatively, the heat dissipation structure may contact the dummy chip 300, utilizing heat transfer between the dummy chip 300 and the chip 200 to dissipate heat from the chip 300. The heat dissipation structure can be a metal heat sink or a metal pillar; in particular, when a metal pillar is used, it can also act as a reinforcing element, improving the overall strength of the chip packaging structure. Of course, in actual production, other structures, such as plate-like structures, can be added as reinforcing elements for structural strengthening; these will not be elaborated upon here, but are all within the scope of protection of this application.

[0054] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0055] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of this application. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A chip packaging structure, characterized in that, include: Substrates, chips, and counterfeit chips; The chip is attached to a substrate and has several pads for electrical connection to an external wire structure; the chip has a sensitive area, and the dummy chip is attached to the chip and at least covers the sensitive area; The substrate, the chip, and the dummy chip are covered with a sealing layer, and the side of the dummy chip away from the chip is at a predetermined distance from the outer surface of the sealing layer.

2. The chip packaging structure according to claim 1, characterized in that, The thickness of the dummy film is greater than 100 μm, and the preset distance is greater than 100 μm.

3. The chip packaging structure according to claim 1, characterized in that, The projected area of ​​the fake chip on the chip is larger than the area of ​​the sensitive region of the chip, and the projected area of ​​the fake chip on the chip is smaller than the area of ​​the chip.

4. The chip packaging structure according to claim 3, characterized in that, The edge of the dummy chip's orthogonal projection onto the chip extends at least 50 μm beyond the edge of the sensitive area.

5. The chip packaging structure according to claim 3, characterized in that, The pads are connected to bonding wires, and among the bonding wires are close-pitch bonding wires that are closest to the orthogonal projection of the dummy chip on the chip. The distance between the close-pitch bonding wires and the edge of the orthogonal projection of the dummy chip on the chip is not less than 100 μm.

6. The chip packaging structure according to claim 5, characterized in that, A portion of the bonding wires electrically connects the substrate and the chip; another portion electrically connects the chip and the external conductive structure. The external conductive structure includes a first conductive part and a second conductive part that are electrically connected. The first conductive part is electrically connected to the bonding wire and is encased in the sealing layer, while the second conductive part is exposed outside the sealing layer and is used to connect to an external circuit.

7. The chip packaging structure according to any one of claims 1-6, characterized in that, The thickness of the fake film is the same everywhere.

8. The chip packaging structure according to any one of claims 1-6, characterized in that, The two end walls of the dummy film in the thickness direction have flat surfaces.

9. The chip packaging structure according to any one of claims 1-6, characterized in that, The dummy chip is attached to the side of the chip away from the substrate by adhesive bonding.

10. The chip packaging structure according to claim 9, characterized in that, An adhesive layer with a thickness of 25 μm is formed between the dummy chip and the chip.

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