A stacked dual-chip fastening package structure

Abstract

The utility model discloses a kind of laminated double-chip fastening packaging structures, specifically related to chip packaging technical field, including: substrate;Double-chip laminated assembly, the double-chip laminated assembly is set at the top side of substrate, and double-chip laminated assembly includes first chip and second chip, the bottom side of the first chip is connected with substrate, and the second chip is above the first chip.The utility model is arranged in first chip and second chip up-down laminated layout mode, can greatly compress the planar space occupied by packaging, realizes double-chip integrated design in limited substrate area, and by setting reinforcing assembly between first chip and second chip, first chip and second chip can be fastened together, cooperate with the further embedding positioning of first chip in card slot, to form multiple fastening, to effectively prevent chip from deviating, loose, greatly improve the overall stability of packaging structure.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, specifically to a stacked dual-chip fastening packaging structure. Background Technology

[0002] A chip is an integrated circuit whose circuits are fabricated on the surface of a semiconductor chip. It is also known as a thin-film integrated circuit. There is another type called a thick-film integrated circuit, which is a miniaturized circuit composed of independent semiconductor devices and passive components integrated onto a substrate or circuit board.

[0003] Currently, existing dual-chip packages mostly consist of two side-by-side chips soldered onto the same substrate via pins. This not only occupies a large amount of substrate space, but also relies on a single adhesive or soldering method for the connection between the chip and the substrate. The chip is prone to shifting or loosening, which greatly affects the overall package structure's tightness and stability. Therefore, this application proposes a stacked dual-chip fastening package structure. Utility Model Content

[0004] The purpose of this invention is to provide a stacked dual-chip fastening packaging structure. By adopting a stacked arrangement of the first and second chips, the planar space occupied by the packaging can be significantly reduced, and a dual-chip integrated design can be achieved within a limited substrate area. Furthermore, by setting a reinforcing component between the first and second chips, the first and second chips can be fastened together. With the help of a slot, the first chip can be further embedded and positioned, thereby forming multiple fastenings to effectively prevent chip displacement and loosening, greatly improving the overall stability of the packaging structure and solving the aforementioned shortcomings in the technology.

[0005] To achieve the above objectives, this utility model provides the following technical solution: a stacked dual-chip fastening package structure, comprising: substrate; A dual-chip stacked assembly is disposed on the top side of a substrate and includes a first chip and a second chip. The bottom side of the first chip is connected to the substrate, the second chip is located above the first chip, and an adhesive layer is provided between the second chip and the first chip. A reinforcing component is provided between the first chip and the second chip. The first chip has multiple first pins on all four ends, and the second chip has second pins on all four ends. The first and second pins are fixedly connected to the substrate by soldering.

[0006] Preferably, a molding compound is disposed on the top of the substrate and outside the dual-chip stack assembly.

[0007] Preferably, the reinforcement component includes a first threaded cylinder disposed at each of the four ends of the first chip, and a second threaded cylinder disposed at each of the four ends of the second chip above the first threaded cylinder. A threaded post is screwed between the first threaded cylinder and the second threaded cylinder, and a fixing cap is provided at the top of the threaded post.

[0008] Preferably, the top four sides of the substrate have multiple sets of first slots facing the first pin, and the top four sides of the substrate have multiple sets of second slots facing the second pin.

[0009] Preferably, a first overflow cavity is provided on one side of the first slot, a second overflow cavity is provided on one side of the second slot, and a through groove is provided between the second slot and the first slot on one side.

[0010] Preferably, a slot is provided in the middle of the top side of the substrate, and the bottom end of the first chip is embedded in the slot.

[0011] The technical effects and advantages provided by this utility model in the above technical solution are as follows: By adopting a stacked layout of the first and second chips, the planar space occupied by the package can be significantly reduced, and a dual-chip integrated design can be achieved within a limited substrate area. Furthermore, by setting a reinforcing component between the first and second chips, the first and second chips can be firmly secured together. With the help of the slot, the first chip can be further embedded and positioned, thus forming multiple fastenings to effectively prevent the chip from shifting or loosening, and greatly improving the overall stability of the package structure. By setting up multiple sets of first and second slots, and with the insertion of each set of first and second pins, the stability of the chip on the substrate can be greatly enhanced. In addition, with the first overflow cavity, second overflow cavity and through groove inside the slot, the solder liquid can enter and solidify inside, thereby further securing the pins firmly to the substrate, thus greatly ensuring the chip's fastening effect. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a schematic diagram of the overall structure of this utility model; Figure 2 This is a schematic diagram of the internal structure of the present invention; Figure 3 This is a schematic diagram of the structure of the substrate of this utility model; Figure 4This is a partial cross-sectional view of the substrate of this utility model; Figure 5 This is a schematic diagram of the connection structure between the first chip and the second chip of this utility model.

[0014] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Molding layer; 3. First chip; 4. Adhesive layer; 5. Second chip; 6. First pin; 7. Second pin; 8. First threaded cylinder; 9. Second threaded cylinder; 10. Threaded post; 11. Fixing cap; 12. Slot; 13. First slot; 14. Second slot; 15. First overflow cavity; 16. Second overflow cavity; 17. Through groove. Detailed Implementation

[0015] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings.

[0016] This utility model provides, for example Figures 1-5 The stacked dual-chip fastening package structure shown includes: substrate1; A dual-chip stacked assembly is disposed on the top side of a substrate 1 and includes a first chip 3 and a second chip 5. The bottom side of the first chip 3 is connected to the substrate 1, and the second chip 5 is located above the first chip 3. An adhesive layer 4 is provided between the second chip 5 and the first chip 3, and a reinforcing component is provided between the first chip 3 and the second chip 5. Based on this, by adopting the stacked layout of the first chip 3 and the second chip 5, the planar space occupied by the package is greatly reduced, and the dual-chip integrated design is realized within the limited area of ​​the substrate 1.

[0017] The reinforcement component includes a first threaded cylinder 8 disposed at the four ends of the first chip 3, and a second threaded cylinder 9 disposed at each of the four ends of the second chip 5 above the first threaded cylinder 8. A threaded post 10 is screwed between the first threaded cylinder 8 and the second threaded cylinder 9, and a fixing cap 11 is provided at the top of the threaded post 10.

[0018] A slot 12 is provided in the middle of the top side of the substrate 1, and the bottom end of the first chip 3 is embedded in the slot 12.

[0019] After the first chip 3 and the second chip 5 are arranged vertically, the first threaded cylinders 8 at the four ends of the first chip 3 can be aligned with the second threaded cylinders 9 at the four ends of the second chip 5 respectively. Then, the threaded post 10 can be screwed into each set of first threaded cylinders 8 and second threaded cylinders 9 through the fixing cap 11, so that the first chip 3 and the second chip 5 can be fastened together. Furthermore, the first chip 3 is embedded and positioned in conjunction with the set slot 12, so as to form multiple fastenings to effectively prevent the chip from shifting or loosening, and greatly improve the overall stability of the packaging structure.

[0020] The first chip 3 has multiple first pins 6 on all four ends, and the second chip 5 has second pins 7 on all four ends. The first pins 6 and the second pins 7 are fixedly connected to the substrate 1 by soldering.

[0021] A molding layer 2 is disposed on the top of the substrate 1 and outside the dual-chip stacked assembly.

[0022] Multiple sets of first slots 13 facing the first pin 6 are provided on the top four sides of the substrate 1, and multiple sets of second slots 14 facing the second pin 7 are provided on the top four sides of the substrate 1.

[0023] A first overflow cavity 15 is provided on one side of the interior of the first slot 13, a second overflow cavity 16 is provided on one side of the interior of the second slot 14, and a through groove 17 is provided between the second slot 14 and the first slot 13 on one side.

[0024] By setting multiple sets of first slots 13 and second slots 14 corresponding to the solder pins of the dual-chip stacked assembly, the first pin 6 on the first chip 3 can be inserted into each first slot 13, and the second pin 7 on the second chip 5 can be inserted into each second slot 14. This can further enhance the stability of the chip on the substrate 1. During soldering, the molten solder can flow through the gap into the first overflow cavity 15 and the second overflow cavity 16 inside the first slot 13 and the second slot 14. The solder can also be connected through the through groove 17. After cooling and solidification, the pins can be firmly fixed to the substrate 1, thereby greatly ensuring the chip's fastening effect.

[0025] The foregoing description only illustrates certain exemplary embodiments of the present invention. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A stacked dual-chip fastening package structure, characterized in that, include: substrate(1); A dual-chip stacked assembly is disposed on the top side of a substrate (1), and the dual-chip stacked assembly includes a first chip (3) and a second chip (5). The bottom side of the first chip (3) is connected to the substrate (1), the second chip (5) is located above the first chip (3), and an adhesive layer (4) is provided between the second chip (5) and the first chip (3). A reinforcing component is provided between the first chip (3) and the second chip (5). The first chip (3) has multiple first pins (6) on all four ends, and the second chip (5) has second pins (7) on all four ends. The first pins (6) and the second pins (7) are fixedly connected to the substrate (1) by soldering.

2. The stacked dual-chip fastening packaging structure according to claim 1, characterized in that: A molding layer (2) is disposed on the top of the substrate (1) and outside the dual-chip stack assembly.

3. The stacked dual-chip fastening packaging structure according to claim 1, characterized in that: The reinforcement component includes a first threaded cylinder (8) disposed at the four ends of the first chip (3), and a second threaded cylinder (9) disposed at each of the four ends of the second chip (5) above the first threaded cylinder (8). A threaded post (10) is screwed between the first threaded cylinder (8) and the second threaded cylinder (9), and a fixing cap (11) is provided at the top of the threaded post (10).

4. The stacked dual-chip fastening packaging structure according to claim 1, characterized in that: The substrate (1) has multiple sets of first slots (13) facing the first pin (6) on all four sides of the top, and multiple sets of second slots (14) facing the second pin (7) on all four sides of the top.

5. The stacked dual-chip fastening packaging structure according to claim 4, characterized in that: The first slot (13) has a first overflow cavity (15) on one side inside, the second slot (14) has a second overflow cavity (16) on one side inside, and a through groove (17) is provided between the second slot (14) and the first slot (13) on one side.

6. The stacked dual-chip fastening package structure according to claim 1, characterized in that: A slot (12) is provided in the middle of the top side of the substrate (1), and the bottom end of the first chip (3) is embedded in the slot (12).

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