A radar hardware security monitoring device and vehicle

Abstract

The embodiment of the application discloses a radar hardware safety monitoring device and a vehicle, relates to the technical field of safety monitoring devices, and can reduce waste of power output resources. The device comprises a microcontroller, a millimeter wave radar chip, a power management chip and a logic gate circuit. The power management chip comprises a power output end, a general input / output pin and a reset control output pin, and is connected to the power input end of the microcontroller and the millimeter wave radar chip through the power output end respectively. The millimeter wave radar chip has a fault signal output pin and a reset pin, and the fault signal output pin is electrically connected to the general input / output pin of the microcontroller. The power management chip has a power fault reset signal pin, the first input end of the logic gate circuit is electrically connected to the reset control output pin, the second input end is electrically connected to the power fault reset signal pin, and the output end of the logic gate circuit is electrically connected to the reset pin of the millimeter wave radar chip. The application is suitable for safety monitoring scenes.

Description

Technical Field

[0001] This application relates to the field of security monitoring device technology, and in particular to a radar hardware security monitoring device and vehicle. Background Technology

[0002] Currently, intelligent vehicles commonly employ forward-facing millimeter-wave radar as the core sensor to achieve key functions such as Autonomous Emergency Braking (AEB). In terms of hardware architecture, mainstream forward-facing radar solutions typically combine a microcontroller unit (MCU) with a millimeter-wave radar chip (MMIC). The MMIC is responsible for integrating the antenna array, transmitting and receiving microwave signals, and preprocessing, while the MCU handles system control, communication management, and fault diagnosis. Since both are involved in implementing safety functions and must meet functional safety requirements, their operational status needs to be effectively monitored.

[0003] In existing technologies, to meet the functional safety monitoring requirements of MCUs and MMICs, a hardware design scheme using dual power management ICs (PMICs) is often adopted. Specifically, by configuring independent PMICs for the MCU and MMIC respectively, independent power supply and fault monitoring for both are achieved. In this architecture, when the MCU or MMIC outputs a low-level signal through a fault signal output pin, the corresponding PMIC will respond and pull down the reset pin signal, thereby resetting the faulty chip.

[0004] However, this dual-PMIC scheme has a significant drawback: since the number of power rails required by the MCU and MMIC in the front radar system is limited, using two PMICs will result in some power output resources being idle, thus wasting some power rail resources. Utility Model Content

[0005] In view of this, embodiments of this application provide a radar hardware security monitoring device that can reduce the waste of power output resources.

[0006] In a first aspect, embodiments of this application provide a radar hardware security monitoring device, comprising: a microcontroller, a millimeter-wave radar chip, a power management chip, and logic gate circuits; the power management chip includes: a power output terminal, a general-purpose input / output pin, and a reset control output pin, wherein the power management chip is connected to the corresponding power input terminals of the microcontroller and the millimeter-wave radar chip respectively through the power output terminal, for providing the required operating power to the microcontroller and the millimeter-wave radar chip; the millimeter-wave radar chip has a fault signal output pin and a reset pin, wherein the fault signal output pin is electrically connected to the general-purpose input / output pin of the microcontroller; the power management chip has a power fault reset signal pin, and the logic gate circuit has a first input terminal and a second input terminal; the first input terminal of the logic gate circuit is electrically connected to the reset control output pin, the second input terminal is electrically connected to the power fault reset signal pin, and the output terminal of the logic gate circuit is electrically connected to the reset pin of the millimeter-wave radar chip.

[0007] Optionally, a pull-down resistor is provided at the node between the output of the logic gate circuit and the reset pin.

[0008] Optionally, the device further includes a DC-DC conversion module, the output of which is electrically connected to the power input of the power management chip, for providing pre-power conversion for the power management chip.

[0009] Optionally, a filter capacitor is provided between the power input terminal and ground of the logic gate circuit to filter the output reset signal.

[0010] Optionally, the power management chip is a single chip that integrates multiple power rails. These power rails are uniformly configured to simultaneously provide the required operating power to both the microcontroller and the millimeter-wave radar chip.

[0011] Optionally, a pull-up resistor is provided between the fault signal output pin of the millimeter-wave radar chip and the power rail supplied by the power management chip. The fault signal output pin of the millimeter-wave radar chip is an open-drain output structure or an open-collector output structure, and is connected to the power rail through the pull-up resistor.

[0012] Optionally, the millimeter-wave radar chip is connected to the microcontroller via a serial peripheral interface.

[0013] Optionally, the millimeter-wave radar chip is a monolithic integrated structure, including a millimeter-wave transmitter, a millimeter-wave receiver, a local oscillator signal generation circuit, and an antenna array unit for radiating and receiving electromagnetic waves. The millimeter-wave transmitter includes one or more transmission channels, and the millimeter-wave receiver includes one or more reception channels. The transmission channels are connected to the transmitting antenna array unit, and the reception channels are connected to the receiving antenna array unit. The local oscillator signal generated by the local oscillator signal generation circuit is connected to the transmission channels and reception channels respectively through a power distribution network.

[0014] Optionally, the power management chip further includes a power status indicator pin, which is electrically connected to the second input terminal of the logic gate circuit and is used to output a signal indicating a power failure of the power management chip itself to the logic gate circuit.

[0015] Secondly, embodiments of this application provide a vehicle, including: a vehicle body; a forward-facing radar system disposed at the front of the vehicle body for detecting target information in front of the vehicle; and a vehicle control unit; wherein the forward-facing radar system includes the radar hardware security monitoring device described in any of the first aspects; the vehicle control unit is communicatively connected to a microcontroller in the radar hardware security monitoring device, for receiving target information processed by the microcontroller, and executing the vehicle's automatic emergency braking control function according to the processed target information.

[0016] This application provides a specific architecture for a radar hardware safety monitoring device and vehicle. A hardware monitoring hub is constructed by introducing logic gate circuits. The first input of the logic gate circuit is electrically connected to the reset control output pin, the second input is electrically connected to the power fault reset signal pin, and the output is electrically connected to the reset pin of the millimeter-wave radar chip. In this way, the logic gate circuit can respond to and comprehensively process fault indications from either the microcontroller or the power management chip without delay. These indications can be immediately converted into a reset action for the millimeter-wave radar chip through this single path. This hardware-level, parallel monitoring and centralized response mechanism based on logic gate circuits, and the system architecture where the power management chip simultaneously powers both the microcontroller and the millimeter-wave radar chip, simultaneously meets the functional safety monitoring requirements of both the microcontroller and the millimeter-wave radar chip without requiring additional dedicated monitoring chips. This ensures system safety while reducing power output resource waste. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a forward-facing radar system with a dual-PMIC architecture in the prior art. Figure 2 This is a schematic diagram of the structure of a radar hardware security monitoring device provided in an embodiment of this application; Figure 3 This is a schematic diagram of a forward radar hardware security monitoring block diagram with a single PMIC architecture provided in an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0020] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0021] Figure 1 This is a schematic diagram of a forward-facing radar system with a dual-PMIC architecture in the prior art, such as... Figure 1The system core comprises three main components: an MCU, a MMIC, and power management chips PMIC1 and PMIC2. During operation, PMIC1 provides power to the MCU and monitors it, while PMIC2 provides power to the MMIC and monitors it, forming an independent dual-power supply and monitoring system. Regarding fault handling, the MCU connects to PMIC1 via its fault indication output pin nERR_OUT1 (this pin is represented by an underscore in the program code or schematic diagram, such as nERR_OUT1, but is expressed without underscores in the text of this specification. Those skilled in the art should understand that both refer to the same technical feature, and the naming difference stems only from coding conventions and documentation habits). When a fault is detected, the MCU triggers PMIC1 to reset the MCU via the reset control output pin N RESET1. The MMIC, on the other hand, resets the MCU via its fault indication output pin nERR_OUT1. OUT2 is connected to PMIC2. In case of a fault, PMIC2 resets the MMIC through the reset pin RESET2. In terms of communication architecture, the MCU and MMIC exchange data through a serial peripheral interface bus. At the same time, the MCU communicates with other control units in the vehicle through the Controller Area Network (CAN) bus. The MMIC is directly connected to the antenna to realize the transmission (TX) and reception (RX) functions of millimeter wave signals.

[0022] Since the number of power rails required by the MCU and MMIC is limited, using two PMICs to power them separately would result in a large number of power rail resources being idle. Furthermore, using two PMICs that meet functional safety requirements significantly increases the bill of materials cost. Moreover, the dual-PMIC architecture requires separate configuration and monitoring, greatly increasing system complexity and development difficulty. Therefore, this application provides a radar hardware safety monitoring device to break away from the redundant design approach used in existing solutions to meet functional safety requirements, reducing resource waste and design complexity.

[0023] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0024] One embodiment of this application provides a radar hardware security monitoring device that can reduce the waste of power output resources.

[0025] Figure 2 This is a schematic diagram of the structure of a radar hardware security monitoring device according to an embodiment of this application, as shown below. Figure 2The radar hardware security monitoring device in this embodiment includes: a microcontroller 1, a millimeter-wave radar chip 2, a power management chip 3, and a logic gate circuit 4. The power management chip 3 includes: a power output terminal 31, a general-purpose input / output pin 32, and a reset control output pin 33. The power management chip 1 is connected to the corresponding power input terminals of the microcontroller 1 and the millimeter-wave radar chip 2 through the power output terminal 31, respectively, to provide the required operating power to the microcontroller 1 and the millimeter-wave radar chip 2. The millimeter-wave radar chip 2 has a fault signal output pin 21 and a reset pin 22. The fault signal output pin 21 is electrically connected to the general-purpose input / output pin 11 of the microcontroller 1. The power management chip 3 has a power fault reset signal pin 34. The logic gate circuit 4 has a first input terminal 41 and a second input terminal 42. The first input terminal 41 of the logic gate circuit 4 is electrically connected to the reset control output pin 33, the second input terminal 42 is electrically connected to the power fault reset signal pin 34, and the output terminal 43 of the logic gate circuit 4 is electrically connected to the reset pin 22 of the millimeter-wave radar chip 2.

[0026] The hardware safety monitoring device for forward radar of intelligent vehicles provided in this application embodiment aims to meet functional safety requirements with a simplified hardware architecture. The core components include: microcontroller 1, millimeter-wave radar chip 2, power management chip 3, and logic gate circuit 4.

[0027] In the hardware architecture of the security monitoring device, the power management chip 3 supplies power to both the microcontroller 1 and the millimeter-wave radar chip 2 simultaneously through the power output terminal 31, achieving a highly integrated single-chip power supply solution. For security monitoring, the fault signal output pin 21 of the millimeter-wave radar chip 2 is directly connected to the general-purpose input / output (GPIO) pin 11 of the microcontroller 1, enabling the microcontroller 1 to continuously monitor the health status of the radar chip. The key to the entire monitoring system lies in the hardware reset path composed of logic gate circuit 4. Specifically, the first input terminal 41 of the logic gate circuit 4 is connected to the reset control output pin 33 of the power management chip 3, and the second input terminal 42 is connected to the power fault reset signal pin 34 of the power management chip 3; while the output terminal 43 of the logic gate circuit 4 is ultimately connected to the reset pin 22 of the millimeter-wave radar chip 2.

[0028] In this way, the above connection structure forms a redundant hardware-level reset trigger path, ensuring that whether it is a reset command initiated by the microcontroller based on software logic or a hardware alarm triggered by the power management chip detecting its own power failure, the millimeter-wave radar chip can be directly, quickly and reliably forced into a reset state, thereby ensuring that the system can switch to a safe mode in time when a fault occurs.

[0029] This application provides a specific architecture for a radar hardware safety monitoring device. A hardware monitoring hub is constructed by introducing logic gate circuits. The first input of the logic gate circuit is electrically connected to the reset control output pin, the second input is electrically connected to the power fault reset signal pin, and the output is electrically connected to the reset pin of the millimeter-wave radar chip. In this way, the logic gate circuit can respond to and comprehensively process fault indications from either the microcontroller or the power management chip without delay. These indications can be immediately converted into a reset action for the millimeter-wave radar chip through this single path. This hardware-level, parallel monitoring and centralized response mechanism based on logic gate circuits, and the system architecture where the power management chip simultaneously powers both the microcontroller and the millimeter-wave radar chip, simultaneously meets the functional safety monitoring requirements of both the microcontroller and the millimeter-wave radar chip without requiring additional dedicated monitoring chips. This ensures system safety while reducing power output resource waste.

[0030] Optionally, a pull-down resistor is provided at the node between the output terminal 43 of the logic gate circuit 4 and the reset pin 22.

[0031] In the radar hardware security monitoring device of this application, in order to ensure the stability and reliability of the reset signal during transmission, a pull-down resistor can be set at the electrical node between the output terminal 43 of the logic gate circuit 4 and the reset signal output line connected to the reset pin 22 of the millimeter-wave radar chip 2.

[0032] In some cases, pull-down resistors can provide a stable low-level reference for the hardware reset signal path, ensuring that the reset pin 22 of the millimeter-wave radar chip 2 can be reliably pulled to a defined low level during the initial power-on phase of the system or when the output terminal 43 of logic gate 4 is in a high-impedance state. This effectively prevents electromagnetic interference introduced due to the floating signal line, avoids the generation of unexpected high-level pulses that cause the MMIC to be falsely reset, enhances the anti-interference capability and static stability of the reset circuit, and is an important hardware measure to ensure reliable system startup and operation.

[0033] Continue reading Figure 3 Optionally, the device further includes a DC-DC converter module, the output terminal of which is electrically connected to the power input terminal of the power management chip 3, for providing pre-power conversion for the power management chip 3.

[0034] The radar hardware security monitoring device also includes an input-level power architecture. Specifically, the device integrates a DC-DC converter module, whose output is directly connected to the power input of the power management chip 3. In some cases, the core function of the DC-DC converter module is to perform pre-power conversion, typically converting the high or unstable input voltage provided by the vehicle battery into a stable and clean intermediate voltage suitable for processing by the subsequent power management chip 3. This provides a high-quality power source for the entire monitoring device, ensuring that the power management chip 3 can generate the precise, low-noise operating power required by the subsequent microcontroller 1 and millimeter-wave radar chip 2, thereby improving the stability and reliability of the system power supply from the source.

[0035] Optionally, a filter capacitor is provided between the power input terminal of the logic gate circuit 4 and ground to filter the output reset signal.

[0036] A filter capacitor is placed between the power input terminal and ground of logic gate 4. This filter capacitor, also known as a decoupling capacitor or bypass capacitor, plays a crucial role in some cases. Its core function is not to directly filter the output reset signal, but rather to indirectly ensure the integrity of the reset signal by providing a stable operating voltage to the logic gate. Specifically, the filter capacitor can quickly absorb high-frequency noise and voltage ripple on the power line, suppress power fluctuations caused by sudden current changes, and create a locally quiet power supply environment for logic gate 4. A stable power supply ensures the reliable operation and steep switching characteristics of logic gate 4, resulting in a cleaner, glitched output reset signal. This reduces the possibility of logic misjudgments or jitter caused by power supply noise, improving the overall anti-interference capability and reliability of the reset circuit.

[0037] Optionally, the power management chip is 3 in total, which integrates multiple power rails. The power rails are uniformly configured to simultaneously provide the required operating power to the microcontroller 1 and the millimeter-wave radar chip 2.

[0038] In this embodiment, the power management chip 3 adopts a single-chip solution and integrates multiple power rails. In some examples, these power rails are not independently and separately configured, but are uniformly configured and systematically planned to simultaneously provide the two core microcontrollers 1 and the millimeter-wave radar chip 2 with their respective required operating power at different voltage and power levels. This highly integrated power supply solution replaces the traditional redundant architecture that requires two PMICs to power the MCU and MMIC respectively, thereby maximizing the power output capability of a single PMIC, effectively avoiding the waste of power rail resources, and significantly reducing system complexity, circuit board area, and overall material cost.

[0039] Optionally, a pull-up resistor is provided between the fault signal output pin 21 of the millimeter-wave radar chip 2 and the power rail powered by the power management chip 3. The fault signal output pin 21 of the millimeter-wave radar chip is an open-drain output structure or an open-collector output structure, and is connected to the power rail through the pull-up resistor.

[0040] In some examples, the fault signal output pin 21 of the millimeter-wave radar chip 2 is designed as an open-drain or open-collector output structure. To achieve effective signal output, the fault signal output pin 21 is connected to the power rail provided by the power management chip 3 through a pull-up resistor. Specifically, when the millimeter-wave radar chip 2 is operating normally, its fault signal output pin 21 is in a high-impedance state, and the pull-up resistor pulls the signal level up to the power rail voltage, representing a fault-free state. Once the chip detects an internal fault, the internal switching transistor will actively ground the fault signal output pin 21, thereby reliably pulling the signal level down and providing a clear fault indication signal to the microcontroller 1. This design not only provides a clear fault communication interface but also enhances the circuit's anti-interference capability and level compatibility.

[0041] Optionally, the millimeter-wave radar chip 2 is connected to the microcontroller 1 via a serial peripheral interface.

[0042] When establishing a data communication link between two core digital chips in a radar hardware security monitoring device, the millimeter-wave radar chip 2 and the microcontroller 1 can establish a communication connection through a serial peripheral interface (SPI). The serial peripheral interface is a high-speed, full-duplex, synchronous serial communication bus, which typically includes master output / slave input, master input / slave output, serial clock, and chip select signal lines. Through the serial peripheral interface, the microcontroller 1, as the master device, can perform initial configuration and transmit / receive control of the millimeter-wave radar chip 2, and periodically read its pre-processed raw radar data, such as the distance, speed, and angle information of the intermediate frequency signal.

[0043] The aforementioned communication connection is the core data path for realizing radar perception function, ensuring real-time information interaction between front-end sensing and back-end processing, thereby supporting the normal operation of advanced driver assistance functions such as automatic emergency braking.

[0044] Optionally, the millimeter-wave radar chip 2 is a monolithic integrated structure, including a millimeter-wave transmitter, a millimeter-wave receiver, a local oscillator signal generation circuit, and an antenna array unit 25 for radiating and receiving electromagnetic waves. The millimeter-wave transmitter includes one or more transmission channels, and the millimeter-wave receiver includes one or more reception channels. The transmission channels are connected to the transmitting antenna array unit, and the reception channels are connected to the receiving antenna array unit. The local oscillator signal generated by the local oscillator signal generation circuit is connected to the transmission channel and the reception channel respectively through a power distribution network.

[0045] In this embodiment, the millimeter-wave radar chip 2 features an integrated internal architecture, integrating a complete radar RF front-end functional module onto a single chip. Specifically, the millimeter-wave radar chip 2 integrates a millimeter-wave transmitter, a millimeter-wave receiver, a local oscillator signal generation circuit, and an antenna array unit. The millimeter-wave transmitter contains one or more transmission channels, each independently connected to the transmitting antenna array unit. Similarly, the millimeter-wave receiver contains one or more receiving channels, each independently connected to the receiving antenna array unit. The local oscillator signal generation circuit, serving as the RF signal source, generates a high-frequency reference signal that is synchronously fed to all transmission and receiving channels through an on-chip power distribution network. This provides a coherent frequency reference for transmission up-conversion and reception down-conversion, thereby ensuring the accuracy and consistency of the radar system's ranging, velocity, and angle measurement.

[0046] Optionally, the power management chip 3 is further provided with a power status indicator pin, which is electrically connected to the second input terminal 42 of the logic gate circuit 4, and is used to output a signal indicating a power failure of the power management chip 3 to the logic gate circuit 4.

[0047] In some examples, in addition to its basic power supply function, the power management chip 3 also has a dedicated power status indicator pin. This pin is configured as an open-drain or push-pull output fault flag signal and is directly electrically connected to the second input terminal 42 of the logic gate circuit 4. Specifically, when the monitoring circuit inside the power management chip 3 detects a critical fault such as overvoltage, undervoltage, or overtemperature on its own output power rail, it immediately outputs a valid low-level or high-level signal through this power status indicator pin 34. This valid signal is directly transmitted to the logic gate circuit 4 via a hardware link, thereby triggering a reset operation on the millimeter-wave radar chip 2. This achieves a fast, microcontroller-independent hardware-level safety response to faults in the power management chip itself.

[0048] One embodiment of this application also provides a vehicle that can reduce the waste of power output resources.

[0049] The vehicle includes: a body; a forward-facing radar system disposed at the front of the body for detecting target information in front of the vehicle; and a vehicle control unit; wherein the forward-facing radar system includes a radar hardware security monitoring device as described in any of the preceding embodiments; the vehicle control unit is communicatively connected to a microcontroller in the radar hardware security monitoring device for receiving target information processed by the microcontroller and executing the vehicle's automatic emergency braking control function according to the processed target information.

[0050] In one specific embodiment Figure 3 This is a schematic diagram of a single PMIC forward radar hardware security monitoring framework, as shown below. Figure 3 The system framework of the security monitoring device mainly consists of a DC-DC converter, PMIC1, MCU, MMIC and a logic gate circuit.

[0051] Specifically, the output of the DC-DC converter provides input power to PMIC1, which in turn supplies power to both the MCU and MMIC through its multiple power outputs, Vout. In the safety monitoring path, the MMIC's fault indication output pin 2 (nERROUT2) is connected to the MCU's general purpose input / output (GPIO) pins, enabling the MCU to monitor the MMIC's status. Simultaneously, the PMIC1's voltage monitoring or general purpose input / output pins (VMON / GPIO) and the MCU's reset control output pin 2 (N RESET2) are connected to the input of a logic gate circuit, whose output is then connected to the MMIC's reset pin 2 (RESET2), forming a parallel hardware reset channel. Furthermore, the MCU and MMIC communicate via a Serial Peripheral Interface (SPI), and the MCU also interacts with the vehicle system via the Controller Area Network (CAN).

[0052] To ensure the stability and reliability of critical signals, the system framework of the safety monitoring device also includes necessary passive components. For example, a pull-up resistor R0 is usually set on the second input terminal of the logic gate circuit, that is, on the line connected to the voltage monitoring or general-purpose input / output pin VMON / GPIO of PMIC1. This ensures that when the pin of PMIC1 is in a high-impedance state, the input of the logic gate circuit can be stabilized at a certain high level, preventing the MMIC from being falsely reset due to a floating signal. On the open-drain output pins of the MMIC, such as the fault indication output pin nERR OUT2, a pull-up resistor R1 is usually connected to the power supply rail to ensure that a clear high level is output. A capacitor C0 is provided between the output terminal of the logic gate circuit and ground to filter the reset signal and ensure that the reset pulse meets the timing requirements of the MMIC.

[0053] The safety monitoring device achieves stable and reliable dual monitoring and reset functions for the MMIC through a single PMIC and innovative logic circuit design, supplemented by necessary RC components. While meeting functional safety requirements, it significantly simplifies the system structure and reduces costs.

[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0055] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0056] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A radar hardware security monitoring device, characterized in that, include: Microcontrollers, millimeter-wave radar chips, power management chips, and logic gate circuits; The power management chip includes a power output terminal, a general-purpose input / output pin, and a reset control output pin. The power management chip is connected to the corresponding power input terminals of the microcontroller and the millimeter-wave radar chip through the power output terminal, respectively, to provide the required operating power to the microcontroller and the millimeter-wave radar chip. The millimeter-wave radar chip has a fault signal output pin and a reset pin, and the fault signal output pin is electrically connected to the general-purpose input / output pin of the microcontroller. The power management chip has a power fault reset signal pin, and the logic gate circuit has a first input terminal and a second input terminal. The first input terminal of the logic gate circuit is electrically connected to the reset control output pin, the second input terminal is electrically connected to the power failure reset signal pin, and the output terminal of the logic gate circuit is electrically connected to the reset pin of the millimeter-wave radar chip.

2. The radar hardware security monitoring device according to claim 1, characterized in that, A pull-down resistor is provided at the node between the output terminal of the logic gate circuit and the reset pin.

3. The radar hardware security monitoring device according to claim 1, characterized in that, The device further includes a DC-DC conversion module, the output terminal of which is electrically connected to the power input terminal of the power management chip, for providing pre-power conversion for the power management chip.

4. The radar hardware security monitoring device according to claim 1, characterized in that, A filter capacitor is provided between the power input terminal and ground of the logic gate circuit to filter the output reset signal.

5. The radar hardware security monitoring device according to claim 1, characterized in that, The power management chip is a single chip that integrates multiple power rails. These power rails are uniformly configured to simultaneously provide the necessary operating power to both the microcontroller and the millimeter-wave radar chip.

6. The radar hardware security monitoring device according to claim 1, characterized in that, A pull-up resistor is provided between the fault signal output pin of the millimeter-wave radar chip and the power rail supplied by the power management chip. The fault signal output pin of the millimeter-wave radar chip is an open-drain output structure or an open-collector output structure, and is connected to the power rail through the pull-up resistor.

7. The radar hardware security monitoring device according to claim 1, characterized in that, The millimeter-wave radar chip is connected to the microcontroller via a serial peripheral interface.

8. The radar hardware security monitoring device according to claim 1, characterized in that, The millimeter-wave radar chip is a monolithic integrated structure, including a millimeter-wave transmitter, a millimeter-wave receiver, a local oscillator signal generation circuit, and an antenna array unit for radiating and receiving electromagnetic waves. The millimeter-wave transmitter includes one or more transmission channels, and the millimeter-wave receiver includes one or more reception channels. The transmission channels are connected to the transmission antenna array unit, and the reception channels are connected to the reception antenna array unit. The local oscillator signal generated by the local oscillator signal generation circuit is connected to the transmission channel and the reception channel respectively through a power distribution network.

9. The radar hardware security monitoring device according to claim 1, characterized in that, The power management chip also has a power status indicator pin, which is electrically connected to the second input terminal of the logic gate circuit and is used to output a signal indicating a power failure of the power management chip itself to the logic gate circuit.

10. A vehicle, characterized in that, include: Body; A forward-facing radar system is installed at the front of the vehicle body to detect target information in front of the vehicle; And, the vehicle control unit; The forward-facing radar system includes the radar hardware security monitoring device according to any one of claims 1 to 9; The vehicle control unit is communicatively connected to the microcontroller in the radar hardware safety monitoring device, and is used to receive target information processed by the microcontroller and execute the vehicle's automatic emergency braking control function according to the processed target information.

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