A DFN package chip pre-burning test carrier based on a TO package pre-burning test board

Abstract

The application relates to a DFN package chip pre-burning test carrier based on a TO package pre-burning test board, which comprises a carrier body and three pins arranged on the lower surface of the carrier body; a bearing area for accommodating a DFN package chip to be tested is arranged on the carrier body; pads are arranged on the carrier body, each pad is connected with a corresponding pin, and in a use state, each pad is connected with a bonding pad on the DFN package chip to be tested in a corresponding mode; the layout of the three pins corresponds to the insertion hole of a test fixture on a standard TO package pre-burning test board. The application has the effects of reducing the test cost of the DFN package chip and improving the utilization rate of the existing TO package pre-burning test equipment.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor packaging and testing, and in particular to a DFN packaged chip pre-burn-in test carrier based on a TO package pre-burn-in test board. Background Technology

[0002] With the development of technology and the increasing demands of industrial applications, semiconductor manufacturers conduct pre-burn-in testing on chips after manufacturing. Pre-burn-in testing involves running the chips under harsh environments such as high temperature and high pressure to accelerate the exposure of potential defects, thereby screening out chips that fail early and improving the reliability of chips leaving the factory. During pre-burn-in testing, the chips are mounted in a dedicated test fixture on a pre-burn-in test board, which uses internal PCB wiring to achieve power supply and signal transmission.

[0003] Existing burn-in test boards are typically designed for specific package types of chips. For example, a burn-in test board designed specifically for TO packages is incompatible with DFN packaged chips because DFN packaged chips have no exposed pins and the pads are located on the bottom, which is significantly different from the structure of TO packages. Therefore, a burn-in test board designed specifically for TO packages cannot be directly used for testing DFN packaged chips.

[0004] Currently, many manufacturers focused on transistor production mainly possess testing equipment for TO packaged chips. When pre-burn-in testing of DFN packaged chips is required, the entire pre-burn-in test board and test fixture need to be replaced simultaneously. This leads to increased testing costs, reduced utilization of existing equipment, and impacts chip production efficiency. Utility Model Content

[0005] In order to reduce the testing cost of DFN packaged chips and improve the utilization rate of existing TO packaged pre-burn-in test equipment, this application provides a DFN packaged chip pre-burn-in test carrier based on a TO packaged pre-burn-in test board.

[0006] A DFN packaged chip pre-burn-in test carrier based on a TO package pre-burn-in test board includes a carrier body and three pins disposed on the lower surface of the carrier body; the carrier body has a carrier area for accommodating the DFN packaged chip to be tested; the carrier body has solder pads, each solder pad being electrically connected to the corresponding pin, and in the assembled state, each solder pad being electrically connected to the corresponding pad on the DFN packaged chip to be tested; the layout of the three pins corresponds to the insertion holes of the test fixture on a standard TO package pre-burn-in test board.

[0007] By adopting the above technical solution, the carrier can adapt DFN packaged chips to standard TO packaged pre-burn-in test boards, utilizing existing TO test infrastructure, reducing testing costs and improving compatibility.

[0008] Preferably, the bearing area is a groove structure that extends through the upper and lower surfaces of the carrier body, and the dimensions of the groove structure are adapted to the DFN packaged chip to be tested.

[0009] By adopting the above technical solution, the through-groove structure facilitates chip placement and positioning, and also helps with heat dissipation during testing, ensuring the stability of the testing environment.

[0010] Preferably, the carrier body is a semi-cylindrical structure, including a rectangular plane and an arc-shaped curved surface; the bearing area is located on one side of the rectangular plane.

[0011] By adopting the above technical solution, the semi-cylindrical structure design facilitates installation and fixation on the test board, the rectangular plane provides stable support for the chip, and the curved surface makes it easy for the operator to hold and position it.

[0012] Preferably, the carrier body has a wire embedded inside, and the solder pad is connected to the corresponding pin through the wire.

[0013] By adopting the above technical solution, the internally embedded wires ensure the stability and reliability of electrical signal transmission, reduce external interference, and make the carrier structure more compact and durable.

[0014] Preferably, the number of solder pads is six, and three solder pads are provided on each side of the bearing area.

[0015] By adopting the above technical solution, the symmetrical layout of the six pads can be adapted to the pin definitions of various DFN packaged chips, providing good versatility and contact reliability.

[0016] Preferably, the solder pad is made of copper or gold-plated copper.

[0017] By adopting the above technical solution, copper or gold-plated copper materials have good conductivity and oxidation resistance, ensuring the stability and low resistance of electrical connections during the test.

[0018] Preferably, of the six pads, three pads are a G-pole pad, a S-pole pad, and a D-pole pad, and the three pins are a G-pole pin, a S-pole pin, and a D-pole pin, respectively. The G-pole pad, S-pole pad, and D-pole pad are respectively connected to the G-pole pin, the S-pole pin, and the D-pole pin.

[0019] By adopting the above technical solution, the clear polarity definition and direct connection method simplify the circuit structure and ensure the integrity of the critical signal path of the power device during the pre-burn-in test.

[0020] Preferably, the center points of the three pins are connected to form a triangular distribution structure; and the spacing, extension length, and diameter of the three pins are consistent with the socket specifications of the test fixture on the TO package pre-burn-in test board.

[0021] By adopting the above technical solution, the pin layout is fully compatible with the TO test fixture socket, making this carrier plug-and-play, without requiring any modification to existing test equipment.

[0022] Preferably, the carrier body is made of alumina ceramic.

[0023] By adopting the above technical solutions, alumina ceramics have excellent heat resistance, insulation and mechanical strength, and can withstand the high temperature environment of pre-firing test, ensuring the reliability of the carrier for long-term use.

[0024] In summary, this application includes at least one of the following beneficial technical effects: 1. Compatibility testing of DFN packaged chips on a standard TO pre-burn-in test board was achieved, significantly reducing testing costs and complexity; 2. Through optimized structural and material design, the stability and reliability of electrical connections and thermal management during testing were ensured; 3. The user-friendly structural design and labeling improve ease of operation and prevent misoperation, thereby enhancing testing efficiency and safety. Attached Figure Description

[0025] Figure 1 This is a three-dimensional structural diagram of the carrier according to an embodiment of this application; Figure 2 This is a schematic diagram of the carrier of this application being applied to a TO package pre-burn-in test board during pre-burn-in testing; Figure 3 This is a bottom view of the carrier in the embodiment of this application; Figure 4 This is a schematic diagram of the carrier assembling the DFN chip to be tested in an embodiment of this application.

[0026] Reference numerals: 1. Carrier body; 11. Rectangular plane; 12. Arc-shaped surface; 13. Bearing area; 111. G-pole pad; 112. S-pole pad; 113. D-pole pad; 2. Pin; 21. G-pole pin; 22. S-pole pin; 23. D-pole pin; 3. DFN packaged chip under test; 31. G-pole pad; 32. S-pole pad; 33. D-pole pad; 4. TO package pre-burn-in test board; 41. Test fixture. Detailed Implementation

[0027] The following is in conjunction with the appendix Figure 1 -Appendix Figure 4 This application will be described in further detail.

[0028] This application discloses a DFN-packaged chip pre-burn-in test carrier based on a TO-packaged pre-burn-in test board. (Refer to...) Figure 1 In this embodiment, the carrier is designed to resemble the shape of a TO packaged chip. It includes a carrier body 1 and three pins 2 disposed on the lower surface of the carrier body 1. The carrier body 1 is provided with a carrier area 13 for accommodating the DFN packaged chip 3 to be tested. The carrier body 1 is symmetrically provided with solder pads on both sides of the carrier area 13. Each solder pad is connected to the corresponding pin 2 through a circuit pre-embedded inside the carrier body 1.

[0029] During the pre-burn-in test, the DFN packaged chip 3 to be tested is attached and fixed in the carrier area 13. The electrode pads of the DFN packaged chip 3 to be tested are connected to the pads on the carrier body 1 to form a circuit connection. The outer dimensions and pin layout of the carrier match the test fixture 41 on the standard TO package pre-burn-in test board 4. The carrier is directly inserted into and contacts the test fixture 41 through three pins 2, realizing the mechanical connection between the DFN packaged chip 3 to be tested and the TO package pre-burn-in test board 4. At the same time, through the electrode pads, pads, the circuit embedded inside the carrier, and the transmission path of the pins 2, the circuit connection between the DFN packaged chip 3 to be tested and the TO package pre-burn-in test board 4 is realized, so as to realize the function of pre-burn-in testing of DFN packaged chips using the TO package pre-burn-in test board 4.

[0030] Reference Figure 2 and Figure 3 In this embodiment, the support area 13 is a groove structure, and the carrier body 1 is a semi-cylindrical structure, including a rectangular plane 11 and an arc-shaped curved surface 12. The support area 13 is located on one side of the rectangular plane 11 and extends through the upper and lower surfaces of the carrier body 1. The size of the support area 13 is adapted to the DFN packaged chip 3 to be tested, and is used to accommodate and fix the DFN chip 3 to be tested. The solder pads are symmetrically arranged on the rectangular plane 11 on both sides of the support area 13. The solder pads are made of a conductive metal material, such as copper or gold-plated copper, to ensure good circuit connection performance.

[0031] In other embodiments, the cross-sectional structure of the carrier body 1 can take the form of a complete semi-circle or a complete square, and the corresponding carrier area 13 of the DFN packaged chip 3 to be tested can be a groove structure or a planar structure.

[0032] In this embodiment, there are six solder pads, with three on each side of the carrier area 13. The solder pad closest to the upper surface of the carrier body on one side is designated as the G-pole solder pad 111, the solder pad closest to the pin on the same side is designated as the S-pole solder pad 112, and the solder pad closest to the pin on the other side of the carrier area 13 is designated as the D-pole solder pad 113. The other three solder pads are not connected by circuitry. The G-pole solder pad 111, S-pole solder pad 112, and D-pole solder pad 113 are connected to the corresponding pins 2 on the lower surface of the carrier body 1 via wires pre-embedded inside the carrier body 1, thus achieving complete signal transmission.

[0033] In this embodiment, the pin layout of the carrier corresponds to the socket of the test fixture 41 on the standard TO package pre-burn-in test board 4, and the center points of the three pins 2 form a stable triangular distribution structure. The three pins 2 are respectively designated as G pin 21, S pin 22, and D pin 23, and are respectively connected to the G pad 111, S pad 112, and D pad 113 on the carrier body 1. The pin spacing, extension length, and diameter are consistent with the pins of the standard TO package chip, thereby ensuring that the carrier and the test fixture 41 can achieve smooth insertion operation and maintain a stable circuit connection, meeting the compatibility requirements of pre-burn-in testing.

[0034] In other embodiments, the arrangement of the three pins 2 can be adjusted according to the test fixture 41 on the TO package pre-burn-in test board actually used, for example, the pins can be arranged in a straight line.

[0035] In this embodiment, the carrier body 1 is made of alumina ceramic, which is resistant to high temperature, has good insulation and strong thermal stability, and can be adapted to the high temperature environment of pre-burning test and avoid circuit interference; the three pins 2 are made of the same material as the solder pad, copper or gold-plated copper, which has excellent conductivity and sufficient hardness, making it easy for the pins 2 to be inserted into the socket of the test fixture to achieve circuit connection.

[0036] Reference Figure 4In this embodiment, the DFN packaged chip 3 is fixedly attached to the groove. The six electrode pads of the DFN packaged chip 3 are symmetrically distributed on both sides of the chip surface. These six electrode pads include at least a G-pad 31, a S-pad 32, and a D-pad 33. The circuit connection between the DFN packaged chip 3 under test and the carrier is achieved through wire bonding: using metal wires, the G-pad 31, S-pad 32, and D-pad 33 of the DFN packaged chip 3 under test are interconnected with the G-pad 111, S-pad 112, and D-pad 113 on the carrier body 1, respectively. After wire bonding, high-temperature silicone is applied to the connection points between the pads, electrode pads, and metal wires for protection. The metal wires can be gold or aluminum wires. After assembly, the circuit signals of the DFN packaged chip 3 under test are transmitted to the pins through the pads and internally embedded wires. In other embodiments, if the chip accommodating area of ​​the carrier is a planar structure, the DFN packaged chip 3 to be tested can also be mounted on the carrier by SMT (Surface Mounted Technology).

[0037] The implementation principle of this application embodiment is as follows: By setting grooves and conductive pads that match the structure of the DFN packaged chip, the characteristics of the DFN packaged chip—no leads and pads on the bottom—are effectively adapted. Simultaneously, by adopting a TO-package-like shape design and pin arrangement, it is compatible with the test fixtures on existing TO package pre-burn-in test boards. Furthermore, wires are pre-embedded inside the carrier, ensuring that the pads of the DFN packaged chip to be tested correspond to the pads and leads of the carrier. Therefore, without modifying the original TO package pre-burn-in test board, mechanical adaptation and circuit connection between the DFN packaged chip and the TO package pre-burn-in test board are achieved, thus successfully completing the pre-burn-in test and improving the versatility and efficiency of the TO package pre-burn-in test equipment.

[0038] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A DFN-packaged chip pre-burn-in test carrier based on a TO-packaged pre-burn-in test board, characterized in that, It includes a carrier body (1) and three pins (2) disposed on the lower surface of the carrier body (1); The carrier body (1) is provided with a carrier area (13) for accommodating the DFN packaged chip (3) to be tested. The carrier body (1) is provided with solder pads, each solder pad is electrically connected to the corresponding pin (2), and in the assembled state, each solder pad is electrically connected to the corresponding pad on the DFN packaged chip (3) to be tested; The layout of the three pins (2) corresponds to the sockets of the test fixture (41) on the standard TO package burn-in test board (4).

2. The DFN packaged chip pre-burn-in test carrier based on the TO package pre-burn-in test board according to claim 1, characterized in that, The bearing area (13) is a groove structure that penetrates the upper and lower surfaces of the carrier body (1), and the size of the groove structure is adapted to the DFN packaged chip (3) to be tested.

3. The DFN packaged chip pre-burn-in test carrier based on the TO package pre-burn-in test board according to claim 1, characterized in that, The carrier body (1) is a semi-cylindrical structure, including a rectangular plane (11) and an arc-shaped curved surface (12); the bearing area (13) is located on one side of the rectangular plane (11).

4. The DFN packaged chip pre-burn-in test carrier based on the TO package pre-burn-in test board according to claim 1, characterized in that, The carrier body (1) has a wire embedded inside, and the solder pad is connected to the corresponding pin (2) through the wire.

5. The DFN packaged chip pre-burn-in test carrier based on the TO package pre-burn-in test board according to claim 1, characterized in that, The number of solder pads is six, and three solder pads are provided on each side of the bearing area (13).

6. The DFN packaged chip pre-burn-in test carrier based on the TO package pre-burn-in test board according to claim 5, characterized in that, The solder pads are made of copper or gold-plated copper.

7. The DFN-packaged chip pre-burn-in test carrier based on a TO-packaged pre-burn-in test board according to claim 5, characterized in that, Of the six pads, three pads are G pad (111), S pad (112), and D pad (113), and three pins are G pin (21), S pin (22), and D pin (23), respectively. The G pad (111), S pad (112), and D pad (113) are connected to the G pin (21), S pin (22), and D pin (23), respectively.

8. The DFN packaged chip pre-burn-in test carrier based on the TO package pre-burn-in test board according to claim 1, characterized in that, The center points of the three pins (2) are connected to form a triangular distribution structure; and the spacing, extension length and diameter of the three pins (2) are consistent with the socket specifications of the test fixture (41) on the TO package pre-burn-in test board (4).

9. The DFN packaged chip pre-burn-in test carrier based on the TO package pre-burn-in test board according to claim 1, characterized in that, The carrier body (1) is made of alumina ceramic.

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