A substrate, a socket test system, and a probe card test system

Abstract

This application provides a substrate, a pin header testing system, and a probe card testing system. The substrate includes: at least one first signal port located on the surface of the substrate for connecting test signals; at least one second signal port located on the surface of the substrate for connecting probes; at least one current control module located between the first and second signal ports, the current control module including a first line and a second line, a switching module, the first ends of the first and second lines being connected in parallel to form a main line connected to the second signal port, and the second end of the first line being connected to the first signal port; and at least one driver, one end of which is connected to the first line and monitors the voltage of the first line, and the other end of which is connected to the switching module. In operation, the driver outputs a control signal to the switching module, and the switching module receives the control signal output by the driver to switch the connection between the first line / second line and the second signal port.

Description

Technical Field

[0001] This application relates to the semiconductor field, more specifically to the wafer testing field, and particularly to a substrate, a pin header testing system, and a probe card testing system. Background Technology

[0002] In recent years, semiconductor reliability has received increasing attention. Semiconductor process reliability testing simulates extreme conditions (high temperature, high pressure, etc.) to identify potential defects in the process (such as electromigration and gate oxide degradation) in advance, optimize the design to extend lifespan, and ensure stable operation of devices during long-term use. Structurally, semiconductor process reliability can be broadly categorized into dielectric layer process reliability, device process reliability, and metal reliability. Dielectric layer reliability testing commonly uses probe station equipment to perform voltage ramp tests (Vramp) and time-dependent dielectric breakdown (TDDB).

[0003] like Figure 1 As shown, Figure 1 This is a schematic diagram illustrating the application of pressure to the dielectric layer under test during a ramp voltage test. Please refer to [link / reference]. Figure 1 Vramp refers to the voltage applied to the gate in steps from the device's operating voltage Vuse until the dielectric layer breakdown is detected, at which point the voltage Vbd is reached. TDDB refers to applying a certain voltage (typically 80% Vbd) and stress to the dielectric layer, monitoring leakage current, and recording the total time (TTF) from the applied voltage to the dielectric layer breakdown. Based on the corresponding failure model, the lifetime of the dielectric layer under normal operating conditions is calculated.

[0004] For thicker dielectric layers, higher test voltages are used. For dielectric layers with low dielectric constant (low k), their characteristics result in a very high breakdown voltage (Vbd) during testing. This means that for thicker and low k dielectric layers, in the later stages of Vramp and TDDB testing, due to the high breakdown voltage (Vbd) and / or prolonged aging under high Vbd conditions, a large leakage current will form in the circuit at the moment the dielectric layer breaks down. This large current can easily cause safety hazards. For example, melting the back-end metal (back-end metal refers to the metal wiring layers and related metal structures used for device interconnection in the back-end process, often abbreviated as BEOL) can affect electrical testing (such as...) Figure 2 As shown, Figure 2This is a schematic diagram of the abnormal voltage-current detected when the dielectric layer under test suddenly breaks down under pressure during a ramp voltage test. It can even damage the test structure (a small circuit structure added between chips on a wafer, commonly referred to in the industry as "scribing"), affecting subsequent failure analysis. More seriously, the large current may directly cause the metal pads on the test structure to explode, and may also burn out the probes and / or probe cards in the test probe station equipment, severely impacting the progress of dielectric layer reliability testing. Utility Model Content

[0005] The purpose of this application is to provide a substrate, a pin header testing system, and a probe card testing system that can help wafer testing personnel control the current in the circuit during the testing process of Vramp testing and / or TDDB testing, so as to avoid unnecessary losses and / or safety accidents caused by large currents when the dielectric layer is broken down.

[0006] A first aspect of this application provides a substrate for semiconductor reliability testing. The substrate includes: At least one first signal port is located on the surface of the substrate for connecting a test signal; At least one second signal port is located on the surface of the substrate for connecting a probe; At least one current control module is located between the first signal port and the second signal port. The current control module includes a first line, a second line, and a switch module. The first ends of the first line and the second line are connected in parallel to form a main line and connected to the second signal port. The second end of the first line is connected to the first signal port. At least one driver is provided, one end of which is connected to the first line and monitors the voltage of the first line, and the other end of which is connected to the switch module. In operation, the driver outputs a control signal to the switch module, and the switch module receives the control signal output by the driver to switch the connection between the first line / second line and the second signal port.

[0007] A second aspect of this application provides a pin header testing system, comprising: At least one source table; A needle holder, wherein at least one probe port is provided on the needle holder and a probe is installed in the probe port; As described in the first aspect embodiment, the substrate has a first signal port connected to the source meter, the source meter transmitting test signals to the first signal port, and the probe card substrate has a second signal port connected to the probe port.

[0008] A third aspect of this application provides a probe card testing system, the testing system comprising: The substrate as described in the first aspect embodiment A plurality of first signal ports are arranged around the periphery of the substrate, and the first signal ports are used to connect to the test signals of the probe card machine. Several second signal ports are spaced apart at the center of the surface of the substrate, and the second signal ports are connected to the probe as probe ports. Several current control modules are connected one-to-one with the second signal port and are arranged around the second signal port; Several drivers are provided, and the switching modules in the current control module are connected to the drivers one by one. All the drivers are connected to an external power supply.

[0009] In this embodiment, when testing a wafer using the testing system provided in this application, probes can be installed on the probe ports of the probe holder or probe card. The probes then contact preset contacts on the wafer. The current applied to the wafer by the source meter through the probes can be controlled via line selection in the current control module. For example, the source meter is electrically connected to the probes through the current control module. In the initial stage of the Vramp test, the first line in the current control module is turned on by the switching module, while the second line (with a resistance value greater than that of the first line) is turned off. In the later stage of the Vramp test, the first line in the current control module is turned on by the switching module, while the second line is turned on. This allows for control of the current in the test circuit at different test stages, preventing unnecessary losses or safety hazards caused by large currents in the test circuit during the later stages of testing. Therefore, the testing system provided in this application can help wafer testing personnel control the current in the circuit during Vramp and / or TDDB tests to prevent unnecessary losses and / or safety accidents caused by large currents when the dielectric layer is broken down. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of applying pressure to the dielectric layer being tested during a ramp voltage test; Figure 2 This is a schematic diagram of the abnormal voltage-current detected when the dielectric layer under test is suddenly broken down under pressure during a ramp voltage test. Figure 3 This is a schematic diagram of the structure of the substrate provided in the embodiments of this application; Figure 4 This is a schematic diagram of a substrate structure; Figure 5 This is a schematic diagram of the circuit structure of a driver in a substrate provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a pin header testing system provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a probe card testing system provided in an embodiment of this application. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0012] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0013] This application provides a substrate for semiconductor reliability testing. Figure 3 As shown, Figure 3 This is a schematic diagram of the substrate structure provided in an embodiment of this application. Please refer to... Figure 3 The system includes at least one first signal port 54, located on the surface of the substrate, for connecting test signals; at least one second signal port 55, located on the surface of the substrate, for connecting probes; at least one current control module 5, located between the first signal port 54 and the second signal port 55, the current control module 5 including a first line and a second line, a switch module, the first ends of the first line and the second line being connected in parallel to form a total line connected to the first signal port 54, the second end of the first line being connected to the second signal port 55; and at least one driver 7, one end of the driver 7 being connected to the first line and monitoring the voltage of the first line, the other end of the driver being connected to the switch module, and in the working state, outputting a control signal to the switch module, the switch module receiving the control signal output by the driver 7 and switching the connection between the first line / second line and the second signal port.

[0014] like Figure 4 As shown, Figure 4 This is a schematic diagram of a substrate structure. The current control module 5 includes a first line 52, a second line 53, and a switching module (in...). Figure 4The Chinese side did not explicitly indicate that, Figure 4 The diagram illustrates the control terminal 564, the first contact 561, the second contact 562, and the third contact 563 of the switch module. The first ends of the first line 52 and the second line 53 are connected in parallel to form a main line and connected to the first signal port 54. The second end of the first line 52 is connected to the second signal port 55.

[0015] Please refer to the above. Figure 3 and Figure 4 The substrate 51 is also provided with at least one driver 7. One end of the driver 7 is connected to the first line 52 and monitors the voltage of the first line 52. The other end of the driver 7 is connected to the switch module. In the working state, the driver 7 outputs a control signal to the switch module. The switch module receives the control signal output by the driver 7 and switches the connection with the first line 52 / first signal port 54 according to the received control signal.

[0016] In one specific embodiment, the resistance value on the second line 53 is greater than the resistance value on the first line 52.

[0017] In one specific embodiment, a resistor 57 (i.e., resistor R) is also connected in series with the second line 53. Resistor 57 serves as a current limiter in the second line 53; that is, resistor 57 is a current-limiting resistor. In some alternative embodiments, the current-limiting resistor 57 is an adjustable resistor.

[0018] In some alternative embodiments, the switch module includes a controller (not shown), a first contact 561 of the controller is disposed at the second end of the first line 52, a second contact 562 of the controller is disposed at the second end of the second line 53, a third contact 563 of the controller is electrically connected to the second signal port 55, and a control terminal 564 of the controller is used to receive a control signal output by the driver 7 to drive the third contact 563 to close with one of the first contact 561 and the second contact 562.

[0019] Optionally, the controller is a relay, wherein the first contact of the relay is the first contact 561 of the controller, the second contact of the relay is the second contact 562 of the controller, the third contact of the relay is the third contact 563 of the controller, and the control terminal of the relay is the control terminal 564 of the controller.

[0020] Optionally, under normal conditions, the third contact 563 of the relay is closed with the first contact 561, and the third contact 563 is disconnected from the second contact 562. However, when the relay is driven by the control signal output by the driver 7 (i.e., the drive voltage that starts the relay from operating), the third contact 563 closes with the second contact 562, and the third contact 563 is disconnected from the first contact 561. In the early stages of the Vramp test and TDDB test (when the breakdown voltage is still low / when a higher breakdown voltage is used for a short time), the closure of the third contact 563 and the first contact 561 of the relay causes the first circuit 52 to conduct. In the later stages of the test (when the breakdown voltage is high / when a higher breakdown voltage is used for a long time), the driver 7 outputs a control signal to the switch module to control the closure of the third contact 563 and the second contact 562. The relay responds to this control signal to control the second circuit 53 to conduct, that is, to control the closure of the third contact 563 and the second contact 562.

[0021] Optionally, under normal conditions, the third contact 563 of the relay is closed with the second contact 562, while the third contact 563 is open with the first contact 561. However, when the relay is driven by the control signal output by the driver 7 (i.e., the drive voltage that starts the relay from operating), the third contact 563 closes with the first contact 561, while the third contact 563 is open with the second contact 562. It should be noted that during the early stages of the Vramp and TDDB tests (when the breakdown voltage is still low / when a higher breakdown voltage is used for a short time), the driver 7 outputs a control signal to the switch module to control the closing of the third contact 563 and the first contact 561. The relay responds to this control signal to control the first circuit 52 to conduct, that is, to control the closing of the third contact 563 and the first contact 561. In the later stages of the test (when the breakdown voltage is high / when a higher breakdown voltage is used for a long time), the driver 7 stops outputting control signals to the switch module, and the third contact 563 and the second contact 562 of the relay naturally close, causing the second circuit 51 to conduct.

[0022] Optionally, the relay is an electromagnetic relay, a photoelectric relay, a thermal relay, or a solid-state relay.

[0023] like Figure 5 As shown, Figure 5 This is a schematic diagram of the circuit structure of a driver in the substrate provided in an embodiment of this application. Please refer to... Figure 5 The driver 7 includes a current monitor, a voltage comparison unit 61, and a switching unit 62. The current monitor monitors the real-time current on the first line 52 and converts the real-time current into a real-time voltage. The voltage comparison unit 61 is electrically connected to the current monitor and is used to compare the real-time voltage. With reference voltage The comparison is performed, and a drive signal is output based on the comparison result. One end of the switching unit 62 is connected to the voltage comparison unit 61, and the other end is connected to the switching module in the current control module 5. The switching unit 62 is used to receive the drive signal and output a control signal to the switching module based on the drive signal.

[0024] Among them, the current monitor can be Figure 5 The Hall sensor H shown is electrically connected to line 52 (see reference). Figure 4 It can collect the real-time current on line 52 and convert the collected real-time current into real-time voltage. .

[0025] Voltage comparison unit 61 includes an amplifier AMP and a comparator. The real-time voltage is input to the non-inverting input of the amplifier AMP. The inverting input of amplifier AMP is grounded through resistor R1, and the signal output of amplifier AMP is connected to the non-inverting input of comparator through resistor R2. The inverting input of comparator is used to input the reference voltage. Reference voltage This is the voltage corresponding to the threshold current, which is the maximum allowable current on the first line 52. In Vramp and TDDB tests, the real-time current in the circuit gradually increases with the voltage; that is, the current in the first line 52 gradually increases. A threshold current can be preset, which is the maximum allowable current on the first line 52. This threshold current corresponds to a preset voltage, i.e., a reference voltage. .

[0026] The Hall sensor H detects a very small actual voltage value, which can be amplified by an amplifier AMP before being input to a comparator for comparison. The comparator then converts the amplified real-time voltage... With reference voltage Compare, if real-time voltage Not greater than the reference voltage The comparator outputs a low-level signal if the real-time voltage... Greater than the reference voltage The comparator outputs a high-level signal.

[0027] Switching unit 62 includes switching devices (e.g. Figure 5 The NMOS transistor N shown can also be any other switching device that can turn on in response to a high-level signal, such as a transistor, freewheeling diode D, and resistors R3 and R4. When the gate (G) of NMOS transistor N receives a low-level signal, NMOS transistor N is turned off, and the control signal... The control terminal 564 of the relay cannot be applied; the relay remains in its normal state, for example, it is... Figure 4 The relay shown in the diagram has its first contact 561 and third contact 563 conducting, thus connecting the first circuit 52; while the second contact 562 and third contact 563 are closed, thus closing the second circuit 53. When the gate of NMOS transistor N receives a high-level signal, NMOS transistor N conducts, and the control signal... When the control terminal 564 of the relay is activated, the relay is no longer in its normal state, for example, it is Figure 4 The relay shown in the diagram has its first contact 561 and third contact 563 cut off, and the first circuit 53 is cut off; while the second contact 562 and third contact 563 are connected, and the second circuit 53 is connected. Using the driver 7 described above, the test circuit can be automatically switched during Vramp and TDDB tests, achieving automated testing.

[0028] Diode D provides a freewheeling path. When MOSFET N is turned off, the current that originally passed through R4 and N needs to be released by the energy storage element (such as the inductor in a relay). Diode D can conduct to form a freewheeling circuit, suppressing the voltage spike at the moment of turn-off and ensuring circuit stability.

[0029] In some alternative embodiments, the substrate 51 further includes an external power supply 6, which is a DC power supply located on the surface of the substrate 51 and connected to the driver 7 to provide power to the driver 7. .

[0030] like Figure 3 As shown, in one specific embodiment, the substrate 51 may include: a plurality of first signal ports 54, a plurality of second signal ports 55, a plurality of current control modules 5, and a plurality of drivers 7, all of which are connected to an external power supply 6. The substrate 51 can be used to simultaneously connect multiple probes and test signals, ensuring normal circuit operation during multiple probe tests and avoiding unnecessary losses caused by large currents.

[0031] This application also provides a pin header testing system. For example... Figure 6 As shown, Figure 6 This is a schematic diagram of a pin header testing system provided in an embodiment of this application. Please refer to... Figure 6The test system 200 includes a source measure unit (SMU) 1, a probe holder 2, a substrate 51, and an external power supply 6. A first signal port 54 of the substrate 51 is connected to the source measure unit 1, and the source measure unit 1 transmits test signals through the first signal port 54. A second signal port 55 of the substrate 51 is connected to the probe port. A probe port 21 is provided on the probe holder 2, and a probe 4 is installed within the probe port 21. A current control module 5 is connected in series between the source measure unit 1 and the probe holder 2. A driver 7 outputs control signals.

[0032] Please refer to the above. Figure 4 and Figure 6 The source meter 1 is electrically connected to the first signal port 54 on the substrate 51 via the first signal line 31. The source meter 1 transmits test signals to the first signal port 54. The second signal port 55 on the substrate 51 is electrically connected to the probe port 21 on the probe holder 2 via the second signal line 32. During Vramp and TDDB tests, the probe 4 makes contact with the contacts on the "scribed" test structure on the wafer, thereby achieving pressure testing on the wafer.

[0033] Among them, Source Meter 1, officially known as the Source Measurement Unit, is an electronic test device that integrates a programmable power supply and high-precision measuring instruments. It can act as a power source, outputting precise voltage or current to the device under test (such as semiconductors, sensors, dielectric materials, etc.), and simultaneously measure the current flowing through the device and the voltage across its terminals, achieving integrated operation of "output" and "measurement." It is a precision "two-in-one" tool in electronic testing, combining "powering the device" and "measuring the device response," and is particularly suitable for scenarios requiring high precision, wide range, and synchronous output and measurement.

[0034] The probe station is a key device in semiconductor device testing used for precise connection between the device under test (DUT) and the testing instruments. Its core function is to establish an electrical signal connection between the DUT (such as a chip, wafer, or device sample) and external testing instruments (such as a source meter or oscilloscope) via probes, ensuring stable transmission of test signals. The probe port is a dedicated interface for mounting probes. The probe port also contains a contact point that abuts against the probe's tail (this contact point is electrically connected to the internal circuitry of the probe station). This means that after the probe is mounted in the probe port, not only is a physical (contact) connection between the probe and the probe station achieved, but also an electrical connection between the probe's tail and the internal circuitry of the probe station.

[0035] As described in the background section, in semiconductor testing, the test points (such as metal pads and wiring endpoints) of the device under test (e.g., chips on a wafer, discrete devices) are typically extremely small (micrometers or even nanometers in size) and require extremely high positional accuracy. Probe station equipment utilizes a precision adjustment mechanism to accurately align the probe tip with these test points, ensuring a stable ohmic contact between the probe and the test point. This allows the voltage / current signal output by the testing instrument to be transmitted to the device under test through the probe, while simultaneously transmitting the device's response signal (such as current or voltage) back to the instrument, thus completing the electrical parameter testing.

[0036] See also Figure 4 and Figure 6 The control terminal 564 of the switch module is electrically connected to the signal output terminal of the driver 7 via a signal line. It can receive control signals output by the driver 7 and control the switching of the first line 52 and the second line 53 according to the received control signals. Optionally, in the early stages of the Vramp and TDDB tests (when the breakdown voltage is still low / when a higher breakdown voltage is used for a short time), the driver 7 outputs a first control signal to the switch module to control the closing of the third contact 563 and the first contact 561. The switch module responds to this first control signal by controlling the first line 52 to conduct, i.e., controlling the closing of the third contact 563 and the first contact 561. In the later stages of the test (when the breakdown voltage is still low / when a higher breakdown voltage is used for a short time), the driver 7 outputs a control signal to the switch module... The second control signal closes the third contact 563 and the second contact 562. The switching module responds to the second control signal to control the second line 53 to conduct, that is, to control the third contact 563 and the second contact 562 to close. Because a current-limiting resistor 57 is connected in series on the second line 53, it can limit the current flowing out of the source meter 1, through the line 53 and the probe 4, and into the wafer under test. This limits the current in the test line during the later stage of the test (from the time the dielectric layer is about to break down to the time it breaks down), that is, limits the current flowing into the wafer, so as to prevent the large current from burning out the test structure, probes, etc.

[0037] Although Figure 6The diagram shows a single-pin socket test system, where the probe socket 2 has only one probe port. However, the probe socket 2 can also be a multi-pin socket, meaning it can have two or more probe ports. In a multi-pin socket test system, the probe socket has at least two probe ports, requiring two or more source meters 1 and two or more current control modules 5. Each test line in the multi-pin socket test system has one source meter 1, one current control module 5, and one probe port 21. The current control module 5 is connected in series via a first signal port 54 and a second signal port 55 between the target current output port of the source meter 1 (if the source meter 1 has only one current output terminal, the target current output terminal is that single current output terminal; if the source meter 1 has at least two current output terminals, the target current output terminal is any one of them) and the probe port. Each circuit control module 5 is connected to a driver 7, and each driver 7 is connected to an external power supply 6. (Refer to...) Figure 3 (The source table and probe ports are not shown; each first signal port is connected to source table 1, and each second signal port is connected to probe port 21.) If... Figure 6 The single-pin socket test system shown is considered as a test circuit. In a multi-pin socket test system, each probe port on the probe socket is electrically connected to a... Figure 6 The test circuit shown.

[0038] The following explanation uses the target test line (which can be any test line in the multi-pin socket test system) as an example in a multi-pin socket test system (which has two or more probe ports).

[0039] The target test circuit includes: a target source meter, a target current control module, and a target probe port. The target current control module is connected in series between the target current output port of the target source meter and the target probe port (for ease of understanding, it can be...). Figure 6 The single-pin socket testing system shown is considered a special case of the multi-pin socket testing system, where only one probe is installed for testing. Further... Figure 6The single-pin socket test system shown is considered as the target test circuit of the multi-pin socket test system. The target current control module includes two lines and a switch module. Each of the two lines is used to electrically connect the target current output terminal of the target source meter to the target probe port, and the resistance value on each line is different. The switch module is used to receive the control signal output by the driver and control the on / off state of each of the at least two lines according to the received control signal. Those skilled in the art can understand the connection relationship and operation mode of the target test circuit in the multi-pin socket test system based on the foregoing description; correspondingly, they can also understand the connection relationship and operation mode of other test circuits, so they will not be elaborated further here.

[0040] like Figure 3 As shown, Figure 3 The substrate 51 shown can be used in a multi-pin connector testing system. Please refer to [link / reference]. Figure 3 and Figure 6 It is obvious that Figure 3 In the schematic diagram shown, at least one current control module 5 is integrated on the same substrate 51, and these current control modules 5 on the substrate 51 are arranged in a (linear) array. The control terminal of the switch module in each current control module is connected to a driver 7, and each driver 7 is electrically connected to an external power supply 6 via a jumper. The structure and operation of each current control module 5 are similar to... Figure 4 , Figure 5 and Figure 6 The implementation methods shown are the same, so they will not be repeated here. Please refer to the previous text for details.

[0041] It should be further explained that the external power supply 6 can perform multiplex control on at least one driver 7 integrated on the same substrate 51. The current monitor in the driver 7 is connected to the first line 52 of the current control module 5, and the switching unit 62 in the driver 7 is connected to the switching module in the current control module 5. That is, each current control module 5 has an independent current monitor, voltage comparison unit 61, and switching unit 62. However, the current monitor of each current control module 5 detects the current on the first line of its respective current control module 5, and the control signal obtained by the switching unit of each current control module 5 is... The reference voltage of each current control module 5's corresponding comparison unit can be provided either uniformly or independently. It can be provided uniformly or independently.

[0042] This application also provides a probe card testing system. For example... Figure 7 As shown, Figure 7 This is a schematic diagram of a probe card testing system provided in an embodiment of this application. Please refer to... Figure 7The probe card testing system 300 includes a substrate 301. A first signal port 302 is disposed around the periphery of the substrate 301. Second signal ports 303 are arranged at intervals at the center of the surface of the substrate 301. A plurality of current control modules 304 are also disposed on the substrate 301. Each current control module 304 is connected to one of the second signal ports 303 and is disposed around the second signal ports 303. Switch modules in the current control modules 304 are connected to drivers 7, and the drivers 7 are connected to an external power supply 6. (Comparison) Figure 3 and Figure 7 As can be seen, substrate 301 is equivalent to substrate 51, and the first signal port 302 on substrate 301 is equivalent to the first signal port 54 on substrate 51, used to connect the test signals of the probe card testing equipment; the second signal port 303 on substrate 301 is equivalent to the second signal port 55 on substrate 51, used as a probe port to connect with the probe; the current control module 304 on substrate 301 is exactly the same as the current control module 5 on substrate 51, the driver 7 on substrate 301 is exactly the same as the driver 7 on substrate 51, and the external power supply 6 on substrate 301 is exactly the same as the external power supply 6 on substrate 51. Therefore, based on the foregoing description, those skilled in the art can understand that the current control module 304 and driver 7 in the probe card testing system of this embodiment have the same structure and working principle as the current control module 5 and driver 7 in the aforementioned substrate 51 or pin socket testing system, which can be understood by those skilled in the art based on the foregoing. Therefore, it will not be described again here.

[0043] In some alternative embodiments, at least one current control module 304 is arranged in an array on the substrate 301. The substrate 301 is in the shape of a disc; the second signal ports 303 are arranged in a linear array on the substrate 301; and at least one first signal port 302 is arranged in a ring array on the substrate 301, surrounding all the second signal ports 303.

[0044] In this embodiment, when testing a wafer using the testing system provided in this application, probes can be installed on the probe ports of the probe holder or probe card. The probes then contact preset contacts on the wafer. The current applied to the wafer by the source meter through the probes can be controlled via line selection in the current control module. For example, the source meter is electrically connected to the probes through the current control module. In the initial stage of the Vramp test, the first line in the current control module is turned on by the switching module, while the second line (with a resistance value greater than that of the first line) is turned off. In the later stage of the Vramp test, the first line in the current control module is turned on by the switching module, while the second line is turned on. This allows for control of the current in the test circuit at different test stages, preventing unnecessary losses or safety hazards caused by large currents in the test circuit during the later stages of testing. Therefore, the testing system provided in this application can help wafer testing personnel control the current in the circuit during Vramp and / or TDDB tests to prevent unnecessary losses and / or safety accidents caused by large currents when the dielectric layer is broken down.

[0045] The above descriptions are merely embodiments of this application and do not limit the patent scope of this application. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art, under the guidance of this application, may make equivalent structural or procedural transformations based on the description and drawings of the embodiments of this application, or directly or indirectly apply them to other related technical fields, without departing from the spirit and scope of protection of the claims. All such transformations are similarly included within the patent protection scope of the embodiments of this application.

Claims

1. A substrate for semiconductor reliability testing, characterized in that, The substrate includes: At least one first signal port is located on the surface of the substrate for connecting a test signal; At least one second signal port is located on the surface of the substrate for connecting a probe; At least one current control module is located between the first signal port and the second signal port. The current control module includes a first line, a second line, and a switch module. The first ends of the first line and the second line are connected in parallel to form a total line and connected to the first signal port. The second end of the first line is connected to the second signal port. At least one driver is provided, one end of which is connected to the first line and monitors the voltage of the first line, and the other end of which is connected to the switch module. In operation, the driver outputs a control signal to the switch module, and the switch module receives the control signal output by the driver to switch the connection between the first line / second line and the second signal port.

2. The substrate according to claim 1, characterized in that, The resistance value on the second line is greater than the resistance value on the first line.

3. The substrate according to claim 2, characterized in that, The switching module includes: The controller has a first contact located at the second end of the first line, a second contact located at the second end of the second line, and a third contact electrically connected to the second signal port. The controller's control terminal is used to receive a control signal output by the driver to drive the third contact to close with one of the first and second contacts.

4. The substrate according to claim 2, characterized in that, A current-limiting resistor is also connected in series on the second line.

5. The substrate according to claim 1, characterized in that, The driver includes: A current monitor, connected to the first line, is used to monitor the real-time current on the first line and convert the monitored real-time current into real-time voltage. A voltage comparison unit, electrically connected to the current monitor, is used to compare the real-time voltage received from the current monitor with a reference voltage and output a drive signal. The switching unit is connected at one end to the voltage comparison unit and at the other end to the switching module. The switching unit is used to receive the drive signal and output the control signal to the switching module.

6. The substrate according to claim 5, characterized in that, The current monitor is a Hall sensor.

7. The substrate according to claim 1, characterized in that, The substrate also includes an external power supply located on the surface of the substrate and connected to the driver to provide power to the driver.

8. The substrate according to claim 7, characterized in that, The substrate includes: a plurality of first signal ports, a plurality of second signal ports, a plurality of current control modules, and a plurality of drivers, all of which are connected to the external power supply.

9. A pin header testing system, characterized in that, include: At least one source table; A needle holder, wherein at least one probe port is provided on the needle holder and a probe is installed in the probe port; The substrate as described in any one of claims 1 to 8, wherein a first signal port of the substrate is connected to the source meter, the source meter transmits a test signal to the first signal port, and a second signal port of the substrate is connected to the probe port.

10. A probe card testing system, characterized in that, include: The substrate as described in any one of claims 1 to 7, A plurality of first signal ports are arranged around the periphery of the substrate, and the first signal ports are used to connect to the test signals of the probe card machine. Several second signal ports are spaced apart at the center of the surface of the substrate, and the second signal ports are connected to the probe as probe ports. Several current control modules are connected one-to-one with the second signal port and are arranged around the second signal port; Several drivers are provided, and the switching modules in the current control module are connected to each driver in a corresponding manner. All drivers are connected to an external power supply.

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