Impedance measurement circuit

Abstract

The utility model provides a kind of impedance measurement circuit, including electrically controlled oscillator, electrically controlled oscillator is configured as according to the power supply voltage existing on power rail generates oscillation signal. Impedance measurement circuit includes edge sampler, edge sampler is coupled to electrically controlled oscillator and is configured to generate first signal, and first signal is based on the first transition edge of first sampling frequency signal and samples oscillation signal. Impedance measurement circuit includes accumulator, accumulator is coupled to edge sampler and is configured to accumulate first signal, to generate second signal based on the third transition edge of second sampling frequency signal. Impedance measurement circuit includes transition detector, transition detector is configured to generate second sampling frequency signal based on detecting the second transition edge of first sampling frequency signal.

Description

Technical Field

[0001] This utility model relates to an impedance measurement circuit. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from the continuous shrinking of the smallest feature size, which allows more components to be integrated into a given area. Utility Model Content

[0003] An impedance measurement circuit according to an embodiment of the present invention includes a voltage-controlled oscillator (VCO), an edge sampler, an accumulator, and a transition detector. The VCO is configured to generate an oscillation signal based on a power supply voltage present on a power rail. The edge sampler is coupled to the VCO and configured to sample the oscillation signal based on a first transition edge of a first sampling frequency signal to generate a first signal. The accumulator is coupled to the edge sampler and configured to accumulate the first signal to generate a second signal based on a third transition edge of a second sampling frequency signal. The transition detector is configured to generate the second sampling frequency signal based on detecting a second transition edge of the first sampling frequency signal.

[0004] An impedance measurement circuit according to an embodiment of the present invention includes a voltage-controlled oscillator (VCO), an edge sampler, an accumulator, and a transition detector. The VCO is configured to generate an oscillation signal based on a power supply voltage present on a power rail. The edge sampler is coupled to the VCO and configured to sample the oscillation signal based on the rising edge of a first sampling frequency signal. The accumulator is coupled to the edge sampler and configured to accumulate the sampled signal based on the rising edge of a second sampling frequency signal to generate a measurement result. The transition detector is configured to generate the second sampling frequency signal based on detecting the falling transition edge of the first sampling frequency signal.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 It is a timing diagram of the respective waveforms of the power supply voltage signal and the sampling frequency signal according to some embodiments.

[0007] Figure 2 This is an example circuit diagram of an on-chip system for extracting a profile of a power transmission network, according to some embodiments.

[0008] Figure 3 This is an example circuit diagram of an impedance measurement circuit according to some embodiments.

[0009] Figure 4 It is based on some implementation examples in operation Figure 3 The impedance measurement circuit measures the waveforms of various signals.

[0010] Figure 5 This is an example circuit diagram of another impedance measurement circuit according to some embodiments.

[0011] Figure 6 This is an example circuit diagram of a transition detector according to some embodiments.

[0012] Figure 7 This is an example circuit diagram of an accumulator according to some embodiments.

[0013] Figure 8 This is a flowchart of an example method for operating a built-in self-test circuit for power impedance measurement according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0016] With the trend towards increasing integration density, the high-performance computing (HPC) market has become more widespread and is being used extensively in advanced networking and server applications, such as the Industrial Internet of Things (IIoT) and engineering applications, especially in artificial intelligence (AI) related products that require high data rates, increased bandwidth, and reduced latency. However, as the package size containing HPC components becomes larger, inter-die communication and power consumption of HPC circuitry have become more challenging issues.

[0017] HPC circuits typically consume large currents to perform complex calculations at high speeds, are capable of processing large datasets, and generate significant power (or ground) bounces. To minimize common-mode current generation within the silicon package of high-current-consuming circuits, a stable power delivery network (PDN) is usually required. Any bounces (noise) on the power supply or reference ground can lead to simultaneous switching noise or signal integrity issues, as well as electromagnetic interference (EMI). Furthermore, if the power supply or ground bounce exceeds the margin level, the component may fail to function properly. Therefore, ensuring PDN stability is a critical issue.

[0018] Power impedance measurement (PIM) or power monitoring circuits are frequently used to ensure robust power delivery networks. To ensure sufficient timing margin, one or more digital components (e.g., accumulators) in existing PIM circuits are typically deliberately slowed down (e.g., started at a deliberately lower frequency). For example, the frequency driving these digital components might be reduced to half the frequency of the PDN test. This can adversely increase (e.g., double) the test time. Therefore, existing PIM circuits are not entirely satisfactory in some respects.

[0019] This disclosure provides various embodiments of impedance measurement circuitry that can more efficiently and accurately characterize the equivalent-time sampling (ETS) of a power transmission network (PDN) compared to existing power impedance measurement (PIM) circuitry, and significantly reduce test time. Generally, a PDN is configured to supply a supply voltage to various integrated circuits (ICs). In the various embodiments of this disclosure, the impedance measurement circuitry disclosed herein may include an edge sampler and an accumulator, which may be activated respectively by first and second sampling frequency signals having the same frequency, further equal to the frequency used to test the PDN (e.g., to generate a profile of the PDN). The edge sampler may sample an oscillating signal generated according to the voltage present on the PDN using the rising edge of the first sampling frequency signal, and the accumulator may accumulate the sampled signal using the rising edge of the second sampling frequency signal to produce a measurement result. The disclosed impedance measurement circuitry also includes a transition detector. The second sampling signal may be generated by the transition detector based on detecting the falling edge of the first sampling frequency signal. The falling edge (of the first sampling frequency signal) of the second sampling frequency signal is immediately followed by the rising edge (of the first sampling frequency signal). In other words, each time the edge sampler samples a data point of the oscillation signal, the accumulator can be activated within half a cycle of the first sampling frequency signal to accumulate the sampled signal. Therefore, the accuracy of the accumulator can be significantly improved, which helps to reduce the test time of the disclosed impedance measurement circuit.

[0020] Figure 1 This is a timing diagram of the respective waveforms of the power supply voltage signal and the sampling frequency signal according to some embodiments of this disclosure. It should be noted that... Figure 1 The waveform shown is merely an example and is not intended to limit this disclosure.

[0021] As shown in the figure, the periodic power supply voltage signal VP represents the voltage difference signal of the power transmission network (PDN), and the sampling frequency signal SCLK is the frequency signal used to sample the power supply voltage signal VP. Points VS1, VS2, and VS3 on the VP waveform can correspond to the first sampling point, the second sampling point, and the third sampling point, respectively. Since the sampling rate of the sampling frequency signal SCLK is lower than the frequency of the power supply voltage signal VP, a lower frequency sampling frequency signal SCLK can be used to sample the power supply voltage signal VP multiple times to completely construct the voltage difference signal of the power transmission network.

[0022] Equivalent Time Sampling (ETS) is typically used to construct the entire waveform of a power supply voltage signal VP by accumulating the sampling frequency signal SCLK over multiple waveform cycles. The sampling frequency signal SCLK repeatedly samples the power supply voltage signal VP over multiple cycles. Alternatively, the sequential sampling method of ETS can be used to capture the entire waveform by sequentially introducing small delays (e.g., DT1, DT2, and DT3) to acquire portions of the real-time waveform during multiple trigger events. Over time, these portions are assembled into the complete waveform. When using the sequential sampling method of ETS, the sampling frequency signal SCLK acquires the sampled signal from each trigger event, with a fixed delay between each acquisition. For example, the delay DT1 is one time the least significant bit (LSB) of the digital value of the sampling frequency signal SCLK period, sometimes referred to as T. LSB The delay DT2 is twice the LSB of the digital value of the sampling frequency signal SCLK period, and the delay DT3 is three times the LSB of the digital value of the sampling frequency signal SCLK period. In other words, DT1 = T LSB DT2 = 2 × T LSB And DT3 = 3 × T LSB The delay values ​​DT1, DT2, and DT3 can be variable.

[0023] ETS's sequential sampling method offers extremely high bandwidth (60 GHz and above), providing the higher timing resolution and accuracy required for telecommunications and device characterization, and is particularly suitable for multiple captures and repeated waveforms. Over time, the instrument accumulates enough sampled signal to reconstruct the waveform. This method ensures that the sampling rate of the sampling frequency signal SCLK is slower than that of the power supply voltage signal VP to obtain all the sampling points needed for accurate waveform reconstruction.

[0024] Figure 2 This is an example circuit diagram of a system (e.g., circuitry on a chip) 200 for extracting an overview of a power delivery network, according to some other embodiments. As shown, the circuitry on a chip 200 includes a power delivery network 201 and a power impedance measurement built-in self-test (PIM BIST) circuitry 202. In some embodiments, the circuitry on a chip 200 can be used for input and output (I / O) power rails.

[0025] The power delivery network 201 is electrically connected to the PIM BIST circuit 202. The power delivery network 201 and the PIM BIST circuit 202 may be connected in parallel. The PIM BIST circuit 202 may include a probe 203, a current extractor 204, and a switch 205. In some embodiments, the current extractor 204 and the switch 205 are connected in series. In some embodiments, the probe 203 is connected in parallel with one end of the switch 205 and the other end of the current extractor 204. The PIM BIST circuit 202 is used to capture an overview of the power delivery network 201 and test its robustness, and is often used for large-scale testing. The voltage difference V across the probe 203 is generated by the difference between the internal power supply VDDS and the internal ground source VSSS. In some embodiments, the voltage difference V corresponds to the power supply voltage signal VP discussed above. The power delivery network 201 is used to provide voltage within specified limits and to provide acceptable noise for each active device.

[0026] The power transmission network 201 may include or be modeled as a capacitor C1, resistors R1-R3, and inductors L1 and L2. Resistors R1 and inductors L1 are connected in series on a first power rail connected to an external power source VDDE. Resistors R2 and inductors L2 are connected in series on a second power rail connected to an external ground source VSSE. Capacitor C1 is coupled between the first and second power rails, and resistor R3 is coupled in parallel with capacitor C1. Capacitor C1, resistors R1-R3, and inductors L1 and L2 may be parasitic components.

[0027] The PDN circuit is configured to use the power generated by the external power supply VDDE and the external ground source VSSE as an internal power source to deliver power to all devices in the integrated circuit. Typically, after the integrated circuit layout is generated, various subsequent test steps are performed to verify the layout design. Test tools simulate the layout design by assuming the power delivery network circuit provides a constant voltage source to each circuit component of the integrated circuit. During actual operation of the integrated circuit, each component in the integrated circuit may be associated with a voltage drop between the power rails. This voltage drop may be due to various parasitic components in the power delivery network circuit; for example, capacitor C1, resistors R1-R3, and inductors L1 and L2 may be parasitic components.

[0028] In some embodiments, the power delivery network 201 of the on-chip circuitry 200 provides an interconnect framework in which the switch 205 is allowed to control the on / off state of the current extractor 204. The external power supply VDDE of the power delivery network 201 may be bulky, thus requiring interconnection. In some embodiments, the current I1 through the components of the power delivery network 201 can cause direct current (DC) step-down and voltage fluctuations. In some embodiments, the power delivery network 201 is used to regulate voltage to supply the current required over time. In some embodiments, the speed or frequency of operation of the power delivery network 201 determines the speed or frequency at which charge can be supplied to or removed from the capacitor.

[0029] On-chip circuitry 200 is configured to measure power impedance by extracting a component profile of power delivery network 201. Current extractor 204 is used to generate a step response when power delivery network 201 is under load. In some embodiments, current extractor 204 may include a fast current loop that detects a current that gradually increases through a power switch (e.g., switch 205) and converges to a step value. Upon receiving the step response, PIM BIST circuitry 202 can measure the voltage difference V (or power supply voltage signal VP) between internal power supplies VDDS and VSSS. Therefore, a model (e.g., profile) of power delivery network 201 can be extracted based on the voltage difference V (or power supply voltage signal VP).

[0030] Figure 3 Example circuit diagrams of an impedance measurement circuit 300 are shown according to various embodiments of this disclosure. The impedance measurement circuit 300 is configured to perform a time-domain sensing method to measure the power impedance of a power transmission network, as described above. Figure 2 As described above. For example, the impedance measurement circuit 300 can be an example implementation of the PIM BIST circuit 202. It should be understood that... Figure 3 The circuit diagram has been simplified, therefore the impedance measurement circuit 300 may include any various other components while still remaining within the scope of this disclosure.

[0031] As shown in the figure, the impedance measurement circuit 300 includes a current source 310, a voltage controlled oscillator (VCO) 320, an edge sampler 330, an accumulator 340, a transition detector 350, and a delay circuit 360. In some embodiments, the edge sampler 330 and the accumulator 340 may be collectively referred to as the operating circuitry of the impedance measurement circuit 300. As a brief overview, this operating circuitry of the impedance measurement circuit 300 of this disclosure can sense a power supply voltage signal transmitted by a power transmission network based on two sampling frequency signals having the same frequency, thereby generating a measurement result describing the profile of the power transmission network. Details of the impedance measurement circuit 300 will be described below.

[0032] Current source 310 is electrically connected to one or more power rails. The power rails can provide an internal (or sensed) power supply VDDS and an internal (or sensed) power ground VSSS, transmitted via a corresponding power delivery network. In some embodiments, current source 310 can provide a constant current between the power rails. Current source 310 can draw current from internal power supply VDDS to internal power ground VSSS. Furthermore, current source 310 can be periodically activated to draw current based on a trigger signal (hereinafter referred to as the "TRIG signal") generated based on a global sampling frequency signal SCK (hereinafter referred to as the "SCK signal"). Therefore, the SCK signal and the TRIG signal can have the same frequency (f...). CLK / N), where N is an integer, f CLK It is T CLK The reciprocal of T CLK It is the period of the frequency signal (CLK) provided by the frequency source.

[0033] Edge sampler 330 is electrically coupled to VCO 320 and delay circuit 360, and accumulator 340 is electrically coupled to edge sampler 330 and transition detector 350. VCO 320 can generate an oscillation signal S1 (hereinafter referred to as "S1 signal") based on changes in power supply voltage signal VP (e.g., the voltage difference between internal power supply VDDS and internal power supply ground VSSS). Edge sampler 330 can sample S1 signal based on a first sampling frequency signal SAMP (hereinafter referred to as "SAMP signal") to output signal S2 (hereinafter referred to as "S2 signal").

[0034] In various embodiments of this disclosure, the SAMP signal can be provided by delay circuit 360 by delaying the SCK signal by a delay amount τ. The delay amount τ may correspond to... Figure 1One of the delay values ​​DT1, DT2, and DT3 described herein. Edge sampler 330 can sample the S1 signal based on the rising edge of the SAMP signal. In other words, whenever edge sampler 330 detects a rising edge of the SAMP signal, edge sampler 330 can sample the data point of the S1 signal as the S2 signal. Accumulator 340 can receive the S2 signal and selectively accumulate the S2 signal based on a second sampling frequency signal DoAcc (hereinafter referred to as the "DoAcc signal") to output a signal AccOut (hereinafter referred to as the "AccOut signal"). The DoAcc signal can be provided by transition detector 350 based on detecting the falling edge of the SAMP signal. For example, whenever transition detector 350 detects a falling edge of the SAMP signal, transition detector 350 can generate one of a plurality of pulses of the DoAcc signal. Therefore, the SAMP signal and the DoAcc signal have the same frequency (e.g., f). CLK / N), which is the same frequency as the SCK signal. The impedance measurement circuit 300 can output the AccOut signal as the measurement result, which can be used to construct an overview of the power transmission network.

[0035] In this configuration, accumulator 340 can perform accumulation at the same frequency as the SCK signal. For example, sampling can be performed on the rising edge of a pulse of the sampling frequency signal (e.g., the SAMP signal), and accumulation can be performed immediately after the falling edge of the same pulse. In other words, accumulation occurs within one period (T) of the sampling frequency signal (where T = N / f). CLK or N·T CLK This allows for the accumulation after a single sampling operation. The minimum setup time and hold time margin ensure that they are equal to T, respectively. Setup_Min (N / 2·T CLK -T Det ) and T Hold_Min (N / 2·T CLK +T Det ), where T Det This indicates the delay caused by the change in detector 350, which may be approximately equal to T. CLK Therefore, the testing time for each data point can be approximated as N·M·T. CLK , where M represents the number of accumulations performed to obtain the statistical result.

[0036] Figure 4 These are example waveforms illustrating the time-varying characteristics of various aforementioned signals when operating the impedance measurement circuit 300, according to various embodiments of the present disclosure. For example, in Figure 4 The image at least shows the frequency signal (CLK), trigger signal (TRIG), and power supply voltage signal (VP or V). PDNThe signals are: a first sampling frequency signal (SAMP), a sampled signal (S2), a second sampling frequency signal (DoAcc), and an accumulated signal (AccOut). It should be understood that the proportions of the signals shown are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0037] As shown in the figure, the period of the CLK signal is TCLK (i.e., the frequency is 1 / T). CLK In some embodiments, the impedance measurement circuit 300 may include a divider (not shown) configured to receive the CLK signal from a frequency source and divide the frequency by N (i.e., f). CLK / N) or multiply the period by N (i.e., N×T) CLK This provides a global sampling frequency signal (SCK signal) or a trigger signal (TRIG signal). The current source 310 and delay circuit 360 can receive the SCK signal and the TRIG signal, respectively. The SCK signal and the TRIG signal can have the same frequency (f...). CLK / N). By based on frequency (f) CLK The power supply voltage signal VP can also be switched on and off at the same frequency (f) during the repeated switching of / N). CLK / N) is provided (e.g., via an electronically controlled oscillator). On the other hand, after receiving the SCK signal, the delay circuit 360 can delay the SCK signal by multiple delay amounts (e.g., 1×LSB, 2×LSB, 3×LSB, etc., spanning the entire period N×T). CLK () as the SAMP signal.

[0038] In some embodiments, whenever the SAMP signal transitions from a low logic state to a high logic state (rising edge), the edge sampler 330 can be activated to sample a data point of the power supply voltage signal VP as the S2 signal. Furthermore, whenever the SAMP signal transitions from the same high logic state to the next low logic state (the falling edge immediately following the rising edge), the transition detector 350 can generate one of a plurality of pulses constituting the DoAcc signal. Therefore, the SAMP signal and the DoAcc signal, serving as the first and second sampling frequency signals of the edge sampler 330 and accumulator 340 respectively, can have the same frequency (f...). CLK / N). By recognizing the rising edge of the DoAcc signal, accumulator 340 can be activated to accumulate the S2 signal as the AccOut signal, which may have the same frequency (f CLK / N).

[0039] Figure 5Example circuit diagrams of another impedance measurement circuit 500 are described according to various embodiments of this disclosure. Impedance measurement circuit 500 is substantially similar to impedance measurement circuit 300, except that impedance measurement circuit 500 does not contain a current source. For example, impedance measurement circuit 500 could be another example implementation of PIM BIST circuit 202. Therefore, the following discussion of impedance measurement circuit 500 will focus on the differences between the two.

[0040] As shown in the figure, the impedance measurement circuit 500 includes a gate control circuit 510, a processing circuit 520, an electrically controlled oscillator (VCO) 530, an edge sampler 540, an accumulator 550, a transition detector 560, and a delay circuit 570. In some embodiments, the gate control circuit 510 is configured to apply a gate control frequency signal (hereinafter referred to as the "GCLK signal") to the processing circuit 520 to adjust the power supply voltage signal VP (or the voltage difference between the internal power supply VDDS and the internal power supply ground VSSS). In some embodiments, the processing circuit 520 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), a high-performance computing (HPC) device, or other suitable devices. Other components (e.g., 530, 540, 550, 506, and 570) and Figure 3 The components described in the previous section are basically the same, so they will not be described again.

[0041] The gate control circuit 510 is configured to generate a GCLK signal based on a frequency signal (hereinafter referred to as the "CLK signal") and a globally sampled frequency signal (hereinafter referred to as the "SCK signal"). The gate control circuit 510 can be implemented as an isolated frequency gate control circuit. In various embodiments, the GCLK signal can be applied to various devices, such as devices and systems requiring precise start-up timing, devices requiring operation in specific timing regions, devices requiring activation or deactivation under strict timing requirements without significant uncertainty, and systems requiring activation at specific points in time, such as rocket launch systems.

[0042] As a non-limiting example, the gate control circuit 510 may include a D-type flip-flop (e.g., a D-type flip-flop) and an AND gate. The data input of the flip-flop may receive an SCK signal, the frequency input may receive a CLK signal, and the output of the flip-flop 510 may output an enable signal GN, which is received by one of the two inputs of the AND gate. The other input of the AND gate may receive the CLK signal. When triggered (or activated) by the edge of the CLK signal, the flip-flop may transmit the logic value of the SCK signal to its output to generate the enable signal. The flip-flop may invert the logic value of the CLK signal and the corresponding voltage value.

[0043] Figure 6 The change detector disclosed is illustrated in various embodiments of this disclosure (e.g., Figure 3 350 in Figure 5 The following is an example circuit diagram of the 560 (in the example circuit). Figure 6 The transition detector shown is called "Transition Detector 600". It should be understood that... Figure 6 The circuit diagram has been simplified, therefore the transition detector 600 may include any other various components while still remaining within the scope of this disclosure.

[0044] As shown in the figure, the transition detector 600 includes a delay circuit 610, a plurality of D-type flip-flops 620, 630 and 640, an inverter 650, and an AND gate 660. In some embodiments, the delay circuit 610 operatively forms the analog side of the transition detector 600, while the remaining components operatively form the digital side of the transition detector 600. The delay circuit 610 (on the analog side) is configured to receive signals from another delay circuit (e.g., Figure 3 360 in Figure 5 The flip-flop 620 (570) receives a first sampling frequency signal (e.g., a SAMP signal) and provides a SampDone signal to the digital side. Specifically, flip-flops 620 to 640 can be connected in series, and inverter 650 is connected in parallel with the last flip-flop 640. Furthermore, the logic gate has a first input, a second input, and an output. The first input is configured to receive the output signal provided by inverter 650, the second input is configured to receive the output signal provided by the last flip-flop 640, and the output is configured to perform an AND operation on the two input signals to provide a second sampling frequency signal (e.g., a DoAcc signal) for activating the corresponding accumulator (e.g., ...). Figure 3 340 in Figure 5 (550 in the middle).

[0045] Figure 7 The accumulator disclosed is based on various embodiments described herein (e.g., Figure 3 340 in Figure 5 The following is an example circuit diagram of the 550 (in the example circuit). Figure 7 The accumulator shown is called "Accumulator 700". It should be understood that... Figure 7 The circuit diagram has been simplified, therefore, the accumulator 700 may include any other various components, while still remaining within the scope of this disclosure.

[0046] As shown in the figure, the accumulator 700 includes an adder 710, a multiplexer 720, and a D-type flip-flop 730. The adder 710 can receive a first input signal (e.g., the S2 signal) and a second input signal (e.g., the AccOut signal) from the output of the accumulator 700 via one or more other D-type flip-flops, and sums the first and second input signals. The multiplexer 720 may have a first input terminal and a second input terminal, the first input terminal being configured to receive the AccOut signal, and the second input terminal being configured to receive the summation signal output from the adder 710. Furthermore, the multiplexer 720 can select either the signal received from its first or second input terminal based on a second sampling frequency signal (e.g., the DoAcc signal). For example, when the DoAcc signal is in a low logic state, the multiplexer 720 can select the DoAcc signal (i.e., keep the AccOut signal unchanged); when the DoAcc signal is in a high logic state, the multiplexer 720 can select the summation signal (i.e., add the DoAcc signal to the S2 signal).

[0047] Figure 8 This is a flowchart illustrating an example method 800 for obtaining a profile of a power transmission network based on two sampled frequency signals having the same frequency, according to various embodiments of this disclosure. The operation of method 800 can be performed by the aforementioned impedance measurement circuit (e.g., Figures 3 to 7 Therefore, some reference numbers used above may be repeated in the following discussion of method 800. Furthermore, it should be understood that method 800 has been simplified and therefore can be... Figure 8 Additional operations are provided before, during, and after Method 800, while some other operations may only be briefly described here.

[0048] Method 800 begins with operation 810, sampling an oscillation signal generated based on the rising edge of the first sampling frequency signal, according to the voltage present on the power rail. The voltage on the power rail (VP or V) PDN The voltage can be provided by the corresponding power transmission network, and can be a voltage difference across the power rails, such as VDDS-VSSS. The oscillation signal (e.g., the S1 signal) can be provided by an electrically controlled oscillator (e.g., Figure 3 320 in Figure 5 The 530 in the middle) is generated, and the electrically controlled oscillator is controlled by voltage VP. Edge sampler ( Figure 3 330 in Figure 5The 540) is operationally coupled to an electronically controlled oscillator, which samples a data point on the S1 signal each time a rising edge of the first sampling frequency signal (e.g., the SAMP signal) is detected, to generate a sampled signal (e.g., the S2 signal). In some embodiments, the first sampling frequency signal may have a first frequency substantially similar to the frequency of the global sampling frequency signal (e.g., the SCK signal), but with a delay.

[0049] Method 800 continues with operation 820, generating a second sampling frequency signal based on the falling edge of the first sampling frequency signal. Continuing the example above, the detector ( Figure 3 350 in Figure 5 The 560 in the diagram can receive a first sampling frequency signal and identify a falling edge of the first sampling frequency signal to generate a second sampling frequency signal (e.g., a DoAcc signal). In some embodiments, immediately following a rising edge used to sample the S1 signal, the transition detector can generate a pulse for the second sampling frequency signal. Therefore, the second sampling frequency signal can have a second frequency substantially similar to the first frequency.

[0050] Method 800 continues with operation 830, accumulating the sampled signal based on the second sampling frequency signal to generate a measurement result. Continuing the example above, the accumulator (e.g., Figure 3 340 in Figure 5 The 550 signal in the circuit is coupled to an edge sampler, which can selectively accumulate the S2 signal based on a second sampling frequency signal (DoAcc signal) to produce a measurement result (e.g., an AccOut signal). In some embodiments, the accumulator may add the AccOut signal to the sampled S2 signal whenever it detects a rising edge of the DoAcc signal. Otherwise, the accumulator may leave the AccOut signal unchanged. Therefore, the disclosed impedance measurement circuit can construct an overview of a power transmission network based on multiple measurement results.

[0051] In one aspect of this disclosure, an impedance measurement circuit is disclosed. The impedance measurement circuit includes a voltage-controlled oscillator (VCO) configured to generate an oscillation signal based on a power supply voltage signal present on a power rail. The impedance measurement circuit includes an edge sampler coupled to the VCO and configured to sample the oscillation signal based on a first transition edge of a first sampling frequency signal to generate a first signal. The impedance measurement circuit includes an accumulator coupled to the edge sampler and configured to accumulate the first signal based on a third transition edge of a second sampling frequency signal to generate a second signal. The impedance measurement circuit includes a transition detector configured to generate a second sampling frequency signal based on the detection of a second transition edge of the first sampling frequency signal.

[0052] In a related embodiment, the first transition edge is the rising edge of the first sampling frequency signal, the second transition edge is the falling edge of the first sampling frequency signal, and the third transition edge is the rising edge of the second sampling frequency signal.

[0053] In a related embodiment, the first sampling frequency signal is associated with a first frequency, and the second sampling frequency signal is associated with a second frequency, wherein the first frequency is equal to the second frequency.

[0054] In a related embodiment, the impedance measurement circuit further includes: a current source coupled to the power rail and configured to draw current from the power rail according to a third sampling frequency signal; and a delay circuit configured to delay the third sampling frequency signal as the first sampling frequency signal.

[0055] In a related embodiment, the impedance measurement circuit further includes: a gate control circuit configured to generate a gate control frequency signal based on a third sampling frequency signal; a processing circuit coupled to the power rail and configured to draw current from the power rail according to the gate control frequency signal; and a delay circuit configured to delay the third sampling frequency signal as the first sampling frequency signal.

[0056] In a related embodiment, the second transition edge is separated from the first transition edge by half the period of the first sampling frequency signal.

[0057] In a related embodiment, the third transition edge is separated from the second transition edge by a delay corresponding to the transition detector.

[0058] In a related embodiment, the delay is approximately equal to one period of the frequency signal, which is 1 / N of the period of the first or second sampled frequency signal.

[0059] In a related embodiment, the transition detector includes: an inverter having an input and an output; a D-type flip-flop having an input and an output, the input of the D-type flip-flop being connected to the input of the inverter, and the output of the D-type flip-flop being connected to the output of the inverter; and an AND gate having a first input, a second input, and an output, the first input of the AND gate being connected to the output of the inverter, the second input of the AND gate being connected to the output of the D-type flip-flop, and the output of the AND gate being configured to provide the second sampling frequency signal.

[0060] In a related embodiment, the accumulator includes: an adder configured to receive the first signal and the second signal; a multiplexer having a first input and a second input, the first input of the multiplexer being configured to receive an output signal of the adder, the second input of the multiplexer being configured to receive the second signal, and the multiplexer being configured to provide an output signal, the output signal being one of the output signal of the adder or the second signal based on the second sampling frequency signal; and a D-type flip-flop configured to receive the output signal of the multiplexer and provide the second signal.

[0061] In another aspect of this disclosure, an impedance measurement circuit is disclosed. The impedance measurement circuit includes a voltage-controlled oscillator (VCO) configured to generate an oscillation signal based on a power supply voltage signal present on a power rail. The impedance measurement circuit includes an edge sampler coupled to the VCO and configured to sample the oscillation signal based on a rising edge of a first sampling frequency signal. The impedance measurement circuit includes an accumulator coupled to the edge sampler and configured to accumulate the sampled signal based on a rising edge of a second sampling frequency signal to produce a measurement result. The impedance measurement circuit includes a transition detector configured to generate a second sampling frequency signal based on the detection of a falling transition edge of the first sampling frequency signal.

[0062] In a related embodiment, the falling transition edge of the first sampling frequency signal immediately follows the rising transition edge of the first sampling frequency signal, with a time difference equal to half the period of the first sampling frequency signal.

[0063] In a related embodiment, the first sampling frequency signal is associated with a first frequency, and the second sampling frequency signal is associated with a second frequency, wherein the first frequency is equal to the second frequency.

[0064] In a related embodiment, the impedance measurement circuit further includes: a current source coupled to the power rail and configured to draw current from the power rail according to a third sampling frequency signal; and a delay circuit configured to delay the third sampling frequency signal as the first sampling frequency signal.

[0065] In a related embodiment, the impedance measurement circuit further includes: a gate control circuit configured to generate a gate control frequency signal based on a third sampling frequency signal; a processing circuit coupled to the power rail and configured to draw current from the power rail according to the gate control frequency signal; and a delay circuit configured to delay the third sampling frequency signal to serve as the first sampling frequency signal.

[0066] In a related embodiment, the transition detector includes: an inverter having an input and an output; a D-type flip-flop having an input and an output, the input of the D-type flip-flop being connected to the input of the inverter, and the output of the D-type flip-flop being connected to the output of the inverter; and an AND gate having a first input, a second input, and an output, the first input of the AND gate being connected to the output of the inverter, the second input of the AND gate being connected to the output of the D-type flip-flop, and the output of the AND gate being configured to provide the second sampling frequency signal.

[0067] In a related embodiment, the rising transition edge of the second sampling frequency signal is separated from the falling transition edge of the first sampling frequency signal by the delay of the transition detector.

[0068] In another aspect of this disclosure, a method for operating impedance measurement circuitry is disclosed. The method includes sampling an oscillating signal generated based on a voltage present on a power rail, based on the rising edge of a first sampling frequency signal. The method also includes generating a second sampling frequency signal based on the falling edge of the first sampling frequency signal. Finally, the method includes accumulating the sampled signals based on the second sampling frequency signal to produce a measurement result.

[0069] In a related embodiment, the first sampling frequency signal is associated with a first frequency, and the second sampling frequency signal is associated with a second frequency, wherein the first frequency is equal to the second frequency.

[0070] In a related embodiment, the falling transition edge of the first sampling frequency signal immediately follows the rising transition edge of the first sampling frequency signal, with a time difference equal to half the period of the first sampling frequency signal.

[0071] As used herein, the terms "about" and "approximately" generally refer to a given number of values ​​that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can mean that a given number of values ​​varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. An impedance measurement circuit, characterized in that, include: An electronically controlled oscillator is configured to generate an oscillation signal based on the power supply voltage present on the power rail; An edge sampler, coupled to the electrically controlled oscillator, is configured to sample the oscillation signal based on a first transition edge of the first sampling frequency signal to generate a first signal; An accumulator, coupled to the edge sampler, is configured to accumulate the first signal to generate a second signal based on the third transition edge of the second sampling frequency signal; as well as A transition detector is configured to generate the second sampling frequency signal based on detecting a second transition edge of the first sampling frequency signal.

2. The impedance measurement circuit according to claim 1, characterized in that, The first transition edge is the rising edge of the first sampling frequency signal, the second transition edge is the falling edge of the first sampling frequency signal, and the third transition edge is the rising edge of the second sampling frequency signal.

3. The impedance measurement circuit according to claim 1, characterized in that, The first sampling frequency signal is associated with a first frequency, and the second sampling frequency signal is associated with a second frequency, wherein the first frequency is equal to the second frequency.

4. The impedance measurement circuit according to claim 1, characterized in that, Also includes: A current source, coupled to the power rail, is configured to draw current from the power rail according to a third sampling frequency signal; as well as The delay circuit is configured to delay the third sampling frequency signal as the first sampling frequency signal.

5. The impedance measurement circuit according to claim 1, characterized in that, Also includes: The gate control circuit is configured to generate a gate control frequency signal based on a third sampling frequency signal; The processing circuit is coupled to the power rail and configured to draw current from the power rail according to the gate frequency signal; as well as The delay circuit is configured to delay the third sampling frequency signal as the first sampling frequency signal.

6. The impedance measurement circuit according to claim 1, characterized in that, The second transition edge is separated from the first transition edge by half the period of the first sampling frequency signal.

7. The impedance measurement circuit according to claim 1, characterized in that, The third transition edge is separated from the second transition edge by a delay corresponding to the transition detector.

8. The impedance measurement circuit according to claim 1, characterized in that, The accumulator includes: The adder is configured to receive the first signal and the second signal; A multiplexer having a first input and a second input, the first input of the multiplexer being configured to receive an output signal of the adder, the second input of the multiplexer being configured to receive a second signal, and the multiplexer being configured to provide an output signal, the output signal being either the output signal of the adder or a second signal based on a second sampling frequency signal; and A D-type flip-flop is configured to receive the output signal of the multiplexer and provide the second signal.

9. An impedance measurement circuit, characterized in that, include: An electronically controlled oscillator is configured to generate an oscillation signal based on the power supply voltage present on the power rail; An edge sampler, coupled to the electrically controlled oscillator, is configured to sample the oscillation signal based on the rising edge of the first sampling frequency signal to generate a sampled signal; An accumulator, coupled to the edge sampler, and configured to accumulate the sampled signal based on the rising edge of the second sampling frequency signal to produce a measurement result; and A transition detector is configured to generate a second sampling frequency signal based on detecting a falling transition edge of the first sampling frequency signal.

10. The impedance measurement circuit according to claim 9, characterized in that, The falling transition edge of the first sampling frequency signal immediately follows the rising transition edge of the first sampling frequency signal, with a time difference equal to half the period of the first sampling frequency signal.

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