A low power consumption load detection circuit

Abstract

The utility model provides a kind of low-power consumption load detection circuit, applied to circuit design technical field, by enabling control timing generation module to the input signal generated by OSC_32 clock signal source is divided frequency processing output rl_en signal, enabling control timing generation module is based on rl_en signal to generate antiphase signal rl_enn, rl_en signal and antiphase signal rl_enn cooperate control current mirror module and the on-off of comparator module;When rl_en signal is high level, current mirror module is turned on output detection current, comparator module starts and completes the comparison of detection voltage VAT and reference voltage vref;When rl_en signal is low level, current mirror module and comparator module are all off and no current consumption, effectively solve the problem that constant current source and comparator need continuous work in existing load detection circuit, power consumption is large, battery-powered device endurance time is short.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit design technology, and in particular to a low-power load detection circuit. Background Technology

[0002] Load detection is a key function for optimizing energy consumption in electronic devices. By identifying the connection status of external loads, it controls the start and stop of corresponding functional circuits, avoiding energy waste when there is no load. It is widely used in scenarios that rely on battery power, such as portable sensors, Bluetooth devices, and low-power IoT terminals.

[0003] Currently, the mainstream load detection technology uses a constant current source as the detection signal generation unit. The constant current source continuously outputs a detection current of a fixed amplitude. Since the constant current source needs to be kept on at all times to output a continuous detection current, the comparator also needs to be in working state throughout the process to achieve real-time comparison, resulting in high power consumption. Utility Model Content

[0004] This invention provides a low-power load detection circuit to solve the problem of high power consumption in existing load detection circuits.

[0005] On the one hand, this utility model provides a low-power load detection circuit, including:

[0006] Enable control timing generation module, current mirror module, comparator module, and ESD protection module;

[0007] The input terminal of the enable control timing generation module is connected to the OSC_32 clock signal source, and the output terminal of the enable control timing generation module is connected to the current mirror module and the comparator respectively; it is used to generate the rl_en signal and the inverted signal rl_enn based on the input signal of the OSC_32 clock signal source, and transmit the rl_en signal and the inverted signal rl_enn to the current mirror module and the comparator module respectively;

[0008] The power supply terminal of the current mirror module is connected to the power supply, the ground terminal of the current mirror module is grounded, the input terminal of the current mirror module is connected to the reference current ib, and the output terminal of the current mirror module is connected to the load resistor and the second fixed resistor through the first fixed resistor respectively. It is used to turn on when the rl_en signal is high level and the inverted signal rl_enn is low level. Based on the reference current ib, a mirror current ib1 is generated and transmitted to the load resistor and the second fixed resistor through the first fixed resistor. After the mirror current ib1 flows through the first fixed resistor and the load resistor, a detection voltage VAT is formed at the input terminal of the load resistor.

[0009] The first input terminal of the comparator module is connected to the output terminal of the current mirror module and is used to input the detection voltage VAT. The second input terminal of the comparator module is connected to the reference current ib. The output terminal of the comparator module is used to output the detection result signal out. When the rl_en signal is high, it is turned on and compares the magnitude of the detection voltage VAT with the magnitude of the reference voltage vref.

[0010] One end of the ESD protection module is connected to the chip output pin corresponding to the access end of the load resistor, and the other end of the ESD protection module is grounded.

[0011] Optionally, the current mirror module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

[0012] The source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of the third PMOS transistor, and the gate of the first PMOS transistor is connected to node N1.

[0013] The source of the second PMOS transistor is connected to the source of the first PMOS transistor, the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the second PMOS transistor is connected to node N1.

[0014] The source of the third PMOS transistor is connected to the drain of the first PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the drain of the third PMOS transistor is connected to the source of the fifth NMOS transistor.

[0015] The gate of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor.

[0016] The source of the fifth NMOS transistor is connected to the drain of the third PMOS transistor, the drain of the fifth NMOS transistor is connected to the source of the fourth NMOS transistor, and the gate of the fifth NMOS transistor is connected to a fixed potential.

[0017] The source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to node N2.

[0018] The source of the third NMOS transistor is connected to the source of the first NMOS transistor, the drain of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to node N2.

[0019] The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is connected to the source of the first NMOS transistor.

[0020] The source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, and the gate of the first NMOS transistor is connected to an inverted signal rl_enn.

[0021] The drain of the sixth NMOS transistor is grounded, the source of the sixth NMOS transistor is connected to node N2, and the gate of the sixth NMOS transistor is connected to the inverted signal rl_enn.

[0022] The source of the fifth PMOS transistor is connected to the power supply, the drain of the fifth PMOS transistor is connected to node N1, and the fifth PMOS transistor is connected to the rl_en signal.

[0023] Optionally, the enable control timing generation module includes a frequency divider, the input of which is connected to the OSC_32 clock signal source, and the output of which is connected to the input of the enable control timing generation module.

[0024] Optionally, after the input signal passes through the frequency divider, the high level of the output rl_en signal lasts for 100μs, with a period of 50ms and a duty cycle of 0.2%.

[0025] Optionally, the ESD protection module is a seventh NMOS transistor, with the source of the seventh NMOS transistor connected to the load resistor, the drain of the seventh NMOS transistor grounded, and the gate of the seventh NMOS transistor connected to the drain of the seventh NMOS transistor.

[0026] Optionally, when the rl_en signal is high and the inverting signal rl_enn is low, the first NMOS transistor is turned on, the second, third, fourth and fifth NMOS transistors are turned on, the sixth NMOS transistor is turned off, the first, second, third and fourth PMOS transistors are turned on, and the fifth PMOS transistor is turned off.

[0027] When the rl_en signal is low and the inverting signal rl_enn is high, the first NMOS transistor is off, the sixth NMOS transistor is on, the second, third, and fourth NMOS transistors are off, the fifth PMOS transistor is on, and the first, second, third, and fourth PMOS transistors are off.

[0028] Optionally, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor form a common source and common gate structure;

[0029] In this configuration, the first PMOS transistor and the second PMOS transistor are connected in series to form a PMOS common source and common gate branch, the third PMOS transistor and the fourth PMOS transistor form current mirrors with the PMOS common source and common gate branch respectively, and the fifth NMOS transistor and the fourth NMOS transistor are connected in series to form an NMOS common source and common gate branch.

[0030] Optionally, one end of the load resistor is connected to the chip output pin, and the other end of the load resistor is grounded;

[0031] When the load resistor is connected, the mirror current ib1 output by the current mirror module flows through the fourth PMOS transistor, the fifth NMOS transistor, the fourth NMOS transistor, the first fixed resistor, the second fixed resistor, and the load resistor to the ground terminal, forming a detection voltage VAT at the chip output pin; when the load resistor is not connected, the mirror current ib1 flows through the fourth PMOS transistor, the fifth NMOS transistor, the fourth NMOS transistor, and the fixed resistor and then floats, and the detection voltage VAT is the product of the sum of the first fixed resistor and the second fixed resistor and the mirror current ib1.

[0032] Optionally, the ratio of the output current of the second NMOS transistor, the output current of the third NMOS transistor, and the output current of the fourth NMOS transistor is 1:2:m.

[0033] Optionally, the ratio of the output current of the first PMOS transistor to the output current of the second PMOS transistor is 1:k.

[0034] The low-power load detection circuit provided by this utility model divides the input signal generated by the OSC_32 clock signal source by enabling the timing generation module and outputs the rl_en signal. Based on the rl_en signal, an inverted signal rl_enn is generated. The rl_en signal and the inverted signal rl_enn work together to control the on / off state of the current mirror module and the comparator module. When the rl_en signal is high, the current mirror module is turned on and outputs the detection current, and the comparator module starts and completes the comparison between the detection voltage VAT and the reference voltage vref. When the rl_en signal is low, both the current mirror module and the comparator module are turned off and there is no current consumption. This effectively solves the problems of continuous operation of the constant current source and comparator, high power consumption, and short battery life of battery-powered devices in existing load detection circuits. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a low-power load detection circuit provided in an embodiment of the present invention;

[0037] Figure 2 This is a low-power load detection circuit diagram provided in an embodiment of the present invention;

[0038] Figure 3 This is a signal timing generation circuit diagram provided in an embodiment of the present invention.

[0039] Figure label:

[0040] Among them, 1-Enable control timing generation module; 2-Current mirror module; 3-Comparator module; 4-ESD protection module; 5-Frequency divider;

[0041] Power supply - VDD; First fixed resistor - R0; Second fixed resistor - R1; Load resistor - RL; Chip output pin - AT;

[0042] First PMOS transistor - MP0; Second PMOS transistor - MP1; Third PMOS transistor - MP2; Fourth PMOS transistor - MP3; Fifth PMOS transistor - MP4;

[0043] First NMOS transistor - MN0; Second NMOS transistor - MN1; Third NMOS transistor - MN2; Fourth NMOS transistor - MN3; Fifth NMOS transistor - MN4; Sixth NMOS transistor - MN5; Seventh NMOS transistor - MN6. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0045] Figure 1 This is a schematic diagram of a low-power load detection circuit provided in an embodiment of the present invention; Figure 2 This is a low-power load detection circuit diagram provided in an embodiment of the present invention.

[0046] like Figure 1 and Figure 2 As shown, the low-power load detection circuit provided in this embodiment of the present invention includes:

[0047] Enable control timing generation module 1, current mirror module 2, comparator module 3, ESD protection module 4 and load resistor RL;

[0048] The input terminal of the enable control timing generation module 1 is connected to the OSC_32 clock signal source, and the output terminal of the enable control timing generation module 1 is connected to the current mirror module 2 and the comparator module 3 respectively. It is used to generate the rl_en signal and the inverted signal rl_enn based on the input signal of the OSC_32 clock signal source, and transmit the rl_en signal and the inverted signal rl_enn to the current mirror module 2 and the comparator module 3 respectively.

[0049] The power supply terminal of the current mirror module 2 is connected to the power supply VDD, the ground terminal of the current mirror module 2 is grounded, the input terminal of the current mirror module 2 is connected to the reference current ib, and the output terminal of the current mirror module 2 is connected to the second fixed resistor R1 and the load resistor RL through the first fixed resistor R0 respectively. It is used to turn on when the rl_en signal is high level and the inverted signal rl_enn is low level. Based on the reference current ib, a mirror current ib1 is generated and transmitted to the second fixed resistor R1 and the load resistor RL through the first fixed resistor R0. After the mirror current ib1 flows through the first fixed resistor R0, the second fixed resistor R1 and the load resistor RL, a detection voltage VAT is formed at the input terminal of the load resistor RL.

[0050] The first input terminal of comparator module 3 is connected to the output terminal of current mirror module 2, and is used to input the detection voltage VAT. The second input terminal of comparator module 3 is connected to the mirror current ibl. The output terminal of comparator module 3 is used to output the detection result signal out. It is turned on when the rl_en signal is high and compares the magnitude of the detection voltage VAT with the reference voltage vref. Comparator module 3 is... Figure 2 The comparator cmp in the code.

[0051] One end of the ESD protection module 4 is connected to the chip output pin AT corresponding to the input end of the load resistor RL, and the other end of the ESD protection module 4 is grounded.

[0052] The enable control timing generation module 1 serves as the time reference source for the low-power load detection circuit. The input terminal of the enable control timing generation module 1 is connected to an external OSC_32 clock signal. The clock signal is divided to generate the rl_en signal, which is then transmitted to the enable terminal of the current mirror module 2. On the other hand, an inverted signal rl_enn, which is opposite to the rl_en signal, is generated and transmitted to the enable terminal of the comparator module 3. The current mirror module 2 and the comparator module 3 only enter the working state when the rl_en signal is high and the inverted signal rl_enn is low. They are turned off at other times to reduce power consumption. The current mirror module 2 serves as the current generation unit for detection. The power supply terminal of the current mirror module 2 is connected to the power supply VDD to obtain power, and the ground terminal is grounded to form a loop. The input terminal is connected to the reference current ib as a reference. When the rl_en signal is high and the inverting signal rl_enn is low, the reference current ib is amplified into the mirror current ib1 based on the current mirror principle. After the mirror current ib1 flows out through the output terminal, it flows through the first fixed resistor R0, the second fixed resistor R1 and the external load resistor RL, and finally to the ground. The voltage drop generated by the mirror current ib1 on the series path of the first fixed resistor R0 and the second fixed resistor R1, and on the series path of the first fixed resistor R0 and the load resistor RL, will form a detection voltage VAT reflecting the load state at the input terminal of the load resistor RL, i.e., the chip output pin AT.

[0053] Comparator module 3 serves as the judgment unit for the detection result. Its first input terminal is connected to the input terminal of the load resistor RL to acquire the detection voltage VAT, and its second input terminal is connected to the reference voltage vref as the judgment threshold. It conducts when RL_e is high. By comparing VAT with vref, it outputs the detection result signal out. If VAT is less than vref, it indicates that a load is connected; otherwise, it indicates that there is no load. Furthermore, one end of the ESD protection module 4 is connected to the chip's output pin AT, and the other end is grounded. This absorbs external electrostatic interference, protects the circuit from electrostatic damage, and ensures the stability of the overall circuit.

[0054] In some embodiments, the current mirror module 2 includes: a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a fifth PMOS transistor MP4, a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, and a sixth NMOS transistor MN5.

[0055] The source of the first PMOS transistor MP0 is connected to the power supply VDD, the drain of the first PMOS transistor MP0 is connected to the source of the third PMOS transistor MP2, and the gate of the first PMOS transistor MP0 is connected to node N1.

[0056] The source of the second PMOS transistor MP1 is connected to the source of the first PMOS transistor MP0, the drain of the second PMOS transistor MP1 is connected to the source of the fourth PMOS transistor MP3, and the gate of the second PMOS transistor MP1 is connected to node N1.

[0057] The source of the third PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP0, the gate of the third PMOS transistor MP2 is connected to the gate of the fourth PMOS transistor MP4, and the drain of the third PMOS transistor MP2 is connected to the source of the fifth NMOS transistor MN4.

[0058] The source of the fourth PMOS transistor MP3 is connected to the second PMOS transistor MP1, and the gate of the fourth PMOS transistor MP3 is connected to the gate of the third PMOS transistor MP2.

[0059] The source of the fifth NMOS transistor MN4 is connected to the drain of the third PMOS transistor MP2, the drain of the fifth NMOS transistor MN4 is connected to the source of the fourth NMOS transistor MN3, and the gate of the fifth NMOS transistor MN4 is connected to a fixed potential.

[0060] The source of the second NMOS transistor MN1 is connected to the drain of the first NMOS transistor MN0, the drain of the second NMOS transistor MN1 is grounded, and the gate of the second NMOS transistor MN1 is connected to node N2.

[0061] The source of the third NMOS transistor MN2 is connected to the source of the first NMOS transistor MN0, the drain of the third NMOS transistor MN2 is grounded, and the gate of the third NMOS transistor MN2 is connected to node N2.

[0062] The source of the fourth NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN4, the drain of the fourth NMOS transistor MN3 is grounded, and the gate of the fourth NMOS transistor MN3 is connected to the source of the first NMOS transistor MN0.

[0063] The source of the first NMOS transistor MN0 is grounded, the drain of the first NMOS transistor MN0 is connected to the source of the second NMOS transistor MN1, and the gate of the first NMOS transistor MN0 is connected to the inverted signal rl_enn.

[0064] The drain of the sixth NMOS transistor MN5 is grounded, the source of the sixth NMOS transistor MN5 is connected to node N2, and the gate of the sixth NMOS transistor MN5 is connected to the inverted signal rl_enn.

[0065] The source of the fifth PMOS transistor MP4 is connected to the power supply VDD, the drain of the fifth PMOS transistor MP4 is connected to node N1, and the fifth PMOS transistor MP4 is connected to the rl_en signal.

[0066] Specifically, both the first PMOS transistor MP0 and the second PMOS transistor MP1 are PMOS transistors, with their sources connected to the power supply VDD and their gates connected to node N1. The first PMOS transistor MP0 and the second PMOS transistor MP1 are controlled by the potential of node N1 and are turned on when the potential of N1 is low. The first PMOS transistor MP0 and the second PMOS transistor MP1 provide power paths for the third PMOS transistor MP2 and the fourth PMOS transistor MP3, respectively, forming a common source and common gate structure to improve the power supply rejection ratio of the current mirror.

[0067] The gates of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are connected to form a current mirror pair. The source of the third PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP0, the drain of the third PMOS transistor MP2 is connected to the source of the fifth NMOS transistor MN4, and the source of the fourth PMOS transistor MP3 is connected to the drain of the second PMOS transistor MP1. The same gate voltage is used to achieve current mirroring, and they serve as current source devices for different branches.

[0068] The fifth PMOS transistor MP4 is a PMOS switch. The source of the fifth PMOS transistor MP4 is connected to the power supply VDD, the drain of the fifth PMOS transistor MP4 is connected to node N1, and the gate of the fifth PMOS transistor MP4 is connected to the rl_en signal. When the rl_en signal is low, it is turned on, pulling node N1 up to VDD to turn off the first PMOS transistor MP0 and the second PMOS transistor MP1. When the rl_en signal is high, it is turned off, so that the potential of node N1 is controlled by other circuits to turn on the first PMOS transistor MP0 and the second PMOS transistor MP1.

[0069] The first NMOS transistor MN0 is an NMOS switch, with its source grounded and its drain connected to the source of the second NMOS transistor MN1. The gate of the first NMOS transistor MN0 is connected to an inverted signal rl_enn. When the inverted signal rl_enn is high, it is turned on, providing a ground path for the second NMOS transistor MN1. When the inverted signal rl_enn is low, it is turned off to cut off the path. The gates of the second NMOS transistor MN1 and the third NMOS transistor MN2 are both connected to node N2. The source of the second NMOS transistor MN1 is connected to the drain of the first NMOS transistor MN0, and the drain of the second NMOS transistor MN1 is grounded. The drain of the third NMOS transistor MN2 is grounded. The second NMOS transistor MN1 and the third NMOS transistor MN2 are controlled by the potential of node N2 and serve as switching devices for current paths.

[0070] The gate of the fourth NMOS transistor MN3 is connected to the source of the first NMOS transistor MN0. The source of the fourth NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN4. The drain of the fourth NMOS transistor MN3 is grounded. The fixed potential of the gate of the fourth NMOS transistor MN3 enables the fourth NMOS transistor MN3 to operate in a constant current state, providing a stable grounding path for the mirror current ib1.

[0071] The gate of the fifth NMOS transistor MN4 is connected to a fixed potential. The source of the fifth NMOS transistor MN4 is connected to the drain of the third PMOS transistor MP2, and the drain of the fifth NMOS transistor MN4 is connected to the source of the fourth NMOS transistor MN3. The fifth NMOS transistor MN4, together with the third PMOS transistor MP2 and the fourth NMOS transistor MN3, forms an NMOS common-source common-gate structure, which improves the current replication accuracy of the current mirror.

[0072] The sixth NMOS transistor MN5 is an NMOS switch. The drain of the sixth NMOS transistor MN5 is grounded, the source of the sixth NMOS transistor MN5 is connected to node N2, and the gate of the sixth NMOS transistor MN5 is connected to the inverted signal rl_enn. When the inverted signal rl_enn is high, it is turned on, pulling node N2 down to ground to turn off the second NMOS transistor MN1 and the third NMOS transistor MN2. When the inverted signal rl_enn is low, it is turned off, so that the potential of node N2 is controlled by other circuits to turn on the second NMOS transistor MN1 and the third NMOS transistor MN2.

[0073] In some embodiments, such as Figure 3 As shown, the enable control timing generation module 1 includes a frequency divider 5. The input terminal of the frequency divider 5 is connected to the OSC_32 clock signal source, and the output terminal of the frequency divider 5 is connected to the input terminal of the enable control timing generation module 1.

[0074] Among them, frequency divider 5 divides the input OSC_32 clock signal to generate rl_en signal that meets the timing requirements of the circuit, and transmits rl_en signal to enable control timing generation module 1. Enable control timing generation module 1 generates inverted signal rl_enn based on rl_en signal, and then provides a time reference for coordinating the on and off of current mirror module 2 and comparator module 3. Finally, the low power consumption design goal is achieved through the intermittent operation of the control circuit.

[0075] In some embodiments, such as Figure 3 As shown, after the rl_en signal passes through frequency divider 5, the high level of the output rl_en signal lasts for 100μs, the period is 50ms, and the duty cycle is 0.2%.

[0076] Specifically, the high-level duration is 100μs, the signal period is 50ms, and the calculated duty cycle is 0.2%. The signal characteristics of short high-level and long low-level provide a precise timing reference for enabling the timing generation module 1 to generate the inverted signal rl_enn and coordinate the on / off control of the current mirror module 2 and comparator module 3. This ensures that the circuit only operates briefly during the 100μs high level of the rl_en signal to complete the load detection, while being in the off state during the remaining approximately 49.9ms low level period. This significantly reduces the operating time and achieves a substantial low-power effect.

[0077] In some embodiments, the ESD protection module 4 is a seventh NMOS transistor MN6. The source of the seventh NMOS transistor MN6 is connected to the load resistor RL, the drain of the seventh NMOS transistor MN6 is grounded, and the gate of the seventh NMOS transistor MN6 is connected to the drain of the seventh NMOS transistor MN6.

[0078] Specifically, the short-circuit connection between the gate and drain of the seventh NMOS transistor MN6 puts it in a specific bias state. When the chip output pin AT encounters electrostatic interference, the seventh NMOS transistor MN6 can quickly turn on and discharge the electrostatic current to ground, preventing electrostatic voltage from damaging the current mirror module 2 and comparator module 3 in the circuit. This achieves electrostatic protection for the entire low-power load detection circuit and ensures the stable operation of the circuit in an electrostatic environment.

[0079] In some embodiments, when the rl_en signal is high and the inverting signal rl_enn is low, the first NMOS transistor MN0 is turned on, the second NMOS transistor MN1, the third NMOS transistor MN2, the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 are turned on, the sixth NMOS transistor MN5 is turned off, the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are turned on, and the fifth PMOS transistor MP4 is turned off.

[0080] When the rl_en signal is low and the inverting signal rl_enn is high, the first NMOS transistor MN0 is off, the sixth NMOS transistor MN5 is on, the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 are off, the fifth PMOS transistor MP4 is on, and the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2, and the fourth PMOS transistor MP3 are off.

[0081] In the low-power load detection circuit, the switching state of each MOS transistor shows a clear correspondence with the level changes of the rl_en signal and the inverted signal rl_enn.

[0082] When the rl_en signal is high and the inverted signal rl_enn is low, the first NMOS transistor MN0 is turned on, and the second NMOS transistor MN1, the third NMOS transistor MN2, the fourth NMOS transistor MN3, and the fifth NMOS transistor MN4 are simultaneously turned on, while the sixth NMOS transistor MN5 is turned off. At the same time, the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2, and the fourth PMOS transistor MP3 are all turned on, while the fifth PMOS transistor MP4 is turned off. At this time, the current path of the current mirror module is complete, and the circuit enters the working state to perform load detection.

[0083] When the rl_en signal is low and the inverted signal rl_enn is high, the state is reversed. The first NMOS transistor MN0 is turned off, the sixth NMOS transistor MN5 is turned on, and the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 are all turned off. At the same time, the fifth PMOS transistor MP4 is turned on, and the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2, and the fourth PMOS transistor MP3 are all turned off. At this time, the current path of the current mirror module is interrupted, the circuit enters a low-power standby state, and the load detection operation is stopped.

[0084] In some embodiments, the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2, the fourth PMOS transistor MP3 and the fifth NMOS transistor MN4 constitute a common source and common gate structure.

[0085] Among them, the first PMOS transistor MP0 and the second PMOS transistor MP1 are connected in series to form a PMOS common source and common gate branch, the third PMOS transistor MP2 and the fourth PMOS transistor MP3 form current mirrors with the PMOS common source and common gate branch respectively, and the fifth NMOS transistor MN4 and the fourth NMOS transistor MN3 are connected in series to form an NMOS common source and common gate branch.

[0086] In this configuration, the first PMOS transistor MP0 serves as the common source and the second PMOS transistor MP1 serves as the common gate, which can significantly improve the output impedance of the branch and enhance the ability to suppress power supply voltage fluctuations.

[0087] The third PMOS transistor MP2 and the fourth PMOS transistor MP3 form current mirrors with the aforementioned PMOS common source and common gate branches, respectively. That is, by using the same gate bias voltage as the first PMOS transistor MP0 and the second PMOS transistor MP1, they replicate the magnitude of the reference current to ensure the proportional stability of the current in each branch.

[0088] Meanwhile, the fifth NMOS transistor MN4 and the fourth NMOS transistor MN3 are connected in series to form an NMOS common-source common-gate branch. The fifth NMOS transistor MN4 serves as the common gate and the fourth NMOS transistor MN3 serves as the common source. The NMOS common-source common-gate branch works in conjunction with the PMOS common-source common-gate branch to further improve the output impedance and current replication accuracy of the entire current mirror module, reduce the influence of factors such as channel length modulation effect on the mirror current ib1, and ensure the stability of the load detection current.

[0089] In some embodiments, one end of the load resistor RL is connected to the chip output pin AT, and the other end of the load resistor RL is grounded.

[0090] When the load resistor RL is connected, the mirror current ib1 output by the current mirror module 2 flows through the fourth PMOS transistor MP3, the fifth NMOS transistor MN4, the fourth NMOS transistor MN3, the first fixed resistor R0, the second fixed resistor R1, the load resistor RL to the ground terminal, forming a detection voltage VAT at the chip output pin AT;

[0091] When the load resistor RL is not connected, the mirror current ib1 flows through the fourth PMOS transistor MP3, the fifth NMOS transistor MN4, the fourth NMOS transistor MN3, the first fixed resistor R0, the second fixed resistor R1, and then to ground. The detected voltage VAT is the product of the resistance of the first fixed resistor R0 and the second fixed resistor R1 and the mirror current ib1.

[0092] The load resistor RL is connected with one end connected to the chip output pin AT and the other end grounded. When the load resistor RL is connected, the mirror current ib1 output by the current mirror module 2 will pass through the fourth PMOS transistor MP3, the fifth NMOS transistor MN4, the fourth NMOS transistor MN3, the first fixed resistor R0, the second fixed resistor R1, and the load resistor RL, and finally flow into the ground terminal. During this process, the mirror current ib1 generates a voltage drop in the series circuit of the load resistor RL and the first fixed resistor R0, and the mirror current ib1 generates a voltage drop in the series circuit of the second fixed resistor R1 and the first fixed resistor R0, thereby forming a detection voltage VAT at the chip output pin AT that reflects the load connection status.

[0093] When the load resistor RL is not connected, the flow path of the mirror current ib1 is grounded after passing through the fourth PMOS transistor MP3, the fifth NMOS transistor MN4, the fourth NMOS transistor MN3, the first fixed resistor R0, and the second fixed resistor R1. At this time, the detection voltage VAT is determined only by the product of the first fixed resistor R0, the second fixed resistor R1 and the mirror current ib1, and its magnitude is equal to the voltage drop generated when the mirror current ib1 flows through the first fixed resistor R0 and the second fixed resistor R1.

[0094] In some embodiments, the ratio of the output current of the second NMOS transistor MN1, the output current of the third NMOS transistor MN2, and the output current of the fourth NMOS transistor MN3 is 1:2:m. The ratio of the output current of the first PMOS transistor MP0 to the output current of the second PMOS transistor MP1 is 1:k.

[0095] The ratio of the output current of the second NMOS transistor MN1, the output current of the third NMOS transistor MN2, and the output current of the fourth NMOS transistor MN3 is 1:2:m. This 1:2:m ratio is achieved through the design of the device dimensions to ensure that the output current of the three transistors is distributed in a fixed proportion under the same bias conditions, so as to adapt to the current requirements of different branches.

[0096] Meanwhile, the ratio of the output current of the first PMOS transistor MP0 to the output current of the second PMOS transistor MP1 is 1:k. This 1:k ratio is also based on the device structure design, which enables the two transistors to provide proportionally distributed current in the common source and common gate branch. Together with the current ratio of the NMOS transistor, this ensures that the current mirror module accurately replicates and distributes the current, providing a stable current basis for the accuracy of load detection and the low power consumption characteristics of the circuit.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A low-power load detection circuit, characterized in that, include: Enable control timing generation module (1), current mirror module (2), comparator module (3), ESD protection module (4); The input terminal of the enable control timing generation module (1) is connected to the OSC_32 clock signal source, and the output terminal of the enable control timing generation module (1) is connected to the current mirror module (2) and the comparator module (3) respectively. It is used to generate the rl_en signal and the inverted signal rl_enn based on the input signal of the OSC_32 clock signal source, and transmit the rl_en signal and the inverted signal rl_enn to the current mirror module (2) and the comparator module (3) respectively. The power supply terminal of the current mirror module (2) is connected to the power supply (VDD), the ground terminal of the current mirror module (2) is grounded, the input terminal of the current mirror module (2) is connected to the reference current ib, and the output terminal of the current mirror module (2) is connected to the load resistor (RL) and the second fixed resistor (R1) through the first fixed resistor (R0) respectively. It is used to conduct when the rl_en signal is high level and the inverted signal rl_enn is low level. Based on the reference current ib, a mirror current ib1 is generated and transmitted to the load resistor (RL) and the second fixed resistor (R1) through the first fixed resistor (R0). The mirror current ib1 flows through the first fixed resistor (R0), the second fixed resistor (R1) and the load resistor (RL) to form a detection voltage VAT at the input terminal of the load resistor (RL). The first input terminal of the comparator module (3) is connected to the output terminal of the current mirror module (2) and is used to input the detection voltage VAT. The second input terminal of the comparator module (3) is connected to the mirror current ib1. The output terminal of the comparator module (3) is used to output the detection result signal out. When the rl_en signal is high, it is turned on and compares the magnitude of the detection voltage VAT with the reference voltage vref. One end of the ESD protection module (4) is connected to the chip output pin (AT) corresponding to the access end of the load resistor (RL), and the other end of the ESD protection module (4) is grounded.

2. The low-power load detection circuit according to claim 1, characterized in that, The current mirror module (2) includes: a first PMOS transistor (MP0), a second PMOS transistor (MP1), a third PMOS transistor (MP2), a fourth PMOS transistor (MP3), a fifth PMOS transistor (MP4), a first NMOS transistor (MN0), a second NMOS transistor (MN1), a third NMOS transistor (MN2), a fourth NMOS transistor (MN3), a fifth NMOS transistor (MN4), and a sixth NMOS transistor (MN5); The source of the first PMOS transistor (MP0) is connected to the power supply (VDD), the drain of the first PMOS transistor (MP0) is connected to the source of the third PMOS transistor (MP2), and the gate of the first PMOS transistor (MP0) is connected to node N1. The source of the second PMOS transistor (MP1) is connected to the source of the first PMOS transistor (MP0), the drain of the second PMOS transistor (MP1) is connected to the source of the fourth PMOS transistor (MP3), and the gate of the second PMOS transistor (MP1) is connected to node N1. The source of the third PMOS transistor (MP2) is connected to the drain of the first PMOS transistor (MP0), the gate of the third PMOS transistor (MP2) is connected to the gate of the fourth PMOS transistor (MP3), and the drain of the third PMOS transistor (MP2) is connected to the source of the fifth NMOS transistor (MN4). The source of the fourth PMOS transistor (MP3) is connected to the second PMOS transistor (MP1), and the gate of the fourth PMOS transistor (MP3) is connected to the gate of the third PMOS transistor (MP2). The source of the fifth NMOS transistor (MN4) is connected to the drain of the third PMOS transistor (MP2), the drain of the fifth NMOS transistor (MN4) is connected to the source of the fourth NMOS transistor (MN3), and the gate of the fifth NMOS transistor (MN4) is connected to a fixed potential. The source of the second NMOS transistor (MN1) is connected to the drain of the first NMOS transistor (MN0), the drain of the second NMOS transistor (MN1) is grounded, and the gate of the second NMOS transistor (MN1) is connected to node N2. The source of the third NMOS transistor (MN2) is connected to the source of the first NMOS transistor (MN0), the drain of the third NMOS transistor (MN2) is grounded, and the gate of the third NMOS transistor (MN2) is connected to node N2. The source of the fourth NMOS transistor (MN3) is connected to the drain of the fifth NMOS transistor (MN4), the drain of the fourth NMOS transistor (MN3) is grounded, and the gate of the fourth NMOS transistor (MN3) is connected to the source of the first NMOS transistor (MN0). The source of the first NMOS transistor (MN0) is grounded, the drain of the first NMOS transistor (MN0) is connected to the source of the second NMOS transistor (MN1), and the gate of the first NMOS transistor (MN0) is connected to the inverted signal rl_enn. The drain of the sixth NMOS transistor (MN5) is grounded, the source of the sixth NMOS transistor (MN5) is connected to node N2, and the gate of the sixth NMOS transistor (MN5) is connected to the inverted signal rl_enn. The source of the fifth PMOS transistor (MP4) is connected to the power supply (VDD), the drain of the fifth PMOS transistor (MP4) is connected to node N1, and the fifth PMOS transistor (MP4) is connected to the rl_en signal.

3. The low-power load detection circuit according to claim 1 or 2, characterized in that, The enable control timing generation module (1) includes a frequency divider (5), the input of which is connected to the OSC_32 clock signal source, and the output of which is connected to the input of the enable control timing generation module (1).

4. The low-power load detection circuit according to claim 3, characterized in that, After the input signal passes through the frequency divider (5), the high level of the output rl_en signal lasts for 100μs, with a period of 50ms and a duty cycle of 0.2%.

5. The low-power load detection circuit according to claim 2, characterized in that, The ESD protection module (4) is a seventh NMOS transistor (MN6). The source of the seventh NMOS transistor (MN6) is connected to the load resistor (RL), the drain of the seventh NMOS transistor (MN6) is grounded, and the gate of the seventh NMOS transistor (MN6) is connected to the drain of the seventh NMOS transistor (MN6).

6. The low-power load detection circuit according to claim 2, characterized in that, When the rl_en signal is high and the inverting signal rl_enn is low, the first NMOS transistor (MN0)... When the first NMOS transistor (MP0), the second NMOS transistor (MN1), the third NMOS transistor (MN2), the fourth NMOS transistor (MN3), and the fifth NMOS transistor (MN4) are turned on, the sixth NMOS transistor (MN5) is turned off, the first PMOS transistor (MP0), the second PMOS transistor (MP1), the third PMOS transistor (MP2), and the fourth PMOS transistor (MP3) are turned on, and the fifth PMOS transistor (MP4) is turned off. When the rl_en signal is low and the inverting signal rl_enn is high, the first NMOS transistor (MN0) is off, the sixth NMOS transistor (MN5) is on, the second NMOS transistor (MN1), the third NMOS transistor (MN2), and the fourth NMOS transistor (MN3) are off, the fifth PMOS transistor (MP4) is on, and the first PMOS transistor (MP0), the second PMOS transistor (MP1), the third PMOS transistor (MP2), and the fourth PMOS transistor (MP3) are off.

7. The low-power load detection circuit according to claim 2, characterized in that, The first PMOS transistor (MP0), the second PMOS transistor (MP1), the third PMOS transistor (MP2), the fourth PMOS transistor (MP3), and the fifth NMOS transistor (MN4) form a common source and common gate structure; In this circuit, the first PMOS transistor (MP0) and the second PMOS transistor (MP1) are connected in series to form a PMOS common source and common gate branch. The third PMOS transistor (MP2) and the fourth PMOS transistor (MP3) form current mirrors with the PMOS common source and common gate branch respectively. The fifth NMOS transistor (MN4) and the fourth NMOS transistor (MN3) are connected in series to form an NMOS common source and common gate branch.

8. The low-power load detection circuit according to claim 2, characterized in that, One end of the load resistor (RL) is connected to the chip output pin (AT), and the other end of the load resistor (RL) is grounded; When the load resistor (RL) is connected, the mirror current ib1 output by the current mirror module (2) flows through the fourth PMOS transistor (MP3), the fifth NMOS transistor (MN4), the fourth NMOS transistor (MN3), the first fixed resistor (R0), the second fixed resistor (R1), and the load resistor (RL) to the ground terminal, forming a detection voltage VAT at the chip output pin (AT); When the load resistor (RL) is not connected, the mirror current ib1 flows through the fourth PMOS transistor (MP3), the fifth NMOS transistor (MN4), the fourth NMOS transistor (MN3), the first fixed resistor (R0), and the second fixed resistor (R1) before being grounded. The detected voltage VAT is the product of the sum of the first fixed resistor (R0) and the second fixed resistor (R1) and the mirror current ib1.

9. The low-power load detection circuit according to claim 2, characterized in that, The ratio of the output current of the second NMOS transistor (MN1), the output current of the third NMOS transistor (MN2), and the output current of the fourth NMOS transistor (MN3) is 1:2:m.

10. The low-power load detection circuit according to claim 2, characterized in that, The ratio of the output current of the first PMOS transistor (MP0) to the output current of the second PMOS transistor (MP1) is 1:k.

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