Photonic package structure

Abstract

The application discloses a photonic packaging structure, which comprises an electronic integrated circuit having a first cavity; a first circuit layer arranged below the electronic integrated circuit; and a photonic integrated circuit arranged in the first cavity, wherein the length direction of the photonic integrated circuit is perpendicular to the length direction of the electronic integrated circuit, and the photonic integrated circuit is electrically connected with the first circuit layer. The technical scheme at least provides a photonic packaging structure meeting the requirements of miniaturization and low cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a photonic packaging structure. Background Technology

[0002] See Figure 1 As shown, in the current photonic packaging structure 10 (e.g., a silicon photonic packaging structure), a PIC (Photonic Integrated Circuit) 12 and an EIC (Electronic Integrated Circuit) 14 are bonded to a substrate 18. Improved performance (e.g., efficiency) and versatility are desired; however, this comes at the cost of lower yield. To meet the demands for improved performance and versatility, larger package structures and substrate sizes are required. Furthermore, single-chip types of PICs and EICs are also necessary. Therefore, cost and complexity are increasing. The lower yield is due to variations between individual chips. The high cost is partly due to, for example, the increasingly larger required substrate size. Utility Model Content

[0003] To address the above issues, this application proposes a photonic packaging structure, providing a solution that meets the requirements of miniaturization and lower cost.

[0004] According to one aspect of this application, a photonic packaging structure is provided, comprising: an electronic integrated circuit having a first cavity; a first circuit layer disposed below the electronic integrated circuit; and a photonic integrated circuit disposed within the first cavity, wherein the length direction of the photonic integrated circuit is perpendicular to the length direction of the electronic integrated circuit, and the photonic integrated circuit is electrically connected to the first circuit layer.

[0005] In some embodiments, the photonic packaging structure further includes a second circuit layer, wherein the photonic integrated circuit has a first surface parallel to its length direction and a side surface connected to the first surface and facing the first circuit layer, and the second circuit layer is disposed on the first surface and the side surface of the photonic integrated circuit.

[0006] In some embodiments, the second circuit layer defines the second cavity.

[0007] In some embodiments, the photonic packaging structure further includes an optical transceiver element disposed within the second cavity.

[0008] In some embodiments, the optical transceiver element receives and transmits light signals, wherein the light signals are transmitted to the optical transceiver element in a direction perpendicular to a first surface of the photonic integrated circuit.

[0009] In some embodiments, the optical transceiver extends beyond the electronic integrated circuit along the length of the photonic integrated circuit.

[0010] In some embodiments, the second circuit layer includes a conductive via extending perpendicular to the first surface of the photonic integrated circuit and disposed on the side surface of the photonic integrated circuit, the conductive via being electrically connected to the first circuit layer.

[0011] According to another aspect of this application, a photonic packaging structure is provided, comprising: an electronic integrated circuit having a first cavity; a first circuit layer disposed below the electronic integrated circuit; a photonic integrated circuit disposed within the first cavity, wherein the length direction of the photonic integrated circuit is perpendicular to the length direction of the electronic integrated circuit; and a second circuit layer disposed on the side surface of the photonic integrated circuit facing the first circuit layer and electrically connected to the first circuit layer.

[0012] In some embodiments, the photonic packaging structure further includes an optical transceiver element disposed on the photonic integrated circuit, and the optical transceiver element extends beyond the electronic integrated circuit along the length direction of the photonic integrated circuit.

[0013] In some embodiments, the photonic integrated circuit has a first surface parallel to its length direction, wherein a second circuit layer is further disposed on the first surface of the photonic integrated circuit, exposing optical transceiver elements and connected to the electrical connection terminals of the photonic integrated circuit.

[0014] The above-described technical solution, by arranging the photonic integrated circuit and the electronic integrated circuit perpendicularly within the first cavity of the electronic integrated circuit, reduces the lateral component space in the photonic packaging structure, which is beneficial for cost savings and further miniaturization of the packaging structure. Furthermore, high-density wiring can be achieved by electrically connecting the first wiring layer located below the photonic integrated circuit to it. Therefore, a solution that meets the requirements of miniaturization and lower cost is provided. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a cross-sectional schematic diagram of an existing photonic packaging structure.

[0017] Figure 2 This is a cross-sectional schematic diagram of a photonic packaging structure according to an embodiment of this application.

[0018] Figures 3A to 3S This is a cross-sectional schematic diagram of multiple stages in forming a PIC component with a photonic packaging structure according to an embodiment of this application.

[0019] Figures 4A to 4P This is a cross-sectional schematic diagram of multiple stages of forming a photonic packaging structure according to an embodiment of this application using pre-formed PIC components.

[0020] Figure 5 This is a cross-sectional schematic diagram of a photonic packaging structure according to another embodiment of this application.

[0021] Figure 6 This is a cross-sectional schematic diagram of a photonic packaging structure according to another embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] An embodiment of this application provides a photonic packaging structure 100. Figure 2 This is a cross-sectional schematic diagram of the photonic packaging structure 100 according to an embodiment of this application. See also... Figure 2As shown, the photonic packaging structure 100 may include an EIC 120, a first circuit layer 140, and a PIC 150. The first circuit layer 140 is disposed below the EIC 120. The EIC 120 may be electrically connected to the first circuit layer 140. The first circuit layer 140 may be an RDL (Redistribution Layer). The EIC 120 has a first cavity 125. The PIC 150 is disposed within the first cavity 125. The PIC 150 and the EIC 120 are arranged perpendicularly to each other. "Perpendicularly to each other" means that the length direction of the PIC 150 is perpendicular to the length direction of the EIC 120. Figure 2 In this configuration, the length direction of PIC 150 is along direction X, and the length direction of EIC 120 is along direction Z. Furthermore, PIC 150 is electrically connected to the first line layer 140.

[0026] By arranging the PIC 150 and EIC 120 perpendicularly within the first cavity 125 of the EIC 120, the lateral component space in the photonic packaging structure can be reduced, which is beneficial for cost savings and further miniaturization of the packaging structure. Furthermore, high-density wiring can be achieved by electrically connecting the first wiring layer 140 located below the EIC 120 to the PIC 150. Therefore, a solution that meets the requirements of miniaturization and lower cost is provided. The photonic packaging structure 100 can be a chip-level packaging structure.

[0027] PIC 150 has a first surface 150a parallel to its direction X, and a side surface 150s connected to the first surface 150a and facing the first circuit layer 140. The photonic packaging structure 100 may further include a second circuit layer 160. The second circuit layer 160 is disposed on the first surface 150a and the side surface 150s of PIC 150, that is, the second circuit layer 160 is disposed on one side of and along the first surface 150a of PIC 150, and below and along the side surface 150s. An adhesive layer 192 may fill the first cavity 125 and connect PIC 150 to the first circuit layer 140. The material of the adhesive layer 192 may be an underfill. The adhesive layer 192 can be used to protect the circuit layers and connection terminals within the first cavity 125, and can also be used to vertically position PIC 150 during manufacturing.

[0028] The EIC 120 may also include a heat sink 195 disposed on the side of the EIC 120 facing away from the first circuit layer 140. The EIC 120 with the heat sink 195 faces the environment with its back side up, thereby enhancing and improving heat dissipation in the package structure.

[0029] The second circuit layer 160 may define a second cavity 165. In some embodiments, the second cavity 165 may be filled with air. A light receiving element 131 and a light transmitting element 132 are disposed within the second cavity 165. The light receiving element 131 and the light transmitting element 132 may be located on a first surface 150a of the PIC 150 and exposed by the second cavity 165. The light receiving element 131 may be, for example, an optical sensor, and the light transmitting element 132 may be, for example, an LED (Light Emitting Diode).

[0030] Optical receiving element 131 and optical transmitting element 132 can be collectively referred to as optical transceivers, and they are used together to receive and transmit optical signal S1. The second cavity 165 provides optical path space for optical receiving element 131 and optical transmitting element 132. Optical signal S1 can be transmitted to optical receiving element 131 through the second cavity 165 in a direction perpendicular to the first surface 150a of PIC 150. Optical transmitting element 132 can transmit optical signal S1 through the second cavity 165 in a direction perpendicular to the first surface 150a of PIC 150.

[0031] In some embodiments, the PIC 150 may protrude beyond the EIC 120 along its length direction (i.e., direction X). Along the length direction of the PIC 150 (i.e., direction X), the optical transceiver extends beyond the EIC 120, such that the optical receiver 131 and the optical transmitter 132 can receive and transmit the light signal S1 in a direction perpendicular to the first surface 150a of the PIC 150. In this way, the linearly propagating optical signal can pass through the space above the back surface of the EIC 120, forming the shortest path for optical signal transmission. Furthermore, the reflector design can be omitted in the package structure.

[0032] The photonic packaging structure 100 may further include a molding layer 180 disposed on a second surface 150b of the PIC 150 opposite to the first surface 150a. The molding layer 180 may also cover the side surfaces 150s of the PIC 150. The material of the molding layer 180 may be a molding compound. The molding layer 180 provides sufficient area for fabricating the second circuit layer 160 and the second cavity 165 defined by the second circuit layer 160.

[0033] The first circuit layer 140 may include at least one dielectric layer 142. Figure 2The diagram shows three stacked dielectric layers 142. The first wiring layer 140 may further include conductive lines disposed in the dielectric layers 142, the conductive lines including conductive vias 144 extending in the Z direction and laterally extending conductive lines 146. The conductive vias 144 can electrically connect conductive lines 146 at different levels. The EIC 120 can be electrically connected to the corresponding conductive vias 144 through its pads 122. The conductive vias 144 located below the first cavity 125 can pass through the uppermost dielectric layer 142 and be electrically connected to the second wiring layer 160. In some embodiments, the first wiring layer 140, which can use fine lines, can be connected to the EIC 120 to improve I / O density. In some embodiments, the line width of the conductive lines in the first wiring layer 140 can be in the range of 1 μm to 10 μm, and the line spacing can be in the range of 1 μm to 10 μm.

[0034] The second wiring layer 160 may be an RDL. The second wiring layer 160 may include at least one dielectric layer 162, and conductive lines 166 and conductive vias 164 disposed on the dielectric layer 162. The conductive lines 166 extend parallel to the first surface 150a of the PIC 150 and are electrically connected to the first wiring layer 140; for example, the conductive lines 166 may be connected to the conductive vias 144 of the first wiring layer 140. In some embodiments, a conductive via 164 extending perpendicular to the first surface 150a of the PIC 150 may be disposed on the side of the second wiring layer 160 facing the first wiring layer 140, and this conductive via 164 may be connected to the conductive via 144 of the first wiring layer 140.

[0035] Furthermore, a portion of the second wiring layer 160 may extend through the molding layer 180 in a direction perpendicular to the upper surface of the PIC 150. Specifically, the second wiring layer 160 may also include a conductive via 1642 extending perpendicular to the first surface 150a of the PIC 150 and disposed on the side surface 150s of the PIC 150. The conductive via 1642 may extend through the molding layer 180 in a direction perpendicular to the upper surface of the PIC 150. The conductive via 1642 is electrically connected to the first wiring layer 140. The conductive via 1642 may connect to the conductive via 144 of the first wiring layer 140 below it. In some embodiments, the line width of the conductive lines in the second wiring layer 160 may be in the range of 1 μm to 10 μm, and the line spacing may be in the range of 1 μm to 10 μm. By fabricating a second wiring layer 160 with fine lines on the surface of the PIC 150, I / O density can be increased and better electrical performance can be obtained. Furthermore, by electrically connecting PIC 150 and EIC 120 through the first circuit layer 140 and the second circuit layer 160, the large-area substrate used in the prior art can be omitted.

[0036] Figures 3A to 3SThis is a cross-sectional schematic diagram showing multiple stages of forming a PIC component with a photonic packaging structure according to an embodiment of this application. See also... Figure 3A As shown, a carrier plate 302 is provided, and a release layer 304 is provided on the carrier plate 302. See also Figure 3B As shown, multiple PICs 150 are bonded to the carrier board 302. Each PIC 150 has multiple pads 150p on its first surface 150a as electrical connection terminals for the PIC 150, and also has a light receiving element 131 and a light transmitting element 132.

[0037] See Figure 3C As shown, a molding layer 180 is formed above the carrier board 302. The molding layer 180 covers multiple PICs 150 and multiple pads 150p on their first surface 150a, as well as the light receiving element 131 and the light transmitting element 132. Then, multiple through holes 182 are formed in the molding layer 180 through a drilling process 312, such as... Figure 3D As shown, the perforations 182 extend through the molding layer 180 along the side surface 150s of the PIC 150. A seed layer 160s1 is formed above the molding layer 180 and within the perforations 182. The seed layer 160s1 can be formed by, for example, a PVD (Physical Vapor Deposition) process.

[0038] See Figure 3E As shown, a mask 322 is formed above the seed layer 160s1 and within multiple vias 182. The mask 322 can be a photomask. Then, the mask 322 is patterned using a photolithography process 314, see [reference needed]. Figure 3F As shown, openings 184 exposing multiple through-holes 182 are formed in mask 322. Metal material is filled into the through-holes 182 and openings 184, for example, through an electroplating process, forming conductive vias 1642 and pads 1642p composed of a seed layer 160s1 and the metal material. The multiple conductive vias 1642 pass through the molding layer 180, and the pads 1642p connect to the conductive vias 1642 and are located above the molding layer 180. Subsequently, mask 322 and the seed layer 160s1 beneath it are removed by an etching process. See [reference needed]. Figure 3G As shown. See also Figure 3H As shown, the carrier plate 302 is removed by detaching the release layer 304.

[0039] Then, Figure 3H The obtained structure is inverted, and a mask 324 is formed above the first surface 150a of the PIC 150, see [reference]. Figure 3I As shown. The mask 324 is patterned using photolithography process 316, see [reference]. Figure 3J As shown, a mask 324 is retained above the optical receiving element 131 and the optical transmitting element 132. See also Figure 3K As shown, a dielectric layer 162 is formed on the area exposed by mask 324. A photolithography process is then performed. See [link to relevant documentation]. Figure 3L As shown, a plurality of openings 362 are formed in the dielectric layer 162 above a plurality of pads 150p. A seed layer 160s2 is formed above the dielectric layer 162 and the mask 324 and in the plurality of openings 362.

[0040] See Figure 3M As shown, a mask 326 is formed above the seed layer 160s2. Then, photolithography process 331 is performed on the mask 326. See [link / reference] Figure 3N Multiple openings 364 are formed in the mask 326 through photolithography process 331, exposing a portion of the seed layer 160s2 above the dielectric layer 162. Metal material is then filled into the openings 364 to form conductive vias 1641 and conductive lines 166, which are composed of the seed layer 160s2 and the metal material. The conductive vias 1641 pass through the dielectric layer 162, and the conductive lines 166 extend laterally on the dielectric layer 162. Subsequently, the mask 326 and the seed layer 160s2 beneath it are removed by etching process. See [link to previous section]. Figure 3O As shown, a conductive via 1641 and a conductive line 166 are formed.

[0041] Then, the steps of forming dielectric layer 162, conductive via 1641, and conductive line 166 can be repeated, see below. Figure 3P As shown, multiple dielectric layers 162 are formed above the PIC 150 and the molding layer 180. Figure 3P It consists of two dielectric layers 162, a conductive via 1641, and a conductive line 166. See then... Figure 3Q As shown, etching process 333 is performed to remove mask 324. After removing mask 324, as... Figure 3R As shown, a second cavity 165 is formed, which exposes the light receiving element 131 and the light transmitting element 132 below the mask 324.

[0042] See Figure 3R As shown, a cutting process 335 is performed to separate multiple PICs 150. The cutting process 335 can be performed along the conductive vias 1642 between the PICs 150, and as... Figure 3S As shown, the cutting process 335 can remove a portion (e.g., half) of the conductive via 1642 and a portion of the pad 1642p, such that the surface of the conductive via 1642 facing away from the PIC 150 extends vertically. This forms a second circuit layer 160 disposed on the first surface 150a and side surface 150s of the PIC 150, defining a second cavity 165.

[0043] Figures 4A to 4PThis is a cross-sectional schematic diagram showing multiple stages of forming a photonic packaging structure according to an embodiment of this application using pre-formed PIC components. See also... Figure 4A As shown, a carrier substrate 402 is provided, on which a release layer 404 is provided. The manufacturing process can be a wafer-level process or a panel-level process. The following description illustrates one unit of either a wafer-level or panel-level process. See also Figure 4B As shown, the EIC 120 is bonded to the carrier board 402. The surface of the EIC 120 with pads 122 faces the carrier board 402, and the pads 122 serve as electrical connection terminals for the EIC 120. See then... Figure 4C As shown, a heat dissipation layer 195 is formed on the back side of the EIC 120. The heat dissipation layer 195 can be formed, for example, by a PVD process. The heat dissipation layer 195 can be a metal layer.

[0044] See Figure 4D As shown, a mask 422 is formed on the heat dissipation layer 195. Then, the mask 422 is patterned using a photolithography process 441, see [reference needed]. Figure 4E As shown, multiple openings 423 are formed in the mask 422 to expose the heat dissipation layer 195. After forming the openings 423, an etching process 443 is performed through the heat dissipation layer 195 and the EIC 120 to form a first cavity 125 in the EIC 120, as shown. Figure 4F As shown.

[0045] See Figure 4G As shown, the above are provided Figures 3A to 3S The obtained structure involves placing the PIC 150 with the second circuit layer 160 into the first cavity 125. After placing the PIC 150 into the first cavity 125, see [link to documentation]. Figure 4H As shown, an adhesive layer 192 is formed in the first cavity 125 to connect the PIC 150 to the first circuit layer 140 and fix the PIC 150 in the first cavity 125.

[0046] See Figure 4I As shown, the release layer 404 is separated from the EIC 120 to remove the carrier plate 402. Then, Figure 4I The resulting structure is inverted, such as Figure 4J As shown. A dielectric layer 142 is formed on the EIC 120, covering multiple pads 122 of the EIC 120. The dielectric layer 142 is patterned using a photolithography process 445, see [reference needed]. Figure 4K As shown, a plurality of openings 143 are formed in the dielectric layer 142 to expose the pads 122. A seed layer 140s is formed above the dielectric layer 142 and in the openings 143.

[0047] See Figure 4LAs shown, mask 424 is formed above seed layer 140s. Photolithography process 447 is performed to pattern mask 424, see [link to diagram]. Figure 4M As shown, multiple openings 425 are formed in the mask 424 to expose the seed layer 140s. Metal material is then filled into the openings 425 to form conductive vias 144 and conductive lines 146, which are composed of the seed layer 140s and the metal material. The conductive lines 146 are located above the dielectric layer 142. Some conductive vias 144 can be connected to the pads 122 of the EIC 120. Other conductive vias 144 can be connected to corresponding conductive vias 1642, 1641, and conductive lines 166 of the second circuit layer 160. Then the mask 424 is removed, as shown... Figure 4N As shown.

[0048] Then, the steps of forming dielectric layer 142, conductive via 144, and conductive line 146 can be repeated, see below. Figure 4O As shown, multiple dielectric layers 142 are formed above EIC 120. Figure 4O The first circuit layer 140 consists of three dielectric layers 142, conductive vias 144, and conductive lines 146. Bumps 198 or solder balls are connected to the first circuit layer 140. The materials for the bumps 198 or solder balls can be solder, ACP (Anisotropic Conductive Paste), or ACF (Anisotropic Conductive Film).

[0049] Will Figure 4O The resulting structure is inverted; see [link / reference]. Figure 4P As shown, a dicing process can then be performed along the dotted lines to separate multiple EICs 120 in the wafer-level process or panel-level process, forming a photonic packaging structure 100.

[0050] The above references Figures 3A to 4PIn the described manufacturing process, during the processing of each PIC 150, a second circuit layer 160 is fabricated on the surface of the PIC 150 by photolithography. Conductive vias 1641 and 1642 for electrical connection are formed at the edges of each PIC 150. These conductive vias 1641 and 1642 are obtained by cutting the originally formed conductive vias. A second cavity 165 is fabricated within the second circuit layer 160 for optical signal transmission between the light receiving element 131 and the light transmitting element 132, with the optical signal transmitted on the back side of the EIC 120. The EIC 120 is placed on a carrier 402, and a heat dissipation layer 195 is fabricated on its back side. Next, a portion of the heat dissipation layer 195 is removed by photolithography. Then, a first cavity 125 is formed through the EIC 120. Finally, the PIC 150 with the second circuit layer 160 formed is embedded in the first cavity 125. An adhesive layer 192 is filled in the first cavity 125 to secure the full-length PIC 150 within the first cavity 125, thereby forming the final photonic packaging structure 100.

[0051] In some embodiments, the dimension of EIC 120 in direction X can be in the range of 1 mm to 1000 mm. The thickness T1 of EIC 120 can be in the range of 50 μm to 500 μm. The dimension of PIC 150 in direction Z can be in the range of 10 μm to 10 mm. The thickness T2 of PIC 150 can be in the range of 10 μm to 100 μm. The total thickness T3 of PIC 150, molding layer 180, and second circuit layer 160 can be in the range of 50 μm to 200 μm. The width W1 of the second cavity 165 can be in the range of 5 μm to 100 μm. The distance D1 of the second cavity 165 extending beyond EIC 120 in direction Z can be in the range of 5 μm to 100 μm.

[0052] The top opening width W2 of the first cavity 125 can be in the range of 100 μm to 500 μm. The bottom opening width W3 of the first cavity 125 can be in the range of 60 μm to 300 μm. Wherein, W2 > W3 > T3. The thickness of each dielectric layer 142 of the first circuit layer 140 in the Z direction can be in the range of 5 μm to 20 μm.

[0053] In some embodiments, the materials of dielectric layer 162, dielectric layer 142, adhesive layer 192, and molding layer 180 may be any one of the following: PI (polyimide), epoxy resin, ABF, PP (polypropylene), acrylic acid, organic photosensitive liquid, organic non-photosensitive liquid, organic photosensitive dry film material, and organic non-photosensitive dry film material. In some embodiments, the seed layer and / or metal material of the conductive lines in the first circuit layer 140 and the second circuit layer 160 may be any one of the following: Cu, Au, Ag, Al, Pd, Pt, Ni, or alloys thereof. In some embodiments, the seed layer and / or metal material of the conductive lines in the first circuit layer 140 and the second circuit layer 160 may be formed using processes such as PVD, electroplating, electroless plating, printing, and metal potting.

[0054] Figure 5 This is a cross-sectional schematic diagram of a photonic packaging structure 200 according to another embodiment of this application. See also Figure 5 As shown, in this embodiment, two first cavities 125 are formed in an EIC 120, and each first cavity 125 is respectively provided with a PIC 150 having a second line layer 160 and a molding layer 180. The second cavities 165 defined by the second line layers 160 on the two PICs 150 are arranged opposite to each other to facilitate the transmission and reception of optical signals.

[0055] Figure 6 This is a cross-sectional schematic diagram of a photonic packaging structure 300 according to another embodiment of this application. See also... Figure 6 As shown, in this embodiment, an EIC 120 forms a first cavity 125, and two PICs 150, each with a second circuit layer 160 and a molding layer 180, are disposed within the first cavity 125. The second cavities 165 defined by the second circuit layers 160 on the two PICs 150 are disposed opposite to each other to facilitate the transmission and reception of optical signals.

[0056] It should be understood that Figure 5 and Figure 6 Other aspects of the photonic packaging structures 200 and 300 shown can be compared with those in the above references. Figures 2 to 4P The descriptions are similar, so they will not be repeated here.

[0057] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A photonic packaging structure, characterized in that, include: An electronic integrated circuit has a first cavity; The first circuit layer is disposed below the electronic integrated circuit; as well as A photonic integrated circuit is disposed within the first cavity, and the length direction of the photonic integrated circuit is perpendicular to the length direction of the electronic integrated circuit. The photonic integrated circuit is electrically connected to the first circuit layer.

2. The photonic packaging structure according to claim 1, characterized in that, Also includes: The second circuit layer is provided, wherein the photonic integrated circuit has a first surface parallel to its length direction and a side surface connected to the first surface and facing the first circuit layer, and the second circuit layer is disposed on the first surface and the side surface of the photonic integrated circuit.

3. The photonic packaging structure according to claim 2, characterized in that, The second circuit layer defines the second cavity.

4. The photonic packaging structure according to claim 3, characterized in that, Also includes: An optical transceiver element is disposed within the second cavity.

5. The photonic packaging structure according to claim 4, characterized in that, The optical transceiver element receives and transmits optical signals, wherein the optical signals are transmitted to the optical transceiver element in a direction perpendicular to the first surface of the photonic integrated circuit.

6. The photonic packaging structure according to claim 4, characterized in that, Along the length direction of the photonic integrated circuit, the optical transceiver element extends beyond the electronic integrated circuit.

7. The photonic packaging structure according to claim 2, characterized in that, The second circuit layer includes a conductive via extending perpendicular to the first surface of the photonic integrated circuit and disposed on the side surface of the photonic integrated circuit, the conductive via being electrically connected to the first circuit layer.

8. A photonic packaging structure, characterized in that, include: An electronic integrated circuit has a first cavity; The first circuit layer is disposed below the electronic integrated circuit; A photonic integrated circuit is disposed within the first cavity, and the length direction of the photonic integrated circuit is perpendicular to the length direction of the electronic integrated circuit. The second circuit layer is disposed on the side surface of the photonic integrated circuit facing the first circuit layer and is electrically connected to the first circuit layer.

9. The photonic packaging structure according to claim 8, characterized in that, Also includes: An optical transceiver element is disposed on the photonic integrated circuit, and extends beyond the electronic integrated circuit along the length direction of the photonic integrated circuit.

10. The photonic packaging structure according to claim 9, characterized in that, The photonic integrated circuit has a first surface parallel to its length direction. The second circuit layer is also disposed on the first surface of the photonic integrated circuit, exposing the optical transceiver element and connected to the electrical connection terminal of the photonic integrated circuit.

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