Power down protection circuit for embedded memory system

Abstract

The disclosure provides a power-off protection circuit of an embedded storage system, comprising: a voltage monitoring circuit and an interrupt trigger circuit; an input end of the voltage monitoring circuit is electrically connected to an output end of a power supply, for monitoring an output voltage, outputting a rising edge jump signal when the output voltage is monitored to decrease to a preset lower limit threshold voltage, and outputting a falling edge jump signal when the input voltage is monitored to increase to a preset upper limit threshold voltage; the interrupt trigger circuit is electrically connected between an output end of the voltage monitoring circuit and an external interrupt pin of a CPU, for inputting the jump signal output by the voltage monitoring circuit to the external interrupt pin of the CPU after logical processing, so that the CPU performs differentiated power-off protection operation based on the jump signal after logical processing. The power-off protection circuit of the disclosure can improve the response speed and effectiveness of the power-off protection mechanism.

Description

Technical Field

[0001] This disclosure relates to the field of electronic equipment technology, and in particular to a power-down protection circuit for an embedded storage system. Background Technology

[0002] Embedded storage systems are widely used in industrial control, IoT devices, and consumer electronics, responsible for data storage and management. These systems typically use flash memory as the storage medium, including NAND Flash and NOR Flash. Under normal operating conditions, embedded storage systems require continuous power to ensure data integrity and file system stability. Power-loss protection refers to technologies that take appropriate measures to prevent data loss or file system corruption in the event of a sudden power outage.

[0003] Currently, power status is typically detected using software polling. When an abnormality is detected, a power outage protection operation is executed. This software-based power outage protection mechanism has a slow response time; it can take tens of milliseconds or even longer from the occurrence of a power abnormality to the software's detection. During this time, the system may already be unable to function properly, causing the protection measures to fail. Therefore, improving the response speed and effectiveness of power outage protection mechanisms has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0004] In view of this, this disclosure proposes a power-loss protection circuit for an embedded storage system, which can improve the response speed and effectiveness of the power-loss protection mechanism.

[0005] According to a first aspect of this disclosure, a power-down protection circuit for an embedded storage system is provided, comprising: a voltage monitoring circuit and an interrupt triggering circuit; The input terminal of the voltage monitoring circuit is electrically connected to the output terminal of the power supply to monitor the output voltage. When the output voltage drops to a preset lower threshold voltage, a rising edge transition signal is output. When the output voltage rises to a preset upper threshold voltage, a falling edge transition signal is output. The interrupt trigger circuit is electrically connected between the output terminal of the voltage monitoring circuit and the external interrupt pin of the CPU. It is used to process the switching signal output by the voltage monitoring circuit and input it to the external interrupt pin of the CPU, so that the CPU can perform differentiated power-off protection operations based on the processed switching signal.

[0006] In one possible implementation, the voltage monitoring circuit is based on an optocoupler having the upper threshold voltage and the lower threshold voltage.

[0007] In one possible implementation, the optocoupler is model ACPL-K376.

[0008] In one possible implementation, the voltage monitoring circuit includes a first resistor, a Zener diode, the optocoupler, a first capacitor, a second capacitor C552, and a third resistor. The first end of the first resistor is electrically connected to the positive output terminal of the power supply as the first input terminal of the voltage monitoring circuit, and the second end of the first resistor is electrically connected to the DC positive input terminal of the optocoupler through a Zener diode. The DC negative input terminal of the optocoupler is electrically connected to the negative output terminal of the power supply as the second input terminal of the voltage monitoring circuit. The voltage output terminal of the optocoupler is electrically connected to the input terminal of the interrupt trigger circuit as the output terminal of the voltage monitoring circuit. The voltage output terminal of the optocoupler is also grounded through the second capacitor C552 connected in parallel and the third resistor. The power supply voltage terminal of the optocoupler is electrically connected to the first operating power supply, and the power supply voltage terminal of the optocoupler is also grounded through the first capacitor; The grounding terminal of the optocoupler is grounded.

[0009] In one possible implementation, the voltage monitoring circuit is based on an integrated power monitoring chip.

[0010] In one possible implementation, the interrupt trigger circuit includes: an inverter, a MOSFET, a second resistor, a third capacitor, and a fourth resistor; The input terminal of the inverter is electrically connected to the output terminal of the voltage monitoring circuit as the input terminal of the interrupt trigger circuit. The input terminal of the inverter is also electrically connected to the first working power supply through the second resistor. The power supply voltage terminal of the inverter is electrically connected to the first working power supply. The power supply voltage terminal of the inverter is also grounded through the third capacitor. The output terminal of the inverter is electrically connected to the gate of the MOS transistor. The ground terminal of the inverter is grounded. The drain (D) of the MOS transistor is electrically connected to the external interrupt pin of the CPU as the output terminal of the interrupt trigger circuit. The drain of the MOS transistor is also electrically connected to the second operating power supply terminal through a fourth resistor. The source (S) of the MOS transistor is grounded.

[0011] In one possible implementation, the interrupt triggering circuit is implemented using an FPGA.

[0012] In one possible implementation, an energy storage circuit is also included, the output of which is electrically connected to the power supply of the CPU to supply power to the CPU when power is off.

[0013] In one possible implementation, the energy storage circuit includes a fifth resistor, a sixth resistor, a seventh resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and a diode; The fifth, sixth, and seventh resistors are connected in series and then connected in parallel with the diode. The negative terminal of the diode is electrically connected to the power supply terminal of the CPU as the output terminal of the energy storage circuit, and the positive terminal of the diode is grounded through the fifth capacitor, the sixth capacitor and the seventh capacitor connected in parallel.

[0014] This disclosure provides a power-down protection circuit for an embedded storage system, including a voltage monitoring circuit and an interrupt triggering circuit. The input terminal of the voltage monitoring circuit is electrically connected to the output terminal of the power supply to monitor the output voltage. When the output voltage drops to a preset lower threshold voltage, a rising edge transition signal is output; when the output voltage rises to a preset upper threshold voltage, a falling edge transition signal is output. The interrupt triggering circuit is electrically connected between the output terminal of the voltage monitoring circuit and the external interrupt pin of the CPU. It processes the transition signal output by the voltage monitoring circuit logically and inputs it to the external interrupt pin of the CPU, so that the CPU performs differentiated power-down protection operations based on the logically processed transition signal. This disclosure, through the hardware circuit of the power-down protection circuit, directly monitors the input power supply voltage and triggers a CPU interrupt in case of an anomaly. This effectively overcomes the slow response problem of traditional software polling methods, shortens the delay between power-down detection and protection action execution, improves the response speed of the power-down protection mechanism, and thus improves the effectiveness of power-down protection.

[0015] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0016] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0017] Figure 1 This illustrates a power-loss protection circuit for an embedded storage system according to an embodiment of the present disclosure; Figure 2 A voltage monitoring circuit according to an embodiment of the present disclosure is shown; Figure 3 An interrupt triggering circuit according to an embodiment of the present disclosure is shown; Figure 4 An energy storage circuit according to an embodiment of the present disclosure is shown; Figure 5 A schematic diagram of a power-off protection mechanism according to an embodiment of the present disclosure is shown. Detailed Implementation

[0018] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0019] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0020] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0021] <Example> Figure 1 A power-down protection circuit for an embedded storage system according to an embodiment of the present disclosure is shown. For example... Figure 1 As shown, the power failure protection circuit 100 includes a voltage monitoring circuit 110 and an interrupt trigger circuit 120.

[0022] The input terminal of the voltage monitoring circuit 110 is electrically connected to the output terminal of the power supply to monitor the output voltage of the power supply. When the output voltage of the power supply drops to a preset lower threshold voltage, a rising edge switching signal is output. When the output voltage of the power supply rises to a preset upper threshold voltage, a falling edge switching signal is output. Interrupt trigger circuit 120 is electrically connected between the output of voltage monitoring circuit 110 and the external interrupt pin of CPU. It is used to process (invert) the switching signal output by voltage monitoring circuit 110 and input it to the external interrupt pin of CPU so that CPU can perform differentiated power-off protection operation based on the processed switching signal.

[0023] In one possible implementation, the voltage monitoring circuit 110 is based on an optocoupler with an upper threshold voltage TH+ and a lower threshold voltage TH-. Specifically, an ACPL-K376 optocoupler can be used, which is an optocoupler with voltage / current threshold detection and an internal threshold detection input buffer IC. Its upper threshold voltage TH+ is 95V, and its lower threshold voltage TH- is 69.3~77V.

[0024] In one possible implementation, the voltage monitoring circuit 110, based on the ACPL-K376 optocoupler, is as follows: Figure 2As shown, it includes a first resistor, a Zener diode, an optocoupler U61, a first capacitor, a second capacitor C552, and a third resistor R590. The first resistor is formed by connecting resistors R584, R587, R588, and R585 in series. The Zener diode is formed by connecting Zener diodes D83 and D84 in series. The first capacitor is formed by connecting capacitors C549 and C550 in parallel. The first end of the first resistor is electrically connected to the positive output terminal VIN 110+ of the power supply as the first input terminal of the voltage monitoring circuit 110, and the second end of the first resistor is electrically connected to the positive DC input terminal DC+ of the optocoupler U61 through the Zener diode. The DC negative input terminal DC- of optocoupler U61 is electrically connected to the negative output terminal VIN 110- of the power supply as the second input terminal of voltage monitoring circuit 110; The voltage output terminal VO of the optocoupler U61 is electrically connected to the input terminal of the interrupt trigger circuit 120 as the output terminal of the voltage monitoring circuit 110. The voltage output terminal VO of the optocoupler U61 is also grounded through the second capacitor C552 and the third resistor R590 connected in parallel. The power supply voltage terminal VCC of optocoupler U61 is electrically connected to the first operating power supply, and the power supply voltage terminal VCC of optocoupler U61 is also grounded through the first capacitor. The grounding terminal GND of optocoupler U61 is grounded.

[0025] In one possible implementation, the interrupt trigger circuit 120 is as follows: Figure 3 The circuit includes: inverter U62, MOSFET Q16, second resistor R589, third capacitor C551, and fourth resistor R586. Inverter U62 is model SN74AHC1G04DBVR, which can flip the switching signal output by the optocoupler. MOSFET Q16 is model BSS138LT1G N-MOS transistor with Vgs=0.85V. The input terminal B of inverter U62 is electrically connected to the output terminal of voltage monitoring circuit 110 as the input terminal of interrupt trigger circuit 120. The input terminal B of inverter U62 is also electrically connected to the first working power supply through the second resistor R589. The power supply voltage terminal VCC of inverter U62 is electrically connected to the first working power supply. The power supply voltage terminal VCC of inverter U62 is also grounded through the third capacitor C551. The output terminal Y of inverter U62 is electrically connected to the gate of MOSFET Q16. The ground terminal GND of inverter U62 is grounded. The drain of MOSFET Q16 is electrically connected to the external interrupt pin of the CPU as the output of interrupt trigger circuit 120. The drain of MOSFET Q16 is also electrically connected to the second operating power supply through the fourth resistor R586. The source of MOSFET Q16 is grounded.

[0026] It should be noted that the first power supply is used to provide operating voltage for the optocoupler and inverter, and the second power supply is used to provide operating voltage for the CPU.

[0027] In one possible implementation, the power-down protection circuit 100 further includes an energy storage circuit 130. The output of the energy storage circuit 130 is electrically connected to the CPU's power supply terminal to provide power to the CPU during power failure, ensuring that the CPU has sufficient time to perform the power-down protection operation. Specifically, the energy storage circuit 130 is as follows: Figure 4 The circuit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and a diode D2. Among them, the fifth capacitor C5, the sixth capacitor C6, and the seventh capacitor C7 are polarized capacitors. The fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are connected in series and then in parallel with the diode D2. The negative terminal of the diode D2 is electrically connected to the power supply terminal of the CPU as the output terminal of the energy storage circuit 130, and the positive terminal of the diode D2 is grounded through the parallel-connected fifth capacitor C5, sixth capacitor C6, and seventh capacitor C7.

[0028] Figure 1 The protection mechanism of the power-down protection circuit shown is as follows: Figure 5 As shown: When the system is powered on, the input voltage of the optocoupler rises rapidly to greater than TH+ (95V), the output of optocoupler U61 is a falling edge, and after passing through inverter U62, the pulse reaching the gate of MOSFET Q16 is a rising edge. MOSFET Q16 is turned off, the CPU external interrupt pin is pulled high by the pull-up resistor, and the interrupt program is not triggered.

[0029] When a short circuit fault occurs in the system, causing the power supply to be pulled low, but remaining above TH- (69.3~77V), the optocoupler U61 still outputs a falling edge, and the interrupt program is not triggered.

[0030] When the system loses power, the input voltage of the optocoupler drops rapidly to below TH- (69.3~77V). At this time, the optocoupler U61 will output a rising edge, which, after passing through the inverter U62, will reach the gate of the MOSFET Q16 as a falling edge. The MOSFET Q16 will turn on, the CPU's external interrupt pin will be pulled low, triggering the CPU to start a high-priority interrupt program, immediately stopping all storage operations and completing the current data transfer to ensure that the file system is not corrupted.

[0031] The energy storage circuit starts working after the power supply fails. Since the supercapacitors C5, C6, and C7 have already been fully charged during the power-on period, they can continue to provide 5V power to the CPU through diode D2 after the power supply fails, thus providing a brief power supply to the CPU and delaying the CPU's power-off time to ensure that the CPU can take appropriate measures to prevent data loss or file system corruption.

[0032] In this feasible approach, by introducing an optocoupler with multiple threshold levels (including an upper threshold voltage TH+ and a lower threshold voltage TH-), the degree of power supply voltage abnormality (short circuit fault or system power failure) can be accurately determined. Then, differentiated protection strategies can be adopted according to the degree of power supply voltage abnormality. In this way, critical data security can be guaranteed, and the normal operation of the system can be maintained as much as possible.

[0033] Furthermore, this implementation method utilizes a hardware interrupt mechanism for power-down protection circuitry in conjunction with a software interrupt routine for the CPU, ensuring fast interrupt response while providing flexible protection strategy configuration capabilities. Compared to the power-down protection mechanism of dual-power supply solutions, this solution is simpler to implement and more reliable. Actual testing shows that this solution can achieve a data integrity rate of over 99.99% in embedded storage systems under sudden power loss conditions, reduce the probability of file system corruption by two orders of magnitude, and shorten system recovery time by over 80%, effectively improving the reliability and data security of embedded storage systems.

[0034] In embodiments where electrical isolation is not required, the voltage monitoring circuit 110 described above can also be implemented based on an integrated power monitoring chip to simplify circuit design. Specifically, a dedicated reset chip (integrated power monitoring chip) of model MAX809 can be used to replace the optocoupler in the above solution. The MAX809 chip can generate a reset signal after detecting a reset threshold voltage, and send this signal to the CPU to start the interrupt protection program. Since the voltage detection range of the MAX809 chip is relatively low, from 2.5V to 5V, the MAX809 chip can be used directly if the input voltage is within this range. However, if the input voltage is higher, for example... Figure 1 The 110V involved requires a voltage divider circuit to be designed after the power supply to provide the MAX809 chip with the required voltage value for its monitoring.

[0035] In another possible implementation, the interrupt trigger circuit 120 described above can also be implemented using an FPGA. Specifically, an FPGA is used instead of the interrupt trigger circuit 120 in the above scheme to directly implement signal conditioning and logic inversion operations on the switching signal output by the voltage monitoring circuit 110 through the FPGA, and input the logic-processed switching signal to the external interrupt pin of the CPU so that the CPU can perform differentiated power-off protection operations based on the logic-processed switching signal.

[0036] In one possible implementation, the power-down protection program executed by the CPU can be implemented at the operating system kernel layer or the hardware abstraction layer to improve the efficiency and reliability of the power-down protection program execution.

[0037] In one possible implementation, voltage detection points can be selected at each DC output terminal after power conversion to enable independent monitoring of different power supplies.

[0038] In one possible implementation, for special storage media such as FRAM, it can be simplified to simply stopping the access operation without requiring a data saving step.

[0039] It should be noted that the above alternatives can be selected and combined according to specific application scenarios and cost requirements, and no specific limitations are made here.

[0040] This disclosure provides a power-down protection circuit for an embedded storage system, including a voltage monitoring circuit and an interrupt triggering circuit. The input terminal of the voltage monitoring circuit is electrically connected to the output terminal of the power supply to monitor the output voltage. When the output voltage drops to a preset lower threshold voltage, a rising edge transition signal is output; when the output voltage rises to a preset upper threshold voltage, a falling edge transition signal is output. The interrupt triggering circuit is electrically connected between the output terminal of the voltage monitoring circuit and the external interrupt pin of the CPU. It processes the transition signal output by the voltage monitoring circuit logically and inputs it to the external interrupt pin of the CPU, so that the CPU performs differentiated power-down protection operations based on the logically processed transition signal. This disclosure, through the hardware circuit of the power-down protection circuit, directly monitors the input power supply voltage and triggers a CPU interrupt in case of an anomaly. This effectively overcomes the slow response problem of traditional software polling methods, shortens the delay between power-down detection and protection action execution, improves the response speed of the power-down protection mechanism, and thus improves the effectiveness of power-down protection.

[0041] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A power-loss protection circuit for an embedded storage system, characterized in that, include: Voltage monitoring circuit and interrupt triggering circuit; The input terminal of the voltage monitoring circuit is electrically connected to the output terminal of the power supply to monitor the output voltage. When the output voltage drops to a preset lower threshold voltage, a rising edge transition signal is output. When the output voltage rises to a preset upper threshold voltage, a falling edge transition signal is output. The interrupt trigger circuit is electrically connected between the output terminal of the voltage monitoring circuit and the external interrupt pin of the CPU. It is used to process the switching signal output by the voltage monitoring circuit and input it to the external interrupt pin of the CPU, so that the CPU can perform differentiated power-off protection operations based on the processed switching signal.

2. The power-off protection circuit according to claim 1, characterized in that, The voltage monitoring circuit is implemented based on an optocoupler having the upper threshold voltage and the lower threshold voltage.

3. The power-off protection circuit according to claim 2, characterized in that, The optocoupler is model ACPL-K376.

4. The power-off protection circuit according to claim 3, characterized in that, The voltage monitoring circuit includes a first resistor, a Zener diode, the optocoupler, a first capacitor, a second capacitor C552, and a third resistor; The first end of the first resistor is electrically connected to the positive output terminal of the power supply as the first input terminal of the voltage monitoring circuit, and the second end of the first resistor is electrically connected to the DC positive input terminal of the optocoupler through a Zener diode. The DC negative input terminal of the optocoupler is electrically connected to the negative output terminal of the power supply as the second input terminal of the voltage monitoring circuit. The voltage output terminal of the optocoupler is electrically connected to the input terminal of the interrupt trigger circuit as the output terminal of the voltage monitoring circuit. The voltage output terminal of the optocoupler is also grounded through the second capacitor C552 connected in parallel and the third resistor. The power supply voltage terminal of the optocoupler is electrically connected to the first operating power supply, and the power supply voltage terminal of the optocoupler is also grounded through the first capacitor; The grounding terminal of the optocoupler is grounded.

5. The power-off protection circuit according to claim 1, characterized in that, The voltage monitoring circuit is implemented based on an integrated power monitoring chip.

6. The power-off protection circuit according to claim 1, characterized in that, The interrupt trigger circuit includes: an inverter, a MOSFET, a second resistor, a third capacitor, and a fourth resistor; The input terminal of the inverter is electrically connected to the output terminal of the voltage monitoring circuit as the input terminal of the interrupt trigger circuit. The input terminal of the inverter is also electrically connected to the first working power supply through the second resistor. The power supply voltage terminal of the inverter is electrically connected to the first working power supply. The power supply voltage terminal of the inverter is also grounded through the third capacitor. The output terminal of the inverter is electrically connected to the gate of the MOS transistor. The ground terminal of the inverter is grounded. The drain (D) of the MOS transistor is electrically connected to the external interrupt pin of the CPU as the output terminal of the interrupt trigger circuit. The drain of the MOS transistor is also electrically connected to the second operating power supply terminal through a fourth resistor. The source (S) of the MOS transistor is grounded.

7. The power-off protection circuit according to claim 1, characterized in that, The interrupt triggering circuit is implemented using an FPGA.

8. The power-off protection circuit according to claim 1, characterized in that, It also includes an energy storage circuit, the output of which is electrically connected to the power supply terminal of the CPU to supply power to the CPU when the power is off.

9. The power-off protection circuit according to claim 8, characterized in that, The energy storage circuit includes a fifth resistor, a sixth resistor, a seventh resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and a diode; The fifth, sixth, and seventh resistors are connected in series and then connected in parallel with the diode. The negative terminal of the diode is electrically connected to the power supply terminal of the CPU as the output terminal of the energy storage circuit, and the positive terminal of the diode is grounded through the fifth capacitor, the sixth capacitor and the seventh capacitor connected in parallel.

Images