Control circuit and electronic device

Abstract

The application discloses a control circuit and electronic equipment, and belongs to the technical field of electronic equipment. The control circuit comprises a software control port, a hardware control port, an external control port and a signal generation circuit. The software control port is used for being connected with a general control port of a processor. The processor calls a shutdown processing method in the case where a first level signal is received by the general control port. The hardware control port is used for being connected with a startup control port of the processor. The processor automatically starts up in the case where a second level signal is received by the startup control port. The signal generation circuit is used for outputting the first level signal to the software control port in the case where a shutdown signal is received by the external control port. The signal generation circuit is used for outputting the second level signal to the hardware control port in the case where a startup signal is received by the external control port. The application can effectively avoid the running problem of the processor caused by abnormal power-off, and guarantee the running stability.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a control circuit and electronic equipment. Background Technology

[0002] The microcontroller-processor platform architecture is widely used in embedded systems, IoT systems, industrial control, and other fields. In this type of platform architecture, processor power-on / off control is an indispensable design requirement.

[0003] Current processor power-on / off control typically involves controlling the power supply device that powers the processor to start or stop, so that the processor can be powered on when the power supply device is turned on and the processor is powered on; and the processor can be powered off when the power supply device is turned off and the processor is de-energized.

[0004] However, the power-on / off control of this processor is similar to a cold shutdown due to an abnormal power outage. An abnormal power outage of the processor can easily cause damage to the processor itself, as well as to normally functioning devices such as memory connected to the processor, resulting in data loss or the need for lengthy abnormal file system repairs, leading to platform malfunctions. Summary of the Invention

[0005] This application provides a control circuit and electronic device to solve the problem that processor power-on / off control can easily cause operational abnormalities in related technologies.

[0006] To solve the above problems, the embodiments of this application are implemented as follows: In a first aspect, embodiments of this application disclose a control circuit, which includes: a software control port, a hardware control port, an external control port, and a signal generation circuit; The software control port is used to connect to the processor's general-purpose control port, and the processor invokes a shutdown process when the general-purpose control port receives a first level signal. The hardware control port is used to connect to the power-on control port of the processor, and the processor automatically powers on when the power-on control port receives a second level signal; The signal generation circuit is connected to the software control port, the hardware control port, and the external control port, respectively, and is used to output the first level signal to the software control port when the external control port receives a power-off signal, and to output the second level signal to the hardware control port when the external control port receives a power-on signal.

[0007] Optionally, the signal generation circuit includes: a first signal switching module, a second signal switching module, a first signal port, and a second signal port, wherein the first signal port is used to provide the first level signal, and the second signal port is used to provide the second level signal; The first signal switching module is connected to the external control port, the software control port, the first signal port, and the second signal port respectively, and is used to output the first level signal to the software control port in response to the power-off signal, and to output the second level signal to the software control port in response to the power-on signal; The second signal switching module is connected to the external control port, the hardware control port and the second signal port respectively, and is used to output the second level signal to the hardware control port in response to the power-on signal.

[0008] Optionally, the first signal switching module includes: n cascaded first switching devices, where n is an odd number; The first end of the i-th first switch is connected to the first signal port and the third end of the (i+1)-th first switch, the second end of the i-th first switch is connected to the second signal port, and the third end of the 1st first switch is connected to the external control port. The first end of the nth first switch is connected to the first signal port and the software control port, the second end of the nth first switch is connected to the second signal port, and the third end of the nth first switch is connected to the first end of the (n-1)th first switch. The nth first switch is used to connect the first terminal and the second terminal in response to the power-on signal, and to disconnect the first terminal and the second terminal in response to the power-off signal. The ith first switch is used to connect the first terminal and the second terminal in response to the first level signal, and to disconnect the first terminal and the second terminal in response to the second level signal. i is a positive integer less than n.

[0009] Optionally, n=1, the second signal port is grounded; the first switching element is a transistor; The input terminal of the first switch is connected to the software control port and the first signal port respectively, the output terminal of the first switch is connected to the second signal port, and the control terminal of the first switch is connected to the external control port.

[0010] Optionally, the first signal switching module further includes: a first resistor; A first resistor is provided between the first terminal of each of the first switching devices and the first signal port.

[0011] Optionally, the second signal switching module includes: m cascaded second switches, where m is an odd number; The first end of the j-th second switch is connected to the first signal port and the third end of the (j+1)-th second switch, the second end of the j-th second switch is connected to the second signal port, and the third end of the first second switch is connected to the external control port. The first end of the m-th second switch is connected to the hardware control port, the second end of the m-th second switch is connected to the second signal port, and the third end of the m-th second switch is connected to the first end of the (m-1)-th second switch. The m-th second switch is used to connect the first terminal and the second terminal in response to the power-on signal, and to disconnect the first terminal and the second terminal in response to the power-off signal. The j-th second switch is used to connect the first terminal and the second terminal in response to the first level signal, and to disconnect the first terminal and the second terminal in response to the second level signal, where j is a positive integer less than m.

[0012] Optionally, m=3, the second signal port is grounded; the second switching element is a transistor; The output terminal of each second switch is connected to the second signal port, the control terminal of the first second switch is connected to the external control port, and the input terminal of the first second switch is connected to the first signal port and the control terminal of the second second switch, respectively. The input terminal of the second second switch is connected to the first signal port and the control terminal of the third second switch, respectively, and the input terminal of the third second switch is connected to the hardware control port.

[0013] Optionally, the second signal switching module further includes: a second resistor and a third resistor; A second resistor is provided between the first end of each second switch and the first signal port, and a third resistor is provided between the first end of the m-th second switch and the hardware control port.

[0014] Optionally, the signal generation circuit further includes: a voltage absorber; The voltage absorber is connected to the external control port, the first signal switching module, and the second signal switching module, and is used to suppress the voltage of the access signal of the external control port.

[0015] Optionally, the power-off signal is the second level signal; the signal generation circuit further includes: a fourth resistor; One end of the fourth resistor is connected to the second signal port, and the other end of the fourth resistor is connected to the first signal switching module and the second signal switching module respectively.

[0016] Optionally, the electronic device includes a controller and a control circuit as described in any of the first aspects; The controller is connected to the external control port and is used to output the shutdown signal to the external control port when a shutdown input is detected, and to output the power-on signal to the external control port when a power-on input is detected.

[0017] In this embodiment, the control circuit includes a software control port, a hardware control port, an external control port, and a signal generation circuit. The software control port is connected to the processor's general-purpose control port, and the hardware control port is connected to the processor's power-on control port. The signal generation circuit is connected to the external control port, the software control port, and the hardware control port. When the external control port receives a power-off signal, it outputs a first-level signal to the software control port, enabling the processor to perform a soft shutdown by invoking a shutdown processing method when the general-purpose control port receives the first-level signal, thus achieving the processor's power-on control. Furthermore, the signal generation circuit is also used to output a second-level signal to the hardware control port when the external control port receives a power-on signal, utilizing the processor's automatic power-on mechanism when the power-on control port receives the second-level signal to achieve processor power-on control, thereby realizing the processor's power-on and power-off control.

[0018] Because the control circuit of this application utilizes the processor's soft shutdown capability and the processor's power-on control port to control the processor to execute the normal power-on and power-off process, compared with related technologies, the control circuit of this application can effectively avoid operational problems caused by abnormal power outages while efficiently realizing the processor's power-on and power-off control, thus ensuring operational stability. Attached Figure Description

[0019] Figure 1 This paper shows a schematic diagram of the control circuit provided in an embodiment of the present application; Figure 2 A second schematic diagram of the control circuit provided in an embodiment of this application is shown; Figure 3 The third schematic diagram of the control circuit provided in the embodiment of this application is shown; Figure 4 The fourth schematic diagram of the control circuit provided in the embodiment of this application is shown; Figure 5 The fifth schematic diagram of the control circuit provided in the embodiment of this application is shown; Figure 6 The sixth schematic diagram of the control circuit provided in the embodiment of this application is shown. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] Please refer to Figure 1 The diagram illustrates a control circuit according to an embodiment of this application. The control circuit is used to control the power on / off of the processor. Figure 1 As shown, the control circuit 1 includes: a software control port PWR_DET, a hardware control port PWR_HAR, an external control port PWR_CTL, and a signal generation circuit 10.

[0022] The software control port PWR_DET is used to connect to the general-purpose control port of processor 2. Processor 2 (Central Processing Unit, CPU) invokes the shutdown procedure upon receiving a first-level signal on the general-purpose control port.

[0023] The hardware control port PWR_HAR is used to connect to the power-on control port of processor 2. Processor 2 automatically powers on when the power-on control port receives the second level signal.

[0024] The signal generation circuit 10 is connected to the software control port PWR_DET, the hardware control port PWR_HAR, and the external control port PWR_CTL. The signal generation circuit 10 is used to output a first-level signal to the software control port PWR_DET when the external control port PWR_CTL receives a power-off signal, and to output a second-level signal to the hardware control port PWR_HAR when the external control port PWR_CTL receives a power-on signal.

[0025] In this embodiment, the general-purpose control port can be an input port of the processor 2. When the processor receives a first-level signal at the general-purpose control port, it calls a shutdown processing method to execute the normal shutdown procedure. Optionally, the shutdown processing method can be used to execute a shutdown handler to power off the processor. For example, the general-purpose control port can be a general-purpose input / output (GPIO) port of the processor, and the shutdown handler function it calls can be a function such as msm_poweroff() or qcom_scm_power_off() used to execute the shutdown procedure. In some embodiments, the general-purpose control port is an interrupt input port, which, when the processor is powered on, can notify the processor to immediately call the shutdown processing method to execute the shutdown procedure upon receiving the first-level signal.

[0026] The power-on control port is a hardware port on processor 2 that controls automatic power-on. The processor automatically powers on when it receives a second-level signal at the power-on control port. For example, the power-on control port is the CBL_PWR_N port, which defaults to a high-level signal and is effective when a low-level signal is received, in order to automatically power on.

[0027] The signal generation circuit 10 is used to output a first-level signal to the software control port PWR_DET when a power-off signal is received at the external control port PWR_CTL, so that the processor receives the first-level signal through the general control port and calls the power-off processing method to execute the power-off procedure. The signal generation circuit 10 is also used to output a second-level signal to the hardware control port PWR_HAR when a power-on signal is received at the external control port PWR_CTL, so that the processor receives the second-level signal through the power-on control port and executes the power-on procedure. Optionally, the signal generation circuit 10 can be hot-swapped or cold-connected to both the software control port PWR_DET and the hardware control port PWR_HAR.

[0028] In some embodiments, the processor does not trigger the shutdown process method call when it receives a second-level signal on the general control port. The processor does not perform any processing operations when it receives a first-level signal on the power-on control port.

[0029] The signal generation circuit 10 is further configured to output a first-level signal to the software control port PWR_DET and a first-level signal to the hardware control port PWR_HAR when a power-off signal is received at the external control port PWR_CTL, so as to cause the processor to perform a soft shutdown. The signal generation circuit 10 is also configured to output a second-level signal to the software control port PWR_DET and a second-level signal to the hardware control port PWR_HAR when a power-on signal is received at the external control port PWR_CTL, so as to cause the processor to perform a power-on procedure. For example, the first-level signal can be a high-level signal; the second-level signal can be a low-level signal.

[0030] Optionally, the external control port PWR_CTL in the control circuit can be connected to the controller. The controller outputs a power-off signal to the external control port PWR_CTL when a power-off input is detected, and outputs a power-on signal to the external control port PWR_CTL when a power-on input is detected. Specifically, the external control port PWR_CTL can be connected to a target GPIO port of the controller, so that the control circuit is controlled by the output signal of the target GPIO port of the controller. The controller outputs a power-off signal to the external control port PWR_CTL through the target GPIO port when a power-off input is detected, and outputs a power-on signal to the external control port PWR_CTL when a power-on input is detected.

[0031] Accordingly, the signal generation circuit 10 can be used to receive a shutdown signal through the external control port PWR_CTL when the controller detects a shutdown input, and output a first-level signal to the hardware control port PWR_HAR to cause the processor to perform a soft shutdown. The signal generation circuit 10 is also used to receive a power-on signal through the external control port PWR_CTL when the controller detects a power-on input, and output a second-level signal to both the software control port PWR_DET and the hardware control port PWR_HAR to cause the processor to execute a power-on process. The controller can be a microcontroller unit (MCU) or a microprocessor unit (MPU), etc.

[0032] For example, the power-off input is a first press operation on a physical button. The power-on input is a second press operation on a physical button. The controller can be connected to the physical button and, upon detecting the first press operation, outputs a power-off signal to the external control port PWR_CTL, causing the signal generation circuit 10 to control the processor to perform a soft power-off; upon detecting the second press operation, it outputs a power-on signal to the external control port PWR_CTL, causing the signal generation circuit 10 to control the processor to perform a power-on. Specifically, for example, the first press operation is a long press operation on the physical button; the second press operation is a short press operation on the physical button. It should be noted that a long press operation can refer to a press operation with a press duration exceeding a target duration threshold. A short press operation can refer to a press operation with a press duration less than or equal to the target duration threshold. Of course, the first press operation can also be two consecutive press operations on the physical button; the second press operation can be a single press operation on the physical button. Two consecutive press operations refer to two press operations with an interval duration less than a target interval threshold.

[0033] As another example, the power-off input and the power-on input are input operations directed to the display device. The controller can be connected to the display device to output a power-off signal to the external control port PWR_CTL upon receiving a power-off input through the display device, causing the signal generation circuit 10 to control the processor to perform a soft power-off; and to output a power-on signal to the external control port PWR_CTL upon receiving a power-on input through the display device, causing the signal generation circuit 10 to control the processor to perform a power-on. Specifically, for example, the power-off input and the power-on input can be different inputs in the form of clicks, swipes, long presses, or voice commands for the power on / off control.

[0034] In this embodiment, the control circuit includes a software control port, a hardware control port, an external control port, and a signal generation circuit. The software control port is connected to the processor's general-purpose control port, and the hardware control port is connected to the processor's power-on control port. The signal generation circuit is connected to the external control port, the software control port, and the hardware control port. When the external control port receives a power-off signal, it outputs a first-level signal to the software control port, enabling the processor to perform a soft shutdown by invoking a shutdown processing method when the general-purpose control port receives the first-level signal, thus achieving the processor's power-on control. Furthermore, the signal generation circuit is also used to output a second-level signal to the hardware control port when the external control port receives a power-on signal, utilizing the processor's automatic power-on mechanism when the power-on control port receives the second-level signal to achieve processor power-on control, thereby realizing the processor's power-on and power-off control.

[0035] Because the control circuit of this application utilizes the processor's soft shutdown capability and the processor's power-on control port to control the processor to execute the normal power-on and power-off process, compared with related technologies, the control circuit of this application can effectively avoid operational problems caused by abnormal power outages while efficiently realizing the processor's power-on and power-off control, thus ensuring operational stability.

[0036] In some embodiments of this application, such as Figure 2 As shown, the signal generation circuit 10 includes: a first signal switching module 101, a second signal switching module 102, a first signal port, and a second signal port. The first signal port is used to provide a first-level signal; the second signal port is used to provide a second-level signal. Optionally, the first-level signal is a high-level signal; the second-level signal is a low-level signal. Correspondingly, the first signal port can be a power supply terminal VDD; the second signal port can be a ground terminal GND. Figure 2 The illustration uses an example where the first signal port is the power supply terminal VDD and the second signal port is the ground terminal GND. In other embodiments, both the first and second signal ports can be power supply terminals, providing first-level signals and second-level signals with different voltages.

[0037] The first signal switching module 101 is connected to the external control port PWR_CTL, the software control port PWR_DET, the first signal port, and the second signal port. The first signal switching module 101 is used to output a first-level signal to the software control port PWR_DET in response to a power-off signal received from the external control port PWR_CTL, and to output a second-level signal to the software control port PWR_DET in response to a power-on signal received from the external control port PWR_CTL.

[0038] The second signal switching module 102 is connected to the external control port PWR_CTL, the hardware control port PWR_HAR, and the second signal port, respectively. The second signal switching module 102 is used to output a second-level signal to the hardware control port PWR_HAR in response to a power-on signal received from the external control port PWR_CTL. Optionally, the second signal switching module 102 is also connected to the first signal port, and is used to output a first-level signal to the hardware control port PWR_HAR in response to a power-off signal received from the external control port PWR_CTL.

[0039] In an optional configuration, the first signal switching module 101 can be used to connect the first signal port and the software control port PWR_DET in response to a power-off signal received from the external control port PWR_CTL, and disconnect the second signal port and the software control port PWR_DET, so that the first signal port provides a first-level signal to the software control port PWR_DET to control the processor to perform a soft shutdown. Furthermore, the second signal switching module 102 can be used to disconnect the first signal port and the software control port PWR_DET in response to a power-on signal received from the external control port PWR_CTL, and connect the second signal port and the software control port PWR_DET, so that the second signal port provides a second-level signal to the software control port PWR_DET to control the processor not to perform a soft shutdown. The second signal switching module 102 can also be used to connect the second signal port and the hardware control port PWR_HAR in response to a power-on signal received from the external control port PWR_CTL, so that the second signal port provides a second-level signal to the hardware control port PWR_HAR to control the processor to automatically power on.

[0040] Optionally, the second signal switching module 102 can be used to connect the second signal port and the hardware control port PWR_HAR in response to a power-on signal received from the external control port PWR_CTL, and disconnect the first signal port and the hardware control port PWR_HAR, so that the second signal port provides a second level signal to the hardware control port PWR_HAR to control the processor to automatically power on. Furthermore, the first signal switching module 101 can be used to disconnect the second signal port and the hardware control port PWR_HAR in response to a power-off signal received from the external control port PWR_CTL, and connect the first signal port and the hardware control port PWR_HAR, so that the first signal port provides a first level signal to the hardware control port PWR_HAR to control the processor not to perform automatic power-on.

[0041] In another alternative embodiment, the first signal switching module 101 includes n cascaded first switching elements, where n is an odd number.

[0042] The first end of the i-th first switch is connected to the first signal port and the third end of the (i+1)-th first switch, the second end of the i-th first switch is connected to the second signal port, and the third end of the 1st first switch is connected to the external control port PWR_CTL.

[0043] The first end of the nth first switch is connected to the first signal port and the software control port PWR_DET, the second end of the nth first switch is connected to the second signal port, and the third end of the nth first switch is connected to the first end of the (n-1)th first switch.

[0044] The nth first switch is used to connect the first and second terminals in response to a power-on signal, and to disconnect the first and second terminals in response to a power-off signal. The ith first switch is used to connect the first and second terminals in response to a first level signal, and to disconnect the first and second terminals in response to a second level signal, where i is a positive integer less than n. For example, the first switch can be a relay or a transistor, etc. Specifically, for example, the first switch is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) or an Insulated-Gate Bipolar Transistor (IGBT).

[0045] Optionally, in the first signal switching module 101, the third terminal of the first first switch is connected to the external control port PWR_CTL; the first terminal of the first first switch is connected to both the first signal port and the third terminal of the second first switch; and the second terminal of the first first switch is connected to the second signal port. Similarly, the first terminal of the second first switch is connected to both the first signal port and the third terminal of the third first switch; and the second terminal of the second first switch is connected to the second signal port. The first terminal of the i-th first switch is connected to both the first signal port and the third terminal of the (i+1)-th first switch; and the second terminal of the i-th first switch is connected to the second signal port. The third terminal of the n-th first switch is connected to the first terminal of the (n-1)-th first switch; the first terminal of the n-th first switch is connected to both the first signal port and the software control port PWR_DET; and the second terminal of the n-th first switch is connected to the second signal port.

[0046] When the external control port PWR_CTL receives a power-off signal, the first first switch disconnects its first and second terminals to disconnect the third terminal of the second first switch from the second signal port. At this time, the third terminal of the second first switch receives a first-level signal provided by the first port signal. Responding to the first-level signal, the second first switch connects its first and second terminals to connect the third terminal of the third first switch from the second signal port. At this time, the third terminal of the third first switch receives a second-level signal provided by the second port signal. Responding to the second-level signal, the third first switch disconnects its first and second terminals to disconnect the third terminal of the fourth first switch from the second signal port. At this time, the third terminal of the fourth first switch receives a first-level signal provided by the first port signal. And so on, the nth first switch disconnects its first and second terminals in response to the second-level signal to disconnect the software control port PWR_DET from the second signal port. At this time, the software control port PWR_DET receives a first-level signal provided by the first port signal to control the processor's soft shutdown.

[0047] Conversely, when the external control port PWR_CTL receives a power-on signal, the first first switch connects its first and second terminals to connect the third terminal of the second first switch to the second signal port. At this time, the third terminal of the second first switch receives a second-level signal provided by the second signal port. In response to the second-level signal, the second first switch disconnects its first and second terminals to disconnect the third terminal of the third first switch from the second signal port. At this time, the third terminal of the third first switch receives a second-level signal provided by the first signal port. Similarly, the nth first switch connects its first and second terminals in response to the first-level signal to connect the software control port PWR_DET to the second signal port. At this time, the software control port PWR_DET receives a second-level signal provided by the second port signal to control the processor not to perform a soft shutdown.

[0048] During the insertion and removal process between the control circuit and the processor, there is a high probability that spike interference signals will be generated, interfering with the control circuit's switching control of the processor. For example, when the first signal switching module 101 provides a low-level signal to the software control port PWR_DET, if this low-level signal contains spike interference signals (high-level signals), it may cause the processor to erroneously trigger a soft shutdown due to the spike interference signals. Therefore, when the first signal switching module 101 includes multiple cascaded first switches, the use of multiple cascaded first switches to effectively filter out spike interference signals generated by insertion and removal can effectively prevent spike interference signals from affecting the control circuit's effective control of the processor, thereby improving the control capability of the control circuit.

[0049] For example, such as Figure 3As shown, n=1. The first signal terminal is the power supply terminal VDD. The second signal port is the ground terminal GND, i.e., the second signal port is grounded. The first switch Q1 is a transistor. The input terminal (i.e., the first terminal) of the first switch Q1 is connected to the software control port PWR_DET and the first signal port VDD, respectively. The output terminal (i.e., the second terminal) of the first switch Q1 is connected to the second signal port GND. The control terminal (i.e., the third terminal) of the first switch Q1 is connected to the external control port PWR_CTL. The first switch Q1 is used to turn off under the control of the power-off signal received by the external control port PWR_CTL, so as to disconnect its input terminal and output terminal; and to turn on under the control of the power-on signal received by the external control port PWR_CTL, so as to connect its input terminal and output terminal.

[0050] For example, the first switching device can be an NMOS transistor, where both the power-off signal and the second-level signal are low-level signals, and both the switching signal and the first-level signal are high-level signals. Accordingly, the input terminal of the first switching device is the drain; the output terminal is the source; and the control terminal is the gate. Alternatively, if the first switching device is a PMOS transistor, both the power-off signal and the second-level signal are high-level signals, and both the switching signal and the first-level signal are low-level signals. Accordingly, the input terminal of the first switching device is the source; the output terminal is the drain; and the control terminal is the gate.

[0051] In some embodiments, the first signal switching module 10 further includes a first resistor. A first resistor is provided between the first terminal of each first switch and the first signal port to prevent the first signal port and the second signal port from being short-circuited when the first switch is connected to the first terminal and the second terminal. For example, please refer to [reference needed]. Figure 3 A first resistor R1_1 is provided between the input terminal of the first switch and the first signal terminal VDD.

[0052] In some embodiments of this application, the second signal switching module 102 is used to output a second level signal to the hardware control port PWR_HAR in response to the power-on signal received by the external control port PWR_CTL.

[0053] Optionally, the second signal switching module 102 includes m cascaded second switches, where m is an odd number. The first end of the j-th second switch is connected to the first signal port and the third end of the (j+1)-th second switch, the second end of the j-th second switch is connected to the second signal port, and the third end of the first second switch is connected to the external control port PWR_CTL.

[0054] The first end of the m-th second switch is connected to the hardware control port PWR_HAR, the second end of the m-th second switch is connected to the second signal port, and the third end of the m-th second switch is connected to the first end of the (m-1)-th second switch.

[0055] The m-th second switch is used to connect the first and second terminals in response to a power-on signal and to disconnect the first and second terminals in response to a power-off signal. The j-th second switch is used to connect the first and second terminals in response to a first-level signal and to disconnect the first and second terminals in response to a second-level signal. j is a positive integer less than m. For example, the second switch can be a relay or a transistor, etc. Specifically, for example, the second switch is a MOSFET or an IGBT.

[0056] Optionally, in the second signal switching module 102, the third terminal of the first second switch is connected to the external control port PWR_CTL, the first terminal of the first second switch is connected to both the first signal port and the third terminal of the second second switch, and the second terminal of the first second switch is connected to the second signal port. The first terminal of the second second switch is connected to both the first signal port and the third terminal of the third second switch, and the second terminal of the second second switch is connected to the second signal port. ... The first terminal of the i-th second switch is connected to both the first signal port and the third terminal of the (i+1)-th second switch, and the second terminal of the i-th second switch is connected to the second signal port. ... The third terminal of the n-th second switch is connected to the first terminal of the (n-1)-th second switch, the first terminal of the n-th second switch is connected to both the first signal port and the hardware control port PWR_HAR, and the second terminal of the n-th second switch is connected to the second signal port.

[0057] When the external control port PWR_CTL receives a power-off signal, the first second switch disconnects its first and second terminals to disconnect the third terminal of the second second switch from the second signal port. At this time, the third terminal of the second second switch receives a first-level signal provided by the first port signal. The second second switch, in response to the first-level signal, connects its first and second terminals to connect the third terminal of the third second switch from the second signal port. At this time, the third terminal of the third second switch receives a second-level signal provided by the second port signal. The third second switch, in response to the second-level signal, disconnects its first and second terminals to disconnect the third terminal of the fourth second switch from the second signal port. At this time, the third terminal of the fourth second switch receives the first-level signal provided by the first port signal. And so on, the nth second switch, in response to the second-level signal, disconnects its first and second terminals to disconnect the hardware control port PWR_HAR from the second signal port. At this time, the hardware control port PWR_HAR cannot receive the second-level signal provided by the second port signal, thus preventing the processor from automatically powering on.

[0058] Conversely, when the external control port PWR_CTL receives a power-on signal, the first second switch connects its first and second terminals to connect the third terminal of the second second switch to the second signal port. At this time, the third terminal of the second second switch receives a second-level signal provided by the second signal port. In response to the second-level signal, the second second switch disconnects its first and second terminals to disconnect the third terminal of the third second switch from the second signal port. At this time, the third terminal of the third second switch receives a second-level signal provided by the first signal port. Similarly, the nth second switch connects its first and second terminals in response to the first-level signal to connect the hardware control port PWR_HAR to the second signal port. At this time, the hardware control port PWR_HAR receives a second-level signal provided by the second port signal to control the processor to automatically power on.

[0059] Similarly, during the insertion and removal process between the control circuit and the processor, there is a high probability that spike interference signals will be generated, interfering with the control circuit's switching control of the processor. For example, when the second signal switching module 102 provides a low-level signal to the hardware control port PWR_HAR, if this low-level signal contains spike interference signals (high-level signals), it may cause the processor to be accidentally disconnected due to the spike interference signals. Therefore, when the second signal switching module 102 includes multiple cascaded second switches, the spike interference signals generated by insertion and removal can be effectively filtered out by using multiple cascaded second switches, which can effectively prevent spike interference signals from affecting the control circuit's effective control of the processor and improve the control capability of the control circuit.

[0060] For example, such as Figure 4As shown, m=3. The first signal terminal is the power supply terminal VDD. The second signal port is the ground terminal GND, meaning the second signal port is grounded. The second switching device is a transistor.

[0061] The output terminal (i.e., the second terminal) of each second switch is connected to the second signal port. The control terminal (i.e., the third terminal) of the first second switch Q2 is connected to the external control port PWR_CTL. The input terminal (i.e., the first terminal) of the first second switch Q2 is connected to the first signal port and the control terminal of the second second switch Q3, respectively.

[0062] The input terminal of the second second switch Q3 is connected to the first signal port and the control terminal of the third second switch Q4, respectively. The input terminal of the third second switch Q4 is connected to the hardware control port PWR_HAR. Specifically, the first second switch Q2 is turned on under the control of a power-on signal to connect its input and output terminals; and turned off under the control of a power-off signal to disconnect its input and output terminals. The second and third switches Q3 and Q4 are turned on under the control of a first-level signal to connect their input and output terminals; and turned off under the control of a second-level signal to disconnect their input and output terminals.

[0063] For example, the second switching device can be an NMOS transistor, where both the power-off signal and the second-level signal are low-level signals, and both the switching signal and the first-level signal are high-level signals. Accordingly, the input terminal of the second switching device is the drain; the output terminal is the source; and the control terminal is the gate. Alternatively, if the second switching device is a PMOS transistor, both the power-off signal and the second-level signal are high-level signals, and both the switching signal and the first-level signal are low-level signals. Accordingly, the input terminal of the second switching device is the source; the output terminal is the drain; and the control terminal is the gate.

[0064] In some embodiments, the second signal switching module 102 further includes a second resistor and a third resistor. A second resistor is provided between the first end of each second switch and the first signal port to prevent the first signal port and the second signal port from being short-circuited when the second switch is connected to the first end and the second end. A third resistor is provided between the first end of the m-th second switch and the hardware control port PWR_HAR to prevent the hardware control port PWR_HAR from being short-circuited to the second signal port when the second switch is connected to the first end and the second end.

[0065] For example, please continue to refer to Figure 4A second resistor R2_1 is provided between the input terminal of the first second switch and the first signal terminal VDD. A second resistor R2_2 is provided between the input terminal of the second second switch and the first signal terminal VDD. A third resistor R3 is provided between the input terminal of the third second switch and the hardware control port PWR_HAR.

[0066] In some embodiments of this application, such as Figure 5 As shown, the signal generation circuit 10 also includes a voltage absorber 103. The voltage absorber 103 is connected to the external control port PWR_CTL, the first signal switching module 101, and the second signal switching module 102. The voltage absorber 103 is used to suppress the voltage of the input signal to the external control port PWR_CTL, thereby effectively absorbing the voltage spikes of the input signal to the external control port PWR_CTL, de-jittering the input signal to the external control port PWR_CTL, improving the stability of the input signal to the external control port PWR_CTL, and correspondingly improving the control stability of the control circuit on the processor. For an example, please refer to [reference needed]. Figure 3 The voltage absorber 103 can be a capacitor C. Alternatively, the voltage absorber 103 can also be a resistor-capacitor RC filter.

[0067] In some embodiments of this application, such as Figure 5 As shown, when the power-off signal is a second-level signal, the signal generation circuit 10 further includes a fourth resistor R4. One end of the fourth resistor R4 is connected to the second signal port, and the other end of the fourth resistor R4 is connected to the first signal switching module 101 and the second signal switching module 102, respectively. By connecting the second signal port to the first signal switching module 101 and the second signal switching module 102 through the fourth resistor R4, when no signal is received at the external control port PWR_CTL, the first signal switching module 101 and the second signal switching module 102 can receive the power-off signal provided by the second signal port to maintain the processor's power-off state.

[0068] In this embodiment, the control circuit utilizes the processor's soft shutdown capability and the processor's power-on control port to control the processor to execute the normal power-on / off process. Therefore, compared to related technologies, the control circuit of this application can efficiently control the processor's power-on / off while effectively preventing operational problems caused by abnormal power outages, thus ensuring operational stability.

[0069] To facilitate understanding of the technical solution of this application, the control circuit provided in the embodiments of this application will be further described below with examples. For example, both the power-off signal and the second-level signal are low-level signals, while both the switch signal and the first-level signal are high-level signals. The first signal port is the power supply terminal VDD; the second signal port is the ground terminal GND.

[0070] like Figure 6 As shown, the control circuit includes: a software control port PWR_DET, a hardware control port PWR_HAR, an external control port PWR_CTL, and a signal generation circuit 10. The signal generation circuit 10 includes: a first signal switching module 101, a second signal switching module 102, a first signal port VDD, a second signal port GND, a voltage absorber 103, and a fourth resistor R4.

[0071] The first signal switching module 101 includes one first switch Q1 and three resistors. The first switch Q1 is an NMOS transistor. Its drain (i.e., input terminal) is connected to the software control port PWR_DET through a sixth resistor R1_2, and its drain is connected to the first signal port VDD through a first resistor R1_1. The source (output terminal) of the first switch Q1 is connected to the second signal port GND through a seventh resistor R1_4. The gate (i.e., control terminal) of the first switch Q1 is connected to the external control port PWR_CTL.

[0072] The second signal switching module 102 includes three second switches Q2-Q4 and four resistors. All second switches Q2-Q4 are NMOS transistors. The gate (control terminal) of the first second switch Q2 is connected to the external control port PWR_CTL, the source (output terminal) of the first second switch Q2 is connected to the second signal port GND, and the drain (input terminal) of the first second switch Q2 is connected to the gate of the second second switch Q3, and is connected to the first signal port VDD through the second resistor R2_1. The source of the second second switch Q3 is connected to the second signal port GND, and the drain of the second second switch Q3 is connected to the gate of the third second switch Q4 through the fifth resistor R5, and is connected to the first signal port VDD through the second resistor R2_2. The source of the third second switch Q4 is connected to the second signal port GND, and the drain of the third second switch Q4 is connected to the hardware control port PWR_HAR through the third resistor R3.

[0073] The voltage absorber 103 includes a capacitor C. One end of the capacitor C is grounded, and the other end of the capacitor C is connected to the external control port PWR_CTL, the gate of the first switch Q1, and the gate of the first second switch Q2. One end of the fourth resistor R4 is connected to the second signal port GND, and the other end of the fourth resistor R4 is connected to the external control port PWR_CTL, the gate of the first switch Q1, and the gate of the first second switch Q2.

[0074] When the external control port PWR_CTL receives a shutdown signal (low-level signal L), the first switch Q1 is turned off, the software control port PWR_DET is not pulled low by the second signal terminal GND, and the software control port PWR_DET receives the first level signal (high-level signal H) provided by the first port signal VDD to control the processor's soft shutdown.

[0075] The first second switch Q2 is turned off. The gate of the second second switch Q3 is not pulled low by the second signal terminal GND. The gate of the second second switch Q3 receives the first level signal (high level signal H) provided by the first port signal VDD, and the second second switch Q3 is turned on. The gate of the third second switch Q4 is pulled low by the second signal terminal GND. The gate of the third second switch Q4 receives the second level signal (low level signal L), and the third second switch Q4 is turned off. The hardware control port PWR_HAR is not pulled low by the second signal terminal GND. The hardware control port PWR_HAR maintains the default high level signal H to control the processor from performing automatic power-on.

[0076] When the external control port PWR_CTL receives a power-on signal (high-level signal H), the first switch Q1 is turned on, the software control port PWR_DET is pulled low by the second signal terminal GND, and the software control port PWR_DET is connected to the second level signal (low-level signal L) to control the processor not to perform a soft shutdown.

[0077] The first second switch Q2 is turned on, the gate of the second second switch Q3 is pulled low by the second signal terminal GND, the gate of the second second switch Q3 is connected to the second level signal (low level signal L), and the second second switch Q3 is turned off.

[0078] The gate of the third second switch Q4 is not pulled low by the second signal terminal GND. The gate of the third second switch Q4 receives the first level signal (high level signal H) provided by the first port signal VDD, and the third second switch Q4 is turned on. The hardware control port PWR_HAR is pulled low by the second signal terminal GND, and the hardware control port PWR_HAR is connected to the second level signal (low level signal L) to control the processor to automatically power on.

[0079] Based on this, as shown in Table 1, when the processor performs a shutdown process, the external control port PWR_CTL, the software control port PWR_DET, and the hardware control port PWR_HAR are connected to a low-level signal L, a high-level signal H, and a high-level signal H, respectively. When the processor performs a power-on process, the external control port PWR_CTL, the software control port PWR_DET, and the hardware control port PWR_HAR are connected to a high-level signal H, a low-level signal L, and a low-level signal L, respectively.

[0080]

[0081] Table 1 In summary, the control circuit provided in this application includes: a software control port, a hardware control port, an external control port, and a signal generation circuit. The software control port is connected to the processor's general-purpose control port, and the hardware control port is connected to the processor's power-on control port. The signal generation circuit is connected to the external control port, the software control port, and the hardware control port. When the external control port receives a power-off signal, it outputs a first-level signal to the software control port, enabling the processor to perform a soft shutdown by calling a shutdown processing method when the general-purpose control port receives the first-level signal, thus achieving the processor's shutdown control purpose. Furthermore, the signal generation circuit is also used to output a second-level signal to the hardware control port when the external control port receives a power-on signal, utilizing the processor's automatic power-on mechanism when the power-on control port receives the second-level signal to achieve processor shutdown control, thereby realizing the processor's power-on and power-off control.

[0082] Because the control circuit of this application utilizes the processor's soft shutdown capability and the processor's power-on control port to control the processor to execute the normal power-on and power-off process, compared with related technologies, the control circuit of this application can effectively avoid operational problems caused by abnormal power outages while efficiently realizing the processor's power-on and power-off control, thus ensuring operational stability.

[0083] This application also provides an electronic device, which includes a controller and a control circuit provided in this application embodiment. The controller is connected to an external control port PWR_CTL and is used to output a shutdown signal to the external control port PWR_CTL when a shutdown input is detected, and to output a power-on signal to the external control port PWR_CTL when a power-on input is detected. In the electronic device provided in this application embodiment, the control circuit includes: a software control port, a hardware control port, an external control port, and a signal generation circuit. The software control port is connected to the processor's general-purpose control port, and the hardware control port is connected to the processor's power-on control port. The signal generation circuit is connected to the external control port, the software control port, and the hardware control port, and is used to output a first-level signal to the software control port when a shutdown signal is received at the external control port, so that the processor can perform a soft shutdown by calling a shutdown processing method when the general-purpose control port receives the first-level signal, thereby achieving the shutdown control purpose of the processor. Furthermore, the signal generation circuit is also used to output a second-level signal to the hardware control port when a power-on signal is received at the external control port, so as to realize the power-off control of the processor by utilizing the processor's automatic power-on mechanism when the power-on control port receives the second-level signal, thereby realizing the power-on and power-off control of the processor.

[0084] Because the control circuit of this application utilizes the processor's soft shutdown capability and the processor's power-on control port to control the processor to execute the normal power-on and power-off process, compared with related technologies, the control circuit of this application can effectively avoid operational problems caused by abnormal power outages while efficiently realizing the processor's power-on and power-off control, thus ensuring operational stability.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0086] It will be readily apparent to those skilled in the art that any combination of the above embodiments is feasible. Therefore, any combination of the above embodiments is an implementation scheme of this application. However, due to space limitations, this specification will not describe them in detail here.

[0087] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0088] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0089] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0090] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0091] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A control circuit, characterized in that, The control circuit includes: a software control port, a hardware control port, an external control port, and a signal generation circuit; The software control port is used to connect to the processor's general-purpose control port, and the processor invokes the shutdown process method when the general-purpose control port receives a first level signal. The hardware control port is used to connect to the power-on control port of the processor, and the processor automatically powers on when the power-on control port receives a second level signal; The signal generation circuit is connected to the software control port, the hardware control port, and the external control port, respectively, and is used to output the first level signal to the software control port when the external control port receives a power-off signal, and to output the second level signal to the hardware control port when the external control port receives a power-on signal.

2. The control circuit according to claim 1, characterized in that, The signal generation circuit includes: a first signal switching module, a second signal switching module, a first signal port, and a second signal port, wherein the first signal port is used to provide the first level signal, and the second signal port is used to provide the second level signal; The first signal switching module is connected to the external control port, the software control port, the first signal port, and the second signal port respectively, and is used to output the first level signal to the software control port in response to the power-off signal, and to output the second level signal to the software control port in response to the power-on signal; The second signal switching module is connected to the external control port, the hardware control port and the second signal port respectively, and is used to output the second level signal to the hardware control port in response to the power-on signal.

3. The control circuit according to claim 2, characterized in that, The first signal switching module includes: n cascaded first switching devices, where n is an odd number; The first end of the i-th first switch is connected to the first signal port and the third end of the (i+1)-th first switch, the second end of the i-th first switch is connected to the second signal port, and the third end of the 1st first switch is connected to the external control port. The first end of the nth first switch is connected to the first signal port and the software control port, the second end of the nth first switch is connected to the second signal port, and the third end of the nth first switch is connected to the first end of the (n-1)th first switch. The nth first switch is used to connect the first terminal and the second terminal in response to the power-on signal, and to disconnect the first terminal and the second terminal in response to the power-off signal. The ith first switch is used to connect the first terminal and the second terminal in response to the first level signal, and to disconnect the first terminal and the second terminal in response to the second level signal. i is a positive integer less than n.

4. The control circuit according to claim 3, characterized in that, n=1, the second signal port is grounded; the first switching element is a transistor; The input terminal of the first switch is connected to the software control port and the first signal port respectively, the output terminal of the first switch is connected to the second signal port, and the control terminal of the first switch is connected to the external control port.

5. The control circuit according to claim 3 or 4, characterized in that, The first signal switching module further includes: a first resistor; A first resistor is provided between the first terminal of each of the first switching devices and the first signal port.

6. The control circuit according to claim 2, characterized in that, The second signal switching module includes: m cascaded second switches, where m is an odd number; The first end of the j-th second switch is connected to the first signal port and the third end of the (j+1)-th second switch, the second end of the j-th second switch is connected to the second signal port, and the third end of the first second switch is connected to the external control port. The first end of the m-th second switch is connected to the hardware control port, the second end of the m-th second switch is connected to the second signal port, and the third end of the m-th second switch is connected to the first end of the (m-1)-th second switch. The m-th second switch is used to connect the first terminal and the second terminal in response to the power-on signal, and to disconnect the first terminal and the second terminal in response to the power-off signal. The j-th second switch is used to connect the first terminal and the second terminal in response to the first level signal, and to disconnect the first terminal and the second terminal in response to the second level signal, where j is a positive integer less than m.

7. The control circuit according to claim 6, characterized in that, m=3, the second signal port is grounded; the second switching device is a transistor; The output terminal of each second switch is connected to the second signal port, the control terminal of the first second switch is connected to the external control port, and the input terminal of the first second switch is connected to the first signal port and the control terminal of the second second switch, respectively. The input terminal of the second second switch is connected to the first signal port and the control terminal of the third second switch, respectively, and the input terminal of the third second switch is connected to the hardware control port.

8. The control circuit according to claim 6 or 7, characterized in that, The second signal switching module further includes: a second resistor and a third resistor; A second resistor is provided between the first end of each second switch and the first signal port, and a third resistor is provided between the first end of the m-th second switch and the hardware control port.

9. The control circuit according to claim 2, characterized in that, The signal generation circuit further includes: a voltage absorber; The voltage absorber is connected to the external control port, the first signal switching module, and the second signal switching module, and is used to suppress the voltage of the access signal of the external control port.

10. The control circuit according to claim 2, characterized in that, The power-off signal is the second level signal; The signal generation circuit further includes: a fourth resistor; One end of the fourth resistor is connected to the second signal port, and the other end of the fourth resistor is connected to the first signal switching module and the second signal switching module respectively.

11. An electronic device, characterized in that, The electronic device includes a controller and a control circuit as described in any one of claims 1 to 10; The controller is connected to the external control port and is used to output the shutdown signal to the external control port when a shutdown input is detected, and to output the power-on signal to the external control port when a power-on input is detected.

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