A memory chip module and a memory device

Abstract

The application provides a storage chip module and a storage device. The storage chip module comprises a circuit board provided with a data bus; a plurality of dies coupled to the circuit board; a controller coupled to the circuit board, wherein the controller is coupled to each die through the data bus to send an access signal to each die; a plurality of enable lines provided on the circuit board, each enable line being connected between the controller and a corresponding die to enable the corresponding die; and a plurality of first internal terminal resistors respectively provided in the corresponding dies, each first internal terminal resistor being coupled to the controller through a corresponding first resistance line. Based on the above, the application can improve signal reflection and attenuation, ensure complete reception of signals, and reduce power consumption.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a storage chip module and storage device. Background Technology

[0002] In storage systems employing a multi-point bus topology, the controller sends access signals to each die based on user read / write commands. Each die then performs data reading or writing based on the received access signals. As high-speed digital signals, access signals face challenges of signal reflection and attenuation during transmission. To address this, current industry manufacturers typically incorporate on-die termination (ODT) resistors within the die. These continuously conducting ODT resistors, positioned along the signal reception path, absorb the signal and suppress reflections. However, the absorption of signals by the ODT resistors may cause additional attenuation and interference to the signal itself, thus affecting the integrity of signal reception. Utility Model Content

[0003] In view of this, this application provides a memory chip module and a memory device, which can improve the problem of the difficulty in simultaneously suppressing signal reflection and attenuation in memory systems and the resulting impact on the complete reception of signals.

[0004] The memory chip module provided in this application includes: The circuit board has a data bus. Multiple bare dies are coupled to the circuit board; A controller, coupled to the circuit board, is connected to each of the bare dies via the data bus to send access signals to each of the bare dies; Multiple enable lines are provided on the circuit board, and each enable line is connected between the controller and the corresponding bare die to enable the corresponding bare die, thereby allowing or disabling the corresponding bare die from receiving the access signal; Multiple first internal terminating resistors are respectively disposed in the corresponding bare die, and each first internal terminating resistor is coupled to the controller through a corresponding first resistor trace.

[0005] Optionally, the memory chip module further includes: At least one second internal terminating resistor, each second internal terminating resistor being coupled to the data bus; At least one second blocking trace is provided, and the controller is coupled to each of the second internal terminating resistors via a corresponding second blocking trace.

[0006] Optionally, the number of the second internal terminating resistors is less than or equal to the number of bare dies.

[0007] Optionally, each of the bare dies is provided with a bus pin and coupled to the data bus through the bus pin; each of the second internal terminating resistors is coupled to the bus pin of the corresponding bare die.

[0008] Optionally, at least two bare dies are stacked on the circuit board, and the bus pins of the at least two bare dies are commonly coupled to a second internal terminating resistor.

[0009] Optionally, at least two bare dies are stacked on the circuit board, and the bus pins of the at least two bare dies are respectively coupled to two stacked second internal terminating resistors.

[0010] Optionally, at least two bare dies are stacked on the circuit board, and the bus pins of the at least two bare dies are respectively coupled to two second internal terminating resistors disposed opposite to each other on the circuit board.

[0011] Optionally, each bare die is disposed opposite to the other on the circuit board, and each of the second internal terminating resistors is disposed between adjacent bare dies.

[0012] Optionally, one or more second internal terminating resistors are provided between two adjacent bare dies.

[0013] This application provides a storage device, including a storage chip module as described in any of the preceding claims.

[0014] As described above, in the memory chip module and memory device of this application, the controller is coupled to the internal terminating resistor (i.e., the first internal terminating resistor) within each die through each first blocking trace. Each die is coupled to the controller through each enable line. This allows each internal terminating resistor to correspond to one enable line. When the controller sends an access signal to the target die through the target enable line, the target internal terminating resistor corresponding to the target die remains open under the control of the controller and the first blocking trace. This avoids interference and unnecessary attenuation of the received access signal by the target internal terminating resistor, ensuring that the original amplitude of the access signal is received completely. Even if the opening of the target internal terminating resistor reduces the suppression effect on signal reflection, since the enable lines corresponding to other dies can be logically turned off under the control of the controller, other dies are not affected by signal reflection. Therefore, this application can simultaneously improve signal reflection and attenuation, ensuring complete signal reception. Furthermore, keeping the target internal terminating resistor corresponding to the target die open reduces power consumption. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a memory chip module according to the first embodiment of this application; Figure 2 This is a schematic diagram of the structure of a memory chip module according to the second embodiment of this application.

[0016] Icon labels: The components include: memory chip module 100, circuit board 11, controller 12, bare die / target bare die 13, data bus 14, enable line 15, first internal terminating resistor / target internal terminating resistor 16, first resistor trace 17, first bare die 131, second bare die 132, third bare die 133, first enable line 151, second enable line 152, third enable line 153, first ODT 161, second ODT 162, third ODT 163, first pin / bus pin 13a, second pin 13b, third pin 13c, first ODT trace 171, second ODT trace 172, third ODT trace 173, second internal terminating resistor 18, second resistor trace 19, fourth ODT 181, fifth ODT 182, first ODT trace 191, and second ODT trace 192. Detailed Implementation

[0017] To address the aforementioned problems in the prior art, this application establishes a first blocking trace between the controller and the internal terminating resistors within each die. For a target die receiving an access signal, the corresponding first blocking trace controls the internal terminating resistor (referred to as the target internal terminating resistor) within that target die to remain open, thereby preventing the target internal terminating resistor from interfering with and causing unnecessary attenuation of the receiving access signal, ensuring that the access signal is received completely. Simultaneously, the controller disables other dies from receiving the access signal through the corresponding enable line, which is equivalent to logically disabling the access function of other dies, thus ensuring that other dies are not affected by signal reflection.

[0018] In the memory chip module and memory device of this application, the shape, quantity, size and other forms of various components such as controller, bare die, internal terminating resistor, resistor trace and enable line can be adapted according to actual needs, and this application does not limit them.

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.

[0020] First Embodiment Figure 1 This is a schematic diagram of the structure of a memory chip module according to the first embodiment of this application. Figure 1As shown, the memory chip module 100 includes a circuit board 11, a controller 12, multiple bare dies 13, a data bus 14, multiple enable lines 15, and multiple first internal terminating resistors 16.

[0021] The memory chip module 100 can be implemented as an independent module with data access function. The controller 12, bare die 13, data bus 14, and enable line 15 are respectively coupled to the circuit board 11. The circuit board 11 has a first surface and a second surface arranged opposite to each other along its own thickness direction. According to the placement of the circuit board 11 in the actual scene, the first surface can be called the upper surface, and the second surface can be called the lower surface. The aforementioned components can be coupled to either surface of the circuit board 11, or they can be disposed inside the circuit board 11 to achieve corresponding coupling.

[0022] For example, in practical scenarios, the circuit board 11 may include, but is not limited to, a PCB (Printed Circuit Board) or similar type of circuit board, which has multiple layers of traces (i.e., copper plating). Adjacent layers of traces are insulated from each other by the circuit board material, and different layers of traces are coupled through vias and conductive posts disposed in the vias, thus achieving so-called interlayer coupling. Based on this, the data bus 14 and enable line 15 can be preset traces disposed within the circuit board 11, and the specific form of the data bus 14 and enable line 15 can be determined according to the adaptability of the trace design of the circuit board 11. For example, either the controller 12 or the bare die 13 can be mounted on the circuit board 11 using SMT (Surface Mount Technology), for example, mounted on the first surface of the circuit board 11 and coupled to the data bus 14 of the circuit board 11; the bare die 13 can also be called a storage bare die. Correspondingly, the storage chip module 100 can be regarded as a module integrating 3D NAND flash memory, such as a SATA hard drive. The controller 12 of the SATA hard drive can be divided into a front-end controller and a back-end controller. The front-end controller is connected to the host so that the host can control the storage chip module 100, and the back-end controller is connected to the 3D NAND flash memory to realize data interaction with the 3D NAND flash memory.

[0023] like Figure 1 As shown, on the circuit board 11, the controller 12 and each bare die 13 can be spaced apart. The so-called spaced apart setting means that there is a minimum distance of non-zero between the two main components, that is, the two do not contact each other.

[0024] A single die 13 includes multiple memory layers, such as 32, 64, or a larger number of memory layers, arranged perpendicularly to each other, with each layer containing a number of memory cells. Multiple memory cells of a single die 13 can be accessed in parallel; access includes at least one of reading, writing, and erasing data. The type of each die 13 can be adapted to the type of the memory chip module 100, for example, including but not limited to 3DN NAND (Non-volatile Memory Device) flash memory chips. The type of memory cells in each die 13 can be any of SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), or QLC (Quad-Level Cell). The controller 12 is coupled to each die 13 via a data bus 14 to send access signals to each die 13 to access the memory cells of the corresponding memory layer.

[0025] The memory chip module 100 can be configured according to actual needs to set the number of bare dies 13 and the number of memory cells contained in a single bare die 13. Figure 1 In the example, the memory chip module 100 has three bare dies 13, which is only for illustrative purposes. Further optionally, each bare die 13 may have its own circuit board, which is coupled to the circuit board 11 after molding.

[0026] Continue reading Figure 1 As shown, the number of enable lines 15 can be equal to the number of bare dies 13. Each enable line 15 is connected between the controller 12 and the corresponding bare die 13 to enable the corresponding bare die 13, thereby allowing or disabling the corresponding bare die 13 from receiving access signals issued by the controller 12. Specifically, the controller 12 is coupled to each bare die 13 through each enable line 15. The controller 12 can send a CE signal (Chip Enable signal, i.e., a signal that determines whether the bare die 13 responds to external operations) to the corresponding bare die 13 through each enable line 15. The bare die 13 that receives the CE signal is determined to be able to respond to the relevant instructions transmitted by the data bus 14. The controller 12 can issue relevant instructions containing target data through the data bus 14. The bare die 13 selects the corresponding memory cell, and the memory chip module 100 transmits the target data between the selected bare die 13 and the data bus 14, thereby realizing access. In other examples, the controller 12 can select not only the bare die 13 to be accessed, but also the memory cell within the bare die 13 to be accessed, through the CE signal.

[0027] The number of the first internal terminating resistor 16, the first blocking trace 17, and the bare die 13 can be equal. Multiple first internal terminating resistors 16 are respectively disposed within corresponding bare dies 13, with one first internal terminating resistor 16 disposed within each bare die 13. Each first internal terminating resistor 16 is coupled to the controller 12 via a corresponding first blocking trace 17. The first blocking trace 17 can be a preset trace disposed within the circuit board 11.

[0028] As described above, in the memory chip module 100 of this application, the controller 12 is coupled to the first internal terminating resistor 16 in each bare die 13 through each first blocking trace 17, and each bare die 13 is coupled to the controller 12 through each enable line 15. This allows each first internal terminating resistor 16 to correspond to one enable line 15. When the controller 12 sends an access signal to the target bare die 13 through the target enable line 15, the target internal terminating resistor 16 corresponding to the target bare die 13 remains open under the control of the controller 12 and the first blocking trace 17. This avoids the target internal terminating resistor 16 from interfering with and causing unnecessary attenuation of the access signal being received, thereby ensuring that the original amplitude of the access signal can be received completely. Even if the opening of the target internal terminating resistor 16 reduces the suppression effect on signal reflection, since the enable lines 15 corresponding to other bare dies 13 can be logically turned off under the control of the controller 12, other bare dies 13 will not be affected by signal reflection. Therefore, this application can simultaneously improve the reflection and attenuation of the access signal, ensuring complete reception of the access signal. Furthermore, keeping the internal terminating resistor 16 corresponding to the target bare die 13 in an open state can reduce power consumption.

[0029] The following is combined with Figure 1 The example memory chip module 100 is described in detail in terms of its working principle and process, thereby illustrating the aforementioned technical effects produced by the cooperation of its various components.

[0030] For ease of reading and description, this article will Figure 1 The three bare dies 13 shown are referred to as the first bare die 131, the second bare die 132, and the third bare die 133, respectively. The three enable lines 15 are referred to as the first enable line 151, the second enable line 152, and the third enable line 153, respectively. The three first internal terminating resistors 16 are referred to as the first ODT 161, the second ODT 162, and the third ODT 163, respectively. The three first resistor traces 17 are referred to as the first ODT trace 171, the second ODT trace 172, and the third ODT trace 173, respectively. Each bare die 13 has at least three pins, as shown below. Figure 1The black squares shown are referred to as first pin 13a, second pin 13b, and third pin 13c, respectively. First pin 13a is coupled to data bus 14, second pin 13b is coupled to the corresponding enable line 15, and third pin 13c is coupled to the corresponding first blocking line 17.

[0031] When controller 12 needs to write data to the third die 133 (which is the target die 13) and the third ODT 163 (which is the target internal terminating resistor 16), controller 12 activates the third enable line 153 to send an enable signal to the third die 133, allowing it to receive data. Simultaneously, controller 12 does not activate the first enable line 151 or the second enable line 152, meaning it does not send enable signals to the first die 131 or the second die 132, thus preventing the first die 131 and the second die 132 from receiving data. The controller 12 also controls the third ODT 163 in the third die 133 to disconnect via the third ODT trace 173, and controls the first ODT 161 in the first die 131 and the second ODT 162 in the second die 132 to be turned on via the first ODT trace 171 and the second ODT trace 172, respectively. The access signal containing the data to be written is sent by the controller 12 and transmitted along the data bus 14 to the first die 131, the second die 132 and the third die 133. Ultimately, only the third die 133 can receive the access signal and write data according to the access signal. During this process, although the first die 131 and the second die 132 are prohibited from receiving data, i.e., they cannot receive access signals, the access signals will exist on the data bus 14 that the first die 131 and the second die 132 are respectively coupled to, and will be transmitted to the first pin 13a of the first die 131 and the first pin 13a of the second die 132. If the first ODT 161 and the second ODT 162 are disconnected, the access signals present here will be reflected to form interference signals. The interference signals will be reflected to the third die 133, thereby interfering with the normal signal transmission of the third die 133. This application turns on the first ODT 161 and the second ODT 162, and the two will absorb the access signals they receive, thereby avoiding interference and attenuation to the third die 133, thereby ensuring that the original amplitude of the access signal can be completely received by the third die 133. In addition, keeping the third ODT 163 within the third die 133 disconnected can also avoid additional interference and attenuation to the access signal being received by the third die 133, further ensuring the complete reception of the access signal.

[0032] In practical scenarios, the memory chip module 100 can be manufactured, transported, and sold as an independent device. To meet this independence requirement, the memory chip module 100 may also include a housing that encloses the circuit board 11. Here, the aforementioned devices, including the controller 12 and the bare die 13, are encapsulated within the same housing, thus protecting the entire memory chip module 100. It should be noted that while the housing covers the circuit board 11, external pins are still allowed to be exposed on the circuit board 11, enabling the memory chip module 100 to be coupled to other devices through these external pins.

[0033] Second Embodiment Figure 2 This is a schematic diagram of a memory chip module according to a second embodiment of this application. Structural elements with the same name are identified by the same reference numerals in this application. See also... Figure 2 As shown, based on the description of the first embodiment above, the difference is that the memory chip module 100 of this embodiment further includes at least one second internal terminating resistor 18 and at least one second blocking trace 19. Each second internal terminating resistor 18 is disposed outside any of the aforementioned bare die 13 and is coupled to the data bus 14. The number of second blocking traces 19 is equal to the number of second internal terminating resistors 18. The controller 12 is coupled to each second internal terminating resistor 18 through a corresponding second blocking trace 19.

[0034] Figure 2 The two second internal terminating resistors 18 and the two corresponding second resistor traces 19 shown are merely illustrative examples and do not constitute a limitation on the scope of protection of this application.

[0035] Regarding the memory chip module 100 of the first embodiment described above, actual research and testing revealed that the internal terminating resistors 16 of other dies 13 may not be able to completely absorb the access signal. The incompletely absorbed access signal will be reflected at the corresponding location of other dies 13, thus still causing attenuation and interference to the target die 13 in receiving the access signal. To solve this problem, this embodiment sets a second internal terminating resistor 18 outside any die 13. By turning on the second internal terminating resistor 18, the access signal that is not absorbed by other dies 13 is absorbed, thereby further avoiding interference and attenuation to the target die 13, and further ensuring that the access signal can be completely received by the target die 13.

[0036] The number of second internal terminating resistors 18 can be less than or equal to the number of bare chips 13. For example, combined with Figure 2As shown, in the memory chip module 100 containing three bare dies 13, only two second internal terminating resistors 18 coupled to the data bus 14 are provided, also referred to as the fourth ODT 181 and the fifth ODT 182, respectively. Correspondingly, the memory chip module 100 is provided with two second resistor traces 19, also referred to as the first ODT trace 191 and the second ODT trace 192, respectively. The controller 12 is coupled to the fourth ODT 181 through the first ODT trace 191, and the controller 12 is coupled to the fifth ODT 182 through the second ODT trace 192. Taking the first embodiment described above, with the third die 133 as the target die 13 and the third ODT 163 as the target internal terminating resistor 16 as an example, after the controller 12 sends an access signal, all the second internal terminating resistors 18 are turned on through the corresponding first ODT trace 191 and second ODT trace 192. When the first ODT 161 in the first die 131 and / or the second ODT 162 in the second die 132 cannot completely absorb the access signal, the fourth ODT 181 and the fifth ODT 182 will absorb the unabsorbed access signal, thereby eliminating interference and attenuation to the third die 133.

[0037] In one example, see Figure 2 As shown, in a scenario where the bare dies 13 are positioned opposite each other on the circuit board 11, each second internal terminating resistor 18 can be positioned between adjacent bare dies 13. For example, a fourth ODT 181 can be positioned between the first bare die 131 and the second bare die 132, optionally adjacent to the fourth ODT 181, primarily to absorb access signals not completely absorbed by the first ODT 161 within the first bare die 131; a fifth ODT 182 can be positioned between the second bare die 132 and the third bare die 133, optionally adjacent to the fifth ODT 182, primarily to absorb access signals not completely absorbed by the second ODT 162 within the second bare die 132. Of course, other examples may involve multiple second internal terminating resistors 18 positioned between two adjacent bare dies 13, depending on the adaptability of the bare die 13 arrangement.

[0038] Continue reading Figure 2As shown, given that each die 13 is provided with a bus pin 13a, i.e., a first pin 13a coupled to the data bus 14, in this embodiment, each second internal terminating resistor 18 can also be coupled to the bus pin 13a of the corresponding die 13. This also allows each second internal terminating resistor 18 to be coupled to the data bus 14. For example, the fourth ODT 181 is coupled to the bus pin 13a of the first die 131, and the fifth ODT 182 is coupled to the bus pin 13a of the second die 132. Here, the distance between each second internal terminating resistor 18 and the corresponding die 13 is shorter, allowing for more targeted and better absorption of access signals not fully absorbed by the first internal terminating resistor 16 within the corresponding die 13.

[0039] In one example, all or part of each bare die 13 can be coupled to the circuit board 11 in a stacked manner. In this case, there are at least two bare dies 13 stacked on the circuit board 11. This application allows the bus pins 13a of the stacked bare dies 13 to be commonly coupled to a second internal terminating resistor 18. For example, a first bare die 131 and a second bare die 132 are stacked on the circuit board 11. This application allows the bus pins 13a of both to be commonly coupled to a second internal terminating resistor 18, compared to... Figure 2 As shown in the example, this example can reduce the number of second internal terminating resistors 18, thereby reducing the area occupied by the circuit board 11, which is beneficial for the miniaturization design of the memory chip module 100.

[0040] In another example, for a scenario where at least two bare dies 13 are stacked on the circuit board 11, the bus pins 13a of the at least two stacked bare dies 13 can be coupled one-to-one with two stacked second internal terminating resistors 18. For example, if the first bare die 131 and the second bare die 132 are stacked on the circuit board 11, this application can stack the second internal terminating resistors 18, the fourth ODT 181 and the fifth ODT 182. When the first bare die 131 is stacked on top of the second bare die 132, the fourth ODT 181 can be stacked on top of the fifth ODT 182. Through the stacking of the bare dies 13 and the corresponding stacking of the second internal terminating resistors 18, this example can also reduce the area of ​​the circuit board 11 occupied, which is beneficial for the miniaturization design of the memory chip module 100.

[0041] In another example, in a scenario where at least two bare dies 13 are stacked on the circuit board 11, the bus pins 13a of the at least two stacked bare dies 13 can be coupled one-to-one with two second internal terminating resistors 18 disposed opposite to each other on the circuit board 11. For example, if the first bare die 131 and the second bare die 132 are stacked on the circuit board 11, this application arranges the two second internal terminating resistors 18, the fourth ODT 181 and the fifth ODT 182, opposite to each other, for example, in the same column and between the first bare die 131 (or the second bare die 132) and the third bare die 133. This can also reduce the area of ​​the circuit board 11 occupied, which is beneficial to the miniaturization design of the memory chip module 100.

[0042] This application also provides a storage device, including the storage chip module 100 of any of the foregoing embodiments, and thus can produce the beneficial effects that the storage chip module 100 of the corresponding embodiment can produce.

[0043] This application does not limit the specific type of the storage device. For example, it can be a SATA hard drive. In addition, the circuit board 11 of the aforementioned storage chip module 100 can be part of the circuit board of a serial interface hard drive, or it can be independent of the circuit board of the storage device. The circuit board 11 of the storage chip module 100 can be called a sub-circuit board, and the circuit board of the storage device can be called a main circuit board. The sub-circuit board and the main circuit board are coupled together. The positional relationship between the two is not limited in this application. For example, the sub-circuit board can be smaller, the main circuit board can be larger, and the sub-circuit board can be stacked on the main circuit board.

[0044] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.

[0045] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the technical solutions of the corresponding embodiments, and are not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limitations on this application.

[0046] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A memory chip module, characterized in that, include: The circuit board has a data bus. Multiple bare dies are coupled to the circuit board; A controller is coupled to the circuit board, and the controller is coupled to each of the bare dies via the data bus; Multiple enable lines are disposed on the circuit board, and each enable line is connected between the controller and the corresponding bare die to enable the corresponding bare die; Multiple first internal terminating resistors are respectively disposed in the corresponding bare die, and each first internal terminating resistor is coupled to the controller through a corresponding first resistor trace.

2. The memory chip module according to claim 1, characterized in that, Also includes: At least one second internal terminating resistor, each second internal terminating resistor being coupled to the data bus; At least one second blocking trace is provided, and the controller is coupled to each of the second internal terminating resistors via a corresponding second blocking trace.

3. The memory chip module according to claim 2, characterized in that, The number of the second internal terminating resistors is less than or equal to the number of the bare die.

4. The memory chip module according to claim 2, characterized in that, Each of the bare dies is provided with a bus pin and is coupled to the data bus through the bus pin; each of the second internal terminating resistors is coupled to the bus pin of the corresponding bare die.

5. The memory chip module according to claim 4, characterized in that, The circuit board has at least two bare dies stacked together, and the bus pins of the at least two bare dies stacked together are commonly coupled to a second internal terminating resistor.

6. The memory chip module according to claim 4, characterized in that, The circuit board has at least two bare dies stacked together, and the bus pins of the at least two bare dies stacked together are respectively coupled to two second internal terminating resistors stacked together.

7. The memory chip module according to claim 4, characterized in that, At least two bare dies are stacked on the circuit board, and the bus pins of the at least two bare dies are respectively coupled to two second internal terminating resistors disposed opposite to each other on the circuit board.

8. The memory chip module according to any one of claims 2 to 4, characterized in that, Each bare die is disposed opposite to the other on the circuit board, and each second internal terminating resistor is disposed between adjacent bare dies.

9. The memory chip module according to claim 8, characterized in that, One or more second internal terminating resistors are provided between two adjacent bare dies.

10. A storage device, characterized in that, The memory chip module includes any one of claims 1 to 9.

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