A hardware test platform verification device for a multi-path SPI bus interface

Abstract

This utility model relates to the field of embedded computer technology, specifically a hardware testing platform verification device with a multi-channel SPI bus interface. The device includes a platform body and hardware board units. The platform body includes a communication module, a data analysis module, and a power supply module. The interface terminals of the communication module are connected to the interface terminals of the hardware board units. The output terminal of the communication module is connected to the input terminal of the data analysis module. The power supply module is connected to the power supply input terminals of both the communication module and the data analysis module. This utility model achieves efficient communication between the hardware board units using the communication module, enabling automated testing of peripheral hardware board units. This facilitates advance debugging, and the test results can be directly analyzed in the data analysis module, significantly improving the efficiency of the hardware design verification process for peripheral interfaces.

Description

Technical Field

[0001] This utility model relates to the field of embedded computer technology, specifically to a hardware test platform verification device with a multi-channel SPI bus interface. Background Technology

[0002] With the rapid development of electronic technology, embedded systems, IoT devices, and complex hardware platforms are being used more and more widely. In these systems, hardware design verification and testing are crucial steps to ensure system reliability and functional integrity. Traditional hardware development processes typically rely on manual debugging and generic testing tools, which are inefficient and fail to meet the demands of modern hardware development for rapid iteration and high reliability.

[0003] Verifying the peripheral SPI bus interface is a critical and complex task in the hardware design process. Existing verification methods typically rely on dedicated equipment or manual operation, which not only increases development costs but may also lead to insufficient test coverage and difficulty in discovering potential design flaws. The difficulty of hardware verification is further increased, especially in scenarios involving multi-bus collaboration and complex interactions. Utility Model Content

[0004] The purpose of this utility model is to provide a solution that overcomes the shortcomings of the prior art.

[0005] This utility model provides a hardware test platform verification device with a multi-channel SPI bus interface, characterized in that it includes a platform body and a hardware board unit, wherein the platform body includes a communication module, a data analysis module and a power supply module. The interface terminals of the communication module are respectively connected to the interface terminals of the hardware board unit; the output terminal of the communication module is connected to the input terminal of the data analysis module. The power module is connected to the power input terminals of the communication module and the data analysis module, respectively.

[0006] Preferably, the hardware board unit includes a first hardware board and a second hardware board; the interface ends of the first hardware board and the second hardware board are connected to the interface end of the communication module.

[0007] Furthermore, the communication module includes a first communication submodule and a second communication submodule; The interface of the first communication submodule is connected to the interface of the first hardware board; The interface of the second communication submodule is connected to the interface of the second hardware board; The first communication submodule and the second communication submodule are electrically connected.

[0008] Furthermore, the first communication submodule includes a first FPGA, a first clock circuit, a first reset circuit, and a first JTAG emulation and debugging interface; The interface of the first hardware board is connected to the interface of the first FPGA, and the control terminal of the first FPGA is connected to the control terminal of the first clock circuit, the first reset circuit, and the first JTAG emulation and debugging interface.

[0009] Furthermore, the interface of the first FPGA and the interface of the first hardware board are connected via SCK signal line, MOSI signal line, MISO signal line and NSS signal line respectively.

[0010] Furthermore, the second communication submodule includes a second FPGA, a second clock circuit, a second reset circuit, and a second JTAG emulation and debugging interface; The interface of the second hardware board is connected to the interface of the second FPGA, and the control terminal of the second FPGA is connected to the control terminal of the second clock circuit, the second reset circuit, and the second JTAG emulation and debugging interface.

[0011] Furthermore, the interface of the second FPGA is connected to the interface of the second hardware board via SCK signal line, MOSI signal line, MISO signal line and NSS signal line respectively.

[0012] Preferably, the data analysis module includes a CPU, a third clock circuit, a third reset circuit, and a serial port driver circuit; The output of the communication module is connected to the interface of the CPU, and the control terminal of the CPU is connected to the third clock circuit, the third reset circuit and the serial port driver circuit respectively.

[0013] Preferably, the power module includes interconnected DC / DC power supply units and filters.

[0014] Preferably, one end of the power module is connected to a DC power supply, and the other end is grounded.

[0015] Compared with the prior art, the present invention has the following beneficial technical effects: This invention provides a hardware testing platform verification device with a multi-channel SPI bus interface. By utilizing the communication module to achieve efficient communication between hardware board units, it enables automated testing of peripheral hardware board units, facilitating advance debugging. The test results can be directly analyzed in the data analysis module, greatly improving the efficiency of the hardware design verification process of peripheral interfaces.

[0016] Furthermore, the hardware board unit includes a first hardware board and a second hardware board; the interface ends of the first hardware board and the second hardware board are connected to the interface end of the communication module, which effectively realizes the testing of multiple hardware boards and greatly improves the testing efficiency.

[0017] Furthermore, the communication module includes a first communication submodule and a second communication submodule; the interface of the first communication submodule is connected to the interface of the first hardware board; the interface of the second communication submodule is connected to the interface of the second hardware board; the first communication submodule and the second communication submodule are electrically connected to each other; the communication module is provided with communication submodules corresponding to multiple hardware boards, and each communication submodule can independently input information to each hardware board, avoiding information data input errors and improving the overall accuracy of information input.

[0018] Furthermore, the communication submodule includes an FPGA, clock circuit, reset circuit, and JTAG simulation and debugging interface, which enables the received data from the hardware board to be sent quickly and accurately to the data analysis module, greatly improving the efficiency of the hardware design and verification process of the peripheral interface.

[0019] Furthermore, the data analysis module includes a CPU, a third clock circuit, a third reset circuit, and a serial port driver circuit. The CPU, third clock circuit, third reset circuit, and serial port driver circuit are used to analyze the received data, which improves the efficiency of the hardware design verification process. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the hardware test platform verification device for the multi-channel SPI bus interface in this embodiment of the present invention. Figure 2 This is a schematic diagram of the principle structure of the communication module in an embodiment of this utility model; Figure 3 This is a schematic diagram of the principle structure of the first communication submodule in this embodiment of the present invention; Figure 4 This is a schematic diagram of the principle structure of the second communication submodule in this embodiment of the present invention; Figure 5 This is a schematic diagram of the principle structure of the data analysis module in this embodiment of the utility model; Figure 6 This is a schematic diagram of the principle structure of the power module in an embodiment of this utility model; In the diagram: 1. Platform body; 2. Hardware board unit; 11. Communication module; 12. Data analysis module; 13. Power supply module; 21. First hardware board; 22. Second hardware board; 111. First communication submodule; 112. Second communication submodule; 1111, First FPGA; 1112, First clock circuit; 1113, First reset circuit; 1114, First JTAG emulation and debugging interface; 1121. Second FPGA; 1122. Second clock circuit; 1123. Second reset circuit; 1124. Second JTAG emulation and debugging interface; 131. DC / DC power supply unit; 132. Filter. Detailed Implementation

[0021] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this invention. Therefore, the drawings and description are considered exemplary in nature and not restrictive.

[0022] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0025] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0026] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0027] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0028] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] The accompanying drawings show various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0030] according to Figure 1As shown, this utility model provides a hardware test platform verification device with a multi-channel SPI bus interface, including a platform body 1 and a hardware board unit 2. The platform body includes a communication module 11, a data analysis module 12, and a power supply module 13. The interface terminals of the communication module 11 are respectively connected to the interface terminals of the hardware board unit 2. The output terminal of the communication module 11 is connected to the input terminal of the data analysis module 12. The power supply module 13 is respectively connected to the power supply input terminals of the communication module 11 and the data analysis module 12.

[0031] In this embodiment, the communication module 11 is used to interact with the hardware board unit 2 via a multi-channel SPI bus, generate standardized test cases, communicate with the hardware under test, and generate test instructions.

[0032] In this embodiment, the data analysis module 12 is used to collect, store and analyze test data in real time, and analyze and judge the response of the hardware under test to quickly locate potential problems.

[0033] In this embodiment, the power module 13 is used to supply power to the communication module 11 and the data analysis module 12.

[0034] Specifically, the hardware board unit 2 includes a first hardware board 21 and a second hardware board 22; the interface ends of the first hardware board 21 and the second hardware board 22 are connected to the interface end of the communication module 11.

[0035] Specifically, according to Figure 2 As shown, the communication module 11 includes a first communication submodule 111 and a second communication submodule 112; the interface end of the first communication submodule 111 is connected to the interface end of the first hardware board 21; the interface end of the second communication submodule 112 is connected to the interface end of the second hardware board 22; the first communication submodule 111 and the second communication submodule 112 are electrically connected to each other.

[0036] Among them, according to Figure 3 As shown, the first communication submodule 111 includes a first FPGA 1111, a first clock circuit 1112, a first reset circuit 1113, and a first JTAG emulation and debugging interface 1114; the interface end of the first hardware board 21 is connected to the interface end of the first FPGA 1111, and the control end of the first FPGA 1111 is connected to the control end of the first clock circuit 1112, the first reset circuit 1113, and the first JTAG emulation and debugging interface 1114.

[0037] The interface of the first FPGA 1111 is connected to the interface of the first hardware board 21 via SCK signal line, MOSI signal line, MISO signal line and NSS signal line respectively.

[0038] Specifically, according to Figure 4 As shown, the second communication submodule 112 includes a second FPGA 1121, a second clock circuit 1122, a second reset circuit 1123, and a second JTAG emulation and debugging interface 1124; the interface end of the second hardware board 22 is connected to the interface end of the second FPGA 1121, and the control end of the second FPGA 1121 is connected to the control end of the second clock circuit 1122, the second reset circuit 1123, and the second JTAG emulation and debugging interface 1124.

[0039] The interface of the second FPGA 1121 is connected to the interface of the second hardware board 22 via SCK signal line, MOSI signal line, MISO signal line and NSS signal line respectively.

[0040] Among them, according to Figure 5 As shown, the data analysis module 12 includes a CPU 121, a third clock circuit 122, a third reset circuit 123, and a serial port driver circuit 124; the output terminal of the communication module 11 is connected to the interface terminal of the CPU 121, and the control terminal of the CPU 121 is connected to the third clock circuit 122, the third reset circuit 123, and the serial port driver circuit 124 respectively.

[0041] Specifically, according to Figure 6 As shown, the power module 13 includes a DC / DC power supply unit 131 and a filter 132 that are interconnected.

[0042] Specifically, one end of the power module 13 is connected to a DC power supply terminal, where the voltage of the DC power supply terminal is 28V; the other end is grounded.

[0043] The hardware test platform verification device with a multi-channel SPI bus interface provided by this utility model, when in use: Determine the type of hardware board unit 2 and configure the SPI bus parameters; Users input test tasks and load test cases through a host computer or control interface; the system parses the test tasks and generates corresponding SPI communication commands.

[0044] Initialize SPI bus communication. Communication module 11 sends configuration or operation commands to the target hardware via the SPI bus. After the target hardware responds, it sends data back to communication module 11 via the SPI bus, recording the timing, waveform and data content during the communication process.

[0045] The data analysis module analyzes the acquired SPI communication data and extracts key parameters; the rapid verification platform generates a test report, which includes pass / fail status, detailed data records and possible causes of failure, and allows for further optimization or adjustment of the hardware design as needed.

[0046] In summary, this utility model provides a hardware testing platform verification device with a multi-channel SPI bus interface. By utilizing the communication module to achieve efficient communication between hardware board units, it enables automated testing of peripheral hardware board units, facilitating advance debugging. The test results can be directly analyzed in the data analysis module, greatly improving the efficiency of the hardware design verification process for peripheral interfaces.

[0047] This platform is widely used in hardware development, system integration, and maintenance. For example, during the hardware R&D phase, it is used to quickly verify the functionality and performance of new designs. In production testing, it is used to batch test the yield of hardware devices. During system maintenance, it is used to diagnose and repair hardware faults. Through these specific implementations, this invention provides an efficient and reliable rapid hardware verification platform that can significantly improve hardware development efficiency and ensure system reliability.

[0048] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A hardware test platform verification device with a multi-channel SPI bus interface, characterized in that, It includes a platform body (1) and a hardware board unit (2). The platform body includes a communication module (11), a data analysis module (12) and a power module (13). The interface of the communication module (11) is connected to the interface of the hardware board unit (2); the output of the communication module (11) is connected to the input of the data analysis module (12). The power module (13) is connected to the power input terminals of the communication module (11) and the data analysis module (12), respectively.

2. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 1, characterized in that, The hardware board unit (2) includes a first hardware board (21) and a second hardware board (22); the interface ends of the first hardware board (21) and the second hardware board (22) are connected to the interface end of the communication module (11).

3. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 2, characterized in that, The communication module (11) includes a first communication submodule (111) and a second communication submodule (112); The interface of the first communication submodule (111) is connected to the interface of the first hardware board (21); The interface of the second communication submodule (112) is connected to the interface of the second hardware board (22); The first communication submodule (111) and the second communication submodule (112) are electrically connected.

4. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 3, characterized in that, The first communication submodule (111) includes a first FPGA (1111), a first clock circuit (1112), a first reset circuit (1113), and a first JTAG emulation and debugging interface (1114). The interface of the first hardware board (21) is connected to the interface of the first FPGA (1111), and the control terminal of the first FPGA (1111) is connected to the control terminal of the first clock circuit (1112), the first reset circuit (1113), and the first JTAG emulation and debugging interface (1114).

5. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 4, characterized in that, The interface of the first FPGA (1111) is connected to the interface of the first hardware board (21) through the SCK signal line, MOSI signal line, MISO signal line and NSS signal line respectively.

6. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 3, characterized in that, The second communication submodule (112) includes a second FPGA (1121), a second clock circuit (1122), a second reset circuit (1123), and a second JTAG emulation and debugging interface (1124). The interface of the second hardware board (22) is connected to the interface of the second FPGA (1121), and the control terminal of the second FPGA (1121) is connected to the control terminal of the second clock circuit (1122), the second reset circuit (1123) and the second JTAG simulation and debugging interface (1124).

7. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 6, characterized in that, The interface of the second FPGA (1121) is connected to the interface of the second hardware board (22) through the SCK signal line, MOSI signal line, MISO signal line and NSS signal line respectively.

8. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 1, characterized in that, The data analysis module (12) includes a CPU (121), a third clock circuit (122), a third reset circuit (123), and a serial port driver circuit (124). The output of the communication module (11) is connected to the interface of the CPU (121), and the control terminal of the CPU (121) is connected to the third clock circuit (122), the third reset circuit (123) and the serial port driver circuit (124) respectively.

9. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 1, characterized in that, The power module (13) includes a DC / DC power supply unit (131) and a filter (132) that are interconnected.

10. The hardware test platform verification device for a multi-channel SPI bus interface according to claim 1, characterized in that, One end of the power module (13) is connected to a DC power supply, and the other end is grounded.

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