A direct current circuit topology of an energy storage system and an energy storage system

Abstract

The utility model discloses a kind of direct current circuit topological structure of energy storage system and energy storage system, direct current circuit topological structure is connected between the energy storage device and bus capacitor of energy storage system, comprising: first main relay, first main relay is connected between the anode of energy storage device and the anode of bus capacitor;Second main relay, second main relay is connected between the cathode of energy storage device and the cathode of bus capacitor;Pre-charge branch, pre-charge branch is connected between the anode of energy storage device and bus capacitor, to provide pre-charge current path;Pre-charge branch includes buffer unit, buffer unit has controlled semiconductor device or energy storage element, to inhibit the impact current flowing through pre-charge branch.By having the buffer unit of controlled semiconductor device or energy storage element, to be equivalent to resistance adjustable resistance, it is favorable to avoid in pre-charge branch instant on to buffer unit cause transient power impact, to reduce the risk of thermal impact fatigue accumulation and burn loss.

Description

Technical Field

[0001] This utility model relates to the field of energy storage technology, and in particular to a DC circuit topology for an energy storage system and an energy storage system. Background Technology

[0002] In energy storage systems, pre-charging the DC bus capacitor is a necessary pre-conditioning step for closing the main relay. Related technologies typically employ a branch where a pre-charging resistor is connected in series with the pre-charging relay, using the resistor to limit inrush current.

[0003] However, the pre-charge resistor will be subjected to instantaneous power surges at the moment of connection. Frequent pre-charging can easily lead to thermal shock fatigue accumulation in the pre-charge resistor, and even cause the risk of burnout. Furthermore, the pre-charge resistor must be selected with high power specifications, resulting in a large size, which is contrary to the development trend of high power density and high integration of energy storage systems. Moreover, when the resistor fails, there is a lack of effective online detection methods in related technologies, making fault location difficult. In addition, related technologies rely on software logic to determine whether the pre-charge stage has ended. Software abnormalities may lead to uncontrolled pre-charge or misjudgment, resulting in low reliability. Utility Model Content

[0004] One objective of this invention is to provide a DC circuit topology for an energy storage system that can solve or mitigate at least one of the defects in the aforementioned background technology.

[0005] Another objective of this invention is to provide an energy storage system having the aforementioned DC circuit topology, in order to solve or mitigate at least one of the defects in the aforementioned background technology.

[0006] The first aspect of this utility model provides a DC circuit topology for an energy storage system. The DC circuit topology connects the energy storage device and the bus capacitor of the energy storage system, and includes: a first main relay connected between the positive terminal of the energy storage device and the positive terminal of the bus capacitor; a second main relay connected between the negative terminal of the energy storage device and the negative terminal of the bus capacitor; and a pre-charge branch connected between the positive terminal of the energy storage device and the bus capacitor to provide a pre-charge current path. The pre-charge branch includes a buffer unit having a controlled semiconductor device or energy storage element to suppress inrush current flowing through the pre-charge branch.

[0007] As a preferred embodiment, the pre-charge branch is connected in parallel with the first main relay, and the buffer unit includes the controlled semiconductor device, which is connected in series in the pre-charge branch. By adjusting the conduction state of the controlled semiconductor device, the inrush current flowing through the pre-charge branch is suppressed.

[0008] As a preferred embodiment, the controlled semiconductor device has a first electrode, a second electrode, and a control terminal. The first electrode is connected to the positive terminal of the energy storage device, and the second electrode is connected to the positive terminal of the bus capacitor. The controlled semiconductor device is configured to regulate the current flowing between the first electrode and the second electrode by changing the voltage of the control terminal.

[0009] As a preferred embodiment, the precharge branch further includes an auxiliary relay connected in series with the controlled semiconductor device to disconnect the precharge branch at the end of the precharge phase.

[0010] As a preferred embodiment, the controlled semiconductor device operates in linear amplification mode during the pre-charge phase, and the current flowing through the pre-charge branch is adjusted by controlling the conduction level of the controlled semiconductor device.

[0011] As a preferred embodiment, the controlled semiconductor device operates in pulse width modulation mode during the precharge phase, and the average current flowing through the precharge branch is adjusted by controlling the switch duty cycle.

[0012] As a preferred embodiment, the pre-charge branch is connected in parallel with the first main relay, and the buffer unit includes a pre-charge inductor connected in series in the pre-charge branch; the pre-charge branch also includes an auxiliary relay connected in series with the pre-charge inductor to disconnect the pre-charge branch at the end of the pre-charge phase.

[0013] As a preferred embodiment, the buffer unit further includes a diode, the anode of which is connected to the node between the pre-charge inductor and the bus capacitor, and the cathode of which is connected to the node between the pre-charge inductor and the auxiliary relay.

[0014] As a preferred embodiment, the buffer unit includes an auxiliary capacitor, a first switching switch, and a second switching switch. The auxiliary capacitor is connected in series with the first switching switch and then connected between the positive and negative terminals of the energy storage device. The two ends of the auxiliary capacitor are connected in parallel with the bus capacitor through the second switching switch. When the first switching switch is closed and the second switching switch is open, the energy storage device charges the auxiliary capacitor. When the first switching switch is open and the second switching switch is closed, the auxiliary capacitor precharges the bus capacitor.

[0015] The second aspect of this utility model provides an energy storage system, comprising: a DC circuit topology as described above; a controller connected to a first main relay, a second main relay, and a pre-charge branch of the DC circuit topology to control the conduction and disconnection of the first main relay, the second main relay, and the pre-charge branch; and a sampling module connected to both ends of a bus capacitor to collect bus voltage and feed it back to the controller.

[0016] Compared with the prior art, the beneficial effects of this utility model are as follows: By using a buffer unit with controlled semiconductor devices or energy storage elements, it can be equivalent to a resistor with adjustable resistance. This helps to gradually increase the current in the precharge branch from zero or keep it at a small value after the precharge branch is turned on. In other words, replacing the passive resistor (i.e., the precharge resistor) in related technologies with a buffer unit helps to avoid instantaneous power surges to the buffer unit at the moment the precharge branch is turned on, thereby reducing the risk of thermal shock fatigue accumulation and burn-out. It can withstand more precharge cycles, extend its service life, and improve the reliability of the energy storage system. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a DC circuit topology according to some embodiments of this application. Detailed Implementation

[0018] The present invention will be further described below with reference to specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0019] In the description of this utility model, it should be noted that the directional terms such as "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", and "counterclockwise" are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific protection scope of this utility model.

[0020] It should be noted that the terms "first" and "second" in the specification and claims of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0021] A DC circuit topology for an energy storage system, such as Figure 1As shown, the DC circuit topology is connected to the energy storage device and the bus capacitor C of the energy storage system. dc This includes: a first main relay K1, a second main relay K2, and a pre-charge branch. Specifically, the first main relay K1 is connected to the positive terminal of the energy storage device and the bus capacitor C. dc The positive terminal is connected to the negative terminal of the energy storage device; the second main relay K2 is connected to the negative terminal of the energy storage device and the bus capacitor C. dc Between the negative terminals; the pre-charge branch is connected to the positive terminal of the energy storage device and the bus capacitor C. dc A pre-charge current path is provided between the two branches; the pre-charge branch includes a buffer unit having a controlled semiconductor device M1 or an energy storage element to suppress the inrush current flowing through the pre-charge branch. The energy storage device can be the DC power source of the energy storage system, such as a battery cluster consisting of multiple cells connected in series.

[0022] It can be understood that a buffer unit with a controlled semiconductor device M1 or an energy storage element can be equivalent to a resistor with an adjustable resistance. This helps to gradually increase the current in the pre-charge branch from zero or maintain a small value after the pre-charge branch is turned on. In other words, replacing the passive resistor (i.e., the pre-charge resistor) in related technologies with a buffer unit helps to avoid instantaneous power surges to the buffer unit at the moment the pre-charge branch is turned on, thereby reducing the risk of thermal shock fatigue accumulation and burn-out. This allows the system to withstand more pre-charge cycles, extends its service life, and improves the reliability of the energy storage system.

[0023] It is worth mentioning that replacing passive resistors with smaller controlled semiconductor devices M1 or energy storage elements reduces the size of the buffer unit, making the overall structure of the energy storage system more compact. Furthermore, as mentioned earlier, the heat generation of the buffer unit is controllable, eliminating the need for additional heat dissipation structures, thereby reducing the material costs, heat dissipation costs, and maintenance costs of the energy storage system.

[0024] In some embodiments, the precharge branch is connected in parallel with the first main relay K1, and the buffer unit includes a controlled semiconductor device M1 connected in series in the precharge branch. By adjusting the conduction state of the controlled semiconductor device M1, the inrush current flowing through the precharge branch is suppressed.

[0025] It is understandable that by adjusting the conduction level of the controlled semiconductor device M1, that is, by adjusting the resistance value of the equivalent resistance of the controlled semiconductor device M1, the current in the precharge branch can be gradually increased from zero, or the current in the precharge branch can be maintained at a small value, which helps to eliminate instantaneous power spikes, thereby reducing the risk of thermal shock fatigue accumulation and burn-out.

[0026] In some embodiments, the controlled semiconductor device M1 has a first electrode, a second electrode, and a control terminal. The first electrode is connected to the positive terminal of the energy storage device, and the second electrode is connected to the bus capacitor C.dc With the positive terminal connected, the controlled semiconductor device M1 is configured to regulate the current flowing between the first and second terminals by changing the voltage at the control terminal.

[0027] In at least one embodiment, the controlled semiconductor device M1 is implemented as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Specifically, the drain D of the MOSFET is connected to the positive terminal of the energy storage device, and the source S is connected to the bus capacitor C. dc The positive terminal of the MOSFET is connected, and the voltage of the gate G is controlled to turn the MOSFET on or off. Furthermore, the on-resistance of the MOSFET is adjusted to keep the current flowing through the drain D and source S of the MOSFET at a low value, which helps to eliminate instantaneous power spikes. Preferably, the controlled semiconductor device M1 is implemented as a SiC MOSFET to have better peak power tolerance, suitable for high-voltage energy storage systems, such as energy storage systems with a rated voltage greater than or equal to 1500V.

[0028] In at least one embodiment, the controlled semiconductor device M1 is implemented as a JFET (Junction Field-Effect Transistor). Specifically, the gate driving method of a JFET is relatively simple, making it suitable for applications that are sensitive to the complexity, power consumption, and cost of the driving circuit, thereby simplifying the driving design and reducing the overall complexity and manufacturing cost of the energy storage system.

[0029] In some embodiments, the pre-charge branch also includes an auxiliary relay K3, which is connected in series with the controlled semiconductor device M1 to disconnect the pre-charge branch at the end of the pre-charge phase. It should be understood that this arrangement physically isolates the controlled semiconductor device M1 from the main circuit after the pre-charge phase, which helps to avoid backflow of bus voltage or long-term high-voltage stress on the controlled semiconductor device M1 from the DC bus, thereby reducing the risk of safety hazards caused by leakage current of the controlled semiconductor device M1 and reducing standby power consumption. Furthermore, in the event of an accidental short circuit or other fault in the controlled semiconductor device M1, the auxiliary relay K3 reliably disconnects the pre-charge circuit to achieve fault isolation, improving the safety and reliability of the energy storage system.

[0030] In other embodiments, the auxiliary relay K3 is omitted from the pre-charge branch; in other words, at the end of the pre-charge phase, the pre-charge branch is switched off simply by disconnecting the controlled semiconductor device M1, equivalent to a fully solid-state pre-charge scheme. It should be understood that this arrangement reduces the number of components, thereby reducing size and cost. Specifically, the scheme that omits the auxiliary relay K3 in the pre-charge branch and only includes the controlled semiconductor device M1 is suitable for low-voltage energy storage systems with lower requirements for electrical isolation and fault redundancy; furthermore, the reliable shutdown of the controlled semiconductor device M1 can be ensured through software settings.

[0031] In some embodiments, the controlled semiconductor device M1 operates in linear amplification mode during the pre-charge phase. By controlling the conduction level of the controlled semiconductor device M1, the current flowing through the pre-charge branch is regulated. It should be understood that by slowly increasing the gate voltage to regulate the conduction level of the controlled semiconductor device M1, the equivalent resistance of the controlled semiconductor device M1 gradually and smoothly decreases from a high-resistance state. This allows the current in the pre-charge branch to gradually increase from zero, or to maintain the current in the pre-charge branch at a low value. This helps to eliminate instantaneous power spikes, thereby reducing the risk of thermal shock fatigue accumulation and burn-out.

[0032] Taking the controlled semiconductor device M1 described above as a MOSFET as an example, by controlling the gate voltage to rise slowly from the threshold voltage, the on-resistance of the MOSFET can be gradually reduced from a high-resistance state to full conduction. For example, the on-resistance of the MOSFET can be reduced from the level of several ohms to the level of milliohms, thereby regulating the current flowing through the precharge branch, that is, the current flowing through the drain D and source S of the MOSFET.

[0033] Specifically, the current value I in the pre-charge branch at time t. pre (t)=(V bat -V dc (t)) / R ds (t), where V bat V represents the voltage value of the energy storage device. dc (t) represents the bus voltage at time t, R ds (t) represents the on-resistance of the MOSFET at time t. At the initial moment of the pre-charge phase, the bus voltage value V... dc (t)≈0, MOSFET on-resistance R ds (t) is larger, so that the current value I in the pre-charge branch is larger. pre (t) is limited to a small value, such as 15A; furthermore, as the bus voltage value V dc As (t) gradually increases, the on-resistance R of the MOSFET... ds (t) gradually decreases, thus maintaining the current value I. pre The smooth stability of (t) keeps it at a small value.

[0034] It is worth mentioning that the passive resistor solution used in related technologies has its limitations. Since the passive resistor itself generates a voltage drop, it is difficult to make the voltage across the contacts of the relay on the positive busbar completely consistent. In other words, it is difficult to achieve zero-impact switching of the relay on the positive busbar. In this embodiment, when the pre-charge stage is completed, the on-resistance of the controlled semiconductor device M1 is extremely small, and the voltage difference across the pre-charge circuit is approximately zero. This makes the voltage difference across the contacts of the first main relay K1 approximately zero, which helps to avoid electrical impacts such as arcing and surges during closing. This allows for low-impact or even zero-impact switching of the first main relay K1, thereby extending the electrical life of the first main relay K1.

[0035] In some embodiments, the DC circuit topology further includes a drive control circuit that provides a voltage to the control terminal of the controlled semiconductor device M1 to control the transition rate of the controlled semiconductor device M1 from off to fully on.

[0036] In at least one embodiment, the drive control circuit employs an RC (Resistance-Capacitance) delay circuit or an analog integrator circuit. It should be understood that using a purely hardware-based drive control circuit helps ensure control timing at the hardware level, reducing the risk of pre-charge runaway due to software crashes or communication delays, thereby improving the safety and reliability of the energy storage system. It is worth mentioning that the operating state of the controlled semiconductor device M1, such as the drive voltage at the control terminal, the on-state voltage drop, and the pre-charge branch current, can all be directly monitored through hardware, facilitating clear fault location.

[0037] In at least one embodiment, the drive control circuit employs an MCU (Microcontroller Unit) or DSP (Digital Signal Processor) to provide a curve that causes the gate voltage to rise slowly to the control terminal of the controlled semiconductor device M1 via a software algorithm. It should be understood that this setup allows for flexible programming of the curve, thereby adapting to the voltage levels and bus capacitance C of different energy storage systems. dc The capacity helps to optimize the balance between the duration of the precharge phase and the power loss of the controlled semiconductor device M1.

[0038] In some embodiments, the controlled semiconductor device M1 operates in pulse width modulation (PWM) mode during the pre-charge phase, and the average current flowing through the pre-charge branch is adjusted by controlling the switching duty cycle. It should be understood that the controlled semiconductor device M1 operates in a switching state at this time, and by adjusting the duty cycle of the PWM signal, the on-time of the controlled semiconductor device M1 can be flexibly controlled, thereby adjusting the average current flowing through the pre-charge branch to keep the average current within a reasonable range.

[0039] It is worth mentioning that this configuration reduces the conduction losses of the controlled semiconductor device M1 and reduces heat generation, thereby allowing for the use of smaller packaged devices and simplifying the heat dissipation configuration. Furthermore, the pre-charge branch can further include a filter inductor to work with the controlled semiconductor device M1 to output a smooth current.

[0040] In at least one embodiment, the drive control circuit uses a hardware PWM circuit to generate the PWM signal. It should be understood that a hardware PWM circuit has a simple structure, good real-time performance, and can achieve switching control of the controlled semiconductor device M1 at a lower cost. In at least one other embodiment, the drive control circuit uses an MCU or DSP to generate the PWM signal through a software algorithm.

[0041] In some embodiments, the precharge branch is connected in parallel with the first main relay K1, and the buffer unit includes a precharge inductor connected in series in the precharge branch; the precharge branch also includes an auxiliary relay K3 connected in series with the precharge inductor to disconnect the precharge branch at the end of the precharge phase.

[0042] It should be understood that this embodiment utilizes the physical characteristic that the current of the pre-charge inductor cannot change abruptly, allowing the circuit to smoothly rise from zero. This helps eliminate instantaneous power spikes and reduces the risk of thermal shock fatigue accumulation and burn-out. Furthermore, this circuit structure is simple, reliable, and less expensive. Moreover, after the pre-charge phase ends, disconnecting the auxiliary relay K3 physically isolates the pre-charge inductor from the main circuit, which helps avoid continuous losses and voltage drops caused by the DC resistance of the pre-charge inductor.

[0043] In some embodiments, the buffer unit further includes a diode, the anode of which is connected to the pre-charge inductor and the bus capacitor C. dcThe cathode of the diode is connected to the node between the pre-charge inductor and the auxiliary relay K3. It should be understood that when the auxiliary relay K3 is disconnected after the pre-charge phase, the pre-charge inductor will generate a reverse induced electromotive force. In this embodiment, the freewheeling path formed by the diode helps to avoid high-voltage spikes, thereby reducing the risk of voltage breakdown of the auxiliary relay K3 and the pre-charge inductor; simultaneously, the remaining energy in the pre-charge inductor can be safely released through the freewheeling path, helping to prevent damage to the bus capacitor C. dc This creates a reverse impact, further improving the reliability and safety of the pre-charge branch.

[0044] In some embodiments, the buffer unit includes an auxiliary capacitor, a first switching switch, and a second switching switch. The auxiliary capacitor and the first switching switch are connected in series between the positive and negative terminals of the energy storage device. The two ends of the auxiliary capacitor are connected to the bus capacitor C through the second switching switch. dc Parallel connection; when the first switching switch is closed and the second switching switch is open, the energy storage device charges the auxiliary capacitor; when the first switching switch is open and the second switching switch is closed, the auxiliary capacitor charges the bus capacitor C. dc Pre-charge.

[0045] It is understandable that the auxiliary capacitor is first charged to the battery voltage using a small current, and then the auxiliary capacitor is connected to the bus capacitor C. dc Parallel connection can utilize the charge balance between capacitors to achieve the bus capacitance C. dc Zero-impact charging. Furthermore, this circuit structure is simple, reliable, and lower in cost, making it suitable for applications where cost is a concern but space is ample.

[0046] An energy storage system, such as Figure 1 As shown, it includes: the aforementioned DC circuit topology, a controller, and a sampling module. Specifically, the controller is connected to the first main relay K1, the second main relay K2, and the pre-charge branch of the DC circuit topology to control the on and off states of the first main relay K1, the second main relay K2, and the pre-charge branch; the sampling module is connected to the bus capacitor C. dc At both ends, the bus voltage can be collected and fed back to the controller.

[0047] Specifically, taking the pre-charge branch of the DC circuit topology, which includes the controlled semiconductor device M1 and the auxiliary relay K3, as an example, in the first stage: the controller issues a command to close the second main relay K2, thereby establishing a common reference ground between the negative terminal of the energy storage device and the negative busbar; at this time, the second main relay K2 and the pre-charge branch are both open, and there is no current in the pre-charge branch and the main circuit.

[0048] Second stage: The controller issues a command to close the auxiliary relay K3, so that the pre-charge branch forms a mechanical path; at this time, the controlled semiconductor device M1 is still in the off state, and there is no current in the pre-charge branch and the main circuit; since the auxiliary relay K3 closes under zero current conditions, it helps to avoid arcing at the contacts of the auxiliary relay K3.

[0049] The third stage: The controller drives the aforementioned drive control circuit to output a drive voltage to the control terminal of the controlled semiconductor device M1, causing the voltage at the control terminal to rise slowly from zero in a ramp-like manner. For example, the rise time can be 50ms to 200ms. As a result, the equivalent resistance of the controlled semiconductor device M1 gradually and smoothly decreases from a high resistance state. At the same time, the current in the pre-charge branch smoothly rises from zero to the target value, such as 15A, thereby affecting the bus capacitor C. dc Charge it.

[0050] The fourth stage: The controller compares the bus voltage with a preset threshold. When the bus voltage reaches the preset threshold, the pre-charging stage is considered complete. The preset threshold can be determined based on the rated voltage of the energy storage device; for example, it can be set to 85% to 95% of the rated voltage. At this point, the on-resistance of the controlled semiconductor device M1 is extremely low, and the voltage difference across the pre-charging circuit is approximately zero, making the voltage difference across the contacts of the first main relay K1 approximately zero as well.

[0051] Fifth stage: The controller issues a command to close the first main relay K1. Since the voltage difference across the contacts of the first main relay K1 is approximately zero, it helps to avoid electrical shocks such as arcs and surges, thus achieving low-impact or even zero-impact switching of the main circuit. In other words, this setting helps to eliminate the electrical shock when the first main relay K1 is closed under load, thereby extending the electrical life of the first main relay K1.

[0052] Sixth stage: The controller removes the drive voltage to the control terminal of the controlled semiconductor device M1 by the drive control circuit, so that the controlled semiconductor device M1 is disconnected; and the controller issues a command to disconnect the auxiliary relay K3.

[0053] Furthermore, the controller can unblock the output of the PCS (Power Conversion System) to allow the PCS to perform DC-AC conversion, thereby enabling power feeding to or drawing power from the grid.

[0054] In at least one embodiment, such as Figure 1 As shown, the sampling module can collect the voltage at voltage sampling point A and voltage sampling point B, where voltage sampling point A is the two ends of the energy storage device, and voltage sampling point B is the bus capacitor C. dcThe sampling module can feed back the voltage at both ends of the energy storage device and the bus voltage to the controller so that the controller can compare and determine whether the pre-charging stage is complete.

[0055] The basic principles, main features, and advantages of this utility model have been described above. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A DC circuit topology for an energy storage system, characterized in that, The DC circuit topology is connected between the energy storage device and the bus capacitor of the energy storage system, including: The first main relay is connected between the positive terminal of the energy storage device and the positive terminal of the bus capacitor. The second main relay is connected between the negative terminal of the energy storage device and the negative terminal of the bus capacitor. A pre-charge branch is connected between the positive terminal of the energy storage device and the bus capacitor to provide a pre-charge current path; the pre-charge branch includes a buffer unit having a controlled semiconductor device or energy storage element to suppress the inrush current flowing through the pre-charge branch.

2. The DC circuit topology of the energy storage system according to claim 1, characterized in that, The pre-charge branch is connected in parallel with the first main relay. The buffer unit includes the controlled semiconductor device, which is connected in series in the pre-charge branch. By adjusting the conduction state of the controlled semiconductor device, the inrush current flowing through the pre-charge branch is suppressed.

3. The DC circuit topology of the energy storage system according to claim 2, characterized in that, The controlled semiconductor device has a first electrode, a second electrode, and a control terminal. The first electrode is connected to the positive terminal of the energy storage device, and the second electrode is connected to the positive terminal of the bus capacitor. The controlled semiconductor device is configured to regulate the current flowing between the first electrode and the second electrode by changing the voltage of the control terminal.

4. The DC circuit topology of the energy storage system according to claim 2 or 3, characterized in that, The precharge branch also includes an auxiliary relay connected in series with the controlled semiconductor device to disconnect the precharge branch at the end of the precharge phase.

5. The DC circuit topology of the energy storage system according to claim 2 or 3, characterized in that, The controlled semiconductor device operates in linear amplification mode during the pre-charge phase. The current flowing through the pre-charge branch is adjusted by controlling the conduction level of the controlled semiconductor device.

6. The DC circuit topology of the energy storage system according to claim 2 or 3, characterized in that, The controlled semiconductor device operates in pulse width modulation mode during the precharge phase, and the average current flowing through the precharge branch is adjusted by controlling the switch duty cycle.

7. The DC circuit topology of the energy storage system according to claim 1, characterized in that, The pre-charge branch is connected in parallel with the first main relay, and the buffer unit includes a pre-charge inductor connected in series in the pre-charge branch; The precharge branch also includes an auxiliary relay connected in series with the precharge inductor to disconnect the precharge branch at the end of the precharge phase.

8. The DC circuit topology of the energy storage system according to claim 7, characterized in that, The buffer unit further includes a diode, the anode of which is connected to the node between the pre-charge inductor and the bus capacitor, and the cathode of which is connected to the node between the pre-charge inductor and the auxiliary relay.

9. The DC circuit topology of the energy storage system according to claim 1, characterized in that, The buffer unit includes an auxiliary capacitor, a first switching switch, and a second switching switch. The auxiliary capacitor is connected in series with the first switching switch and then connected between the positive and negative terminals of the energy storage device. The two ends of the auxiliary capacitor are connected in parallel with the bus capacitor through the second switching switch. When the first switching switch is closed and the second switching switch is open, the energy storage device charges the auxiliary capacitor. When the first switching switch is open and the second switching switch is closed, the auxiliary capacitor precharges the bus capacitor.

10. An energy storage system, characterized in that, include: DC circuit topology as described in any one of claims 1-9; A controller is connected to the first main relay, the second main relay, and the precharge branch of the DC circuit topology to control the conduction and disconnection of the first main relay, the second main relay, and the precharge branch; A sampling module is connected to both ends of the bus capacitor to collect the bus voltage and feed it back to the controller.

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