A novel SVG power unit board card driving circuit

Abstract

The utility model discloses a novel SVG power unit board card drive circuit, include: resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity C7, electric capacity C8, electric capacity C9, diode D1, diode D2, diode D3, triode T1, triode T2 and drive chip. The gate voltage of the utility model has obviously improved in the early stage, reduces the opening time simultaneously, and IGBT enters the saturation state more quickly, reduces IGBT false report risk, avoids the risk of gate voltage high moment upper and lower tube straight-through damage, reduces the loss simultaneously, effectively reduces the raw material cost, and lays the foundation for the stable operation of product.

Description

Technical Field

[0001] This utility model belongs to the field of reactive power compensation technology, specifically relating to a novel SVG power unit board drive circuit. Background Technology

[0002] A Static Var Generator (SVG) is a device used for dynamic reactive power compensation. It connects to the power grid via a self-commutated bridge circuit, adjusting the amplitude of the AC output voltage to absorb or generate reactive power. Multiple power units are cascaded and connected in series with the power grid to achieve high-voltage operation.

[0003] As the basic unit of SVG, the SVG power unit adopts the voltage source inverter principle. The performance of the drive circuit is directly related to the stable operation of IGBT, and thus affects the reliability of SVG power unit. Specifically, there are the following shortcomings: (1) The gate voltage is too low at the turn-on time, which causes the risk of false alarm of IGBT; (2) The gate voltage is too low, which causes the Vce voltage to drop slowly, thereby increasing the loss at the turn-on time; (3) In order to achieve rapid turn-on of IGBT, it is necessary to increase the amplitude of IGBT gate positive voltage. In the later stage of IGBT fully conduction, the gate voltage is higher than the required +15V. When the upper and lower tubes of IGBT are directly connected, the short circuit current is much higher than the multiple of the rated current, which increases the loss of IGBT entering desaturation state due to short circuit, and thus increases the IGBT overheating damage caused by the increase of instantaneous loss. Utility Model Content

[0004] This utility model aims to overcome the shortcomings of the existing technology and provides the following solution: A novel SVG power unit board driver circuit includes: resistors R1, R2, R3, R4, R5, R6, and R7; capacitors C1, C2, C3, C4, C5, C6, C7, C8, and C9; diodes D1, D2, and D3; transistors T1 and T2; and a driver chip.

[0005] Preferably, the driver chip is an ACPL-332J optically isolated driver chip, with the primary side powered by +5V and the secondary side powered by -10V and +15V.

[0006] Preferably, the resistor R2 is connected to the ANODE pin of the driver chip, and the CATHODE pin of the driver chip is grounded.

[0007] Preferably, the first Vs pin of the driver chip is connected to the capacitor C1 and grounded, and the other end of the capacitor C1 is connected to the +5V power supply; The second Vs pin of the driver chip is connected to capacitors C2 and C3 and grounded. The other end of capacitor C3 is connected to resistor R1 and pin FAULT. The other end of capacitor C2 and the other end of resistor R1 are connected to the +5V power supply and pin Vcc1.

[0008] Preferably, the V of the driver chip E The pin is connected to capacitor C4, capacitor C5, the emitter of the IGBT, and capacitor C7; The other end of capacitor C4 is connected to capacitor C6 and the Vcc pin of the driver chip; the other end of capacitor C5 is connected to resistor R3 and the DESAT pin of the driver chip; the other end of resistor R3 is connected to diode D1; and the other end of diode D1 is connected to the collector of the IGBT. The other end of capacitor C6 is connected to the first V of the driver chip. EE Pin connection, the other end of capacitor C7 is connected to the second V of the driver chip. EE pins and V CLAMP Pin connection; The capacitor C4 is a +15V coupling capacitor, and the capacitor C6 is a -10V and +15V coupling capacitor.

[0009] Preferably, the resistor R6, the resistor R7, the diode D2, the diode D3, the transistor T1, and the transistor T2 constitute a power amplifier circuit; The collector of transistor T1 is connected to resistor R6, capacitor C6, and the Vcc pin of the driver chip. The emitter of transistor T1 is connected to the emitter of transistor T2 and to resistor R5. The collector of transistor T2 is connected to resistor R7, capacitor C8, and the second Vcc pin of the driver chip. EE pins and V CLAMP Pin connection; The other end of resistor R6 is connected to diode D2, the other end of diode D2 is connected to diode D3, and the other end of diode D3 is connected to resistor R7; The bases of transistors T1 and T2 are connected to capacitor C8 and resistor R4, and the other end of resistor R4 is connected to the V of the driver chip. OUT Pin connection; The other end of the resistor R5 is connected to the capacitor C9 and the IGBT, and the other end of the capacitor C9 is connected to the capacitor C7.

[0010] Compared with the prior art, the beneficial effects of this utility model are as follows: This invention significantly improves the gate voltage in the early stages, reduces the turn-on time, allows the IGBT to enter saturation more quickly, reduces the risk of false alarms, avoids the risk of shoot-through damage to the upper and lower transistors when the gate voltage is too high, and also reduces losses, effectively lowering raw material costs and laying the foundation for stable product operation. Attached Figure Description

[0011] To more clearly illustrate the technical solution of this utility model, the drawings used in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a circuit diagram of an embodiment of the present utility model; Figure 2 This is a waveform diagram of the driving pulse in an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0014] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] Example In this embodiment, as Figure 1 As shown, a novel SVG power unit board driver circuit includes: resistors R1, R2, R3, R4, R5, R6, and R7; capacitors C1, C2, C3, C4, C5, C6, C7, C8, and C9; diodes D1, D2, and D3; transistors T1 and T2; and a driver chip.

[0016] The driver chip is an ACPL-332J optically isolated driver chip. The primary side of the driver chip is powered by +5V, and the secondary side is powered by -10V and +15V.

[0017] Resistor R2 is connected to the ANODE pin of the driver chip, and the CATHODE pin of the driver chip is grounded. In this embodiment, resistor R2 is a current-limiting resistor for the low-voltage side drive signal, used for the drive current of ACPL-332J (ACPL-332J is an optically isolated chip, and the pulse is current-driven). The drive current pulse waveform is as follows: Figure 2 As shown.

[0018] The first Vs pin of the driver chip is connected to capacitor C1 and grounded, and the other end of capacitor C1 is connected to the +5V power supply.

[0019] The second Vs pin of the driver chip is connected to capacitors C2 and C3 and grounded. The other end of capacitor C3 is connected to resistor R1 and the FAULT pin. The other ends of capacitor C2 and resistor R1 are connected to the +5V power supply and the Vcc1 pin. In this embodiment, R1 is the pull-up resistor for the fault signal, and C3 is the coupling capacitor for FAULT.

[0020] V of the driver chip E The pins are connected to capacitors C4 and C5, the emitter of the IGBT, and capacitor C7. The other end of capacitor C4 is connected to capacitor C6 and the Vcc pin of the driver chip. The other end of capacitor C5 is connected to resistor R3 and the DESAT pin of the driver chip. The other end of resistor R3 is connected to diode D1, and the other end of diode D1 is connected to the collector of the IGBT. In this embodiment, resistor R3 and capacitor C5 form an RC circuit. During the IGBT turn-on process, the desaturation state of the IGBT is detected. Capacitor C5 acts as a blanking capacitor at the turn-on moment of the IGBT, detecting the voltage rise time of the IGBT at the turn-on moment. By adjusting the parameters of resistor R3 and capacitor C5, the IGBT fault alarm time is determined.

[0021] The other end of capacitor C6 is connected to the first V of the driver chip. EE Pin connections, the other end of capacitor C7 is connected to the second V of the driver chip. EE pins and V CLAMP Pin connections. In this embodiment, capacitor C7 serves as V. E pins and V EE Coupling capacitance between pins.

[0022] Capacitor C4 is a +15V coupling capacitor, and capacitor C6 is a -10V and +15V coupling capacitor.

[0023] Resistors R6 and R7, diodes D2 and D3, and transistors T1 and T2 constitute a power amplifier circuit. In this embodiment, the power amplifier circuit is a class AB dual-supply push-pull circuit. Diodes D2 and D3 prevent transistor crossover distortion. Transistors T1 and T2 are power amplification devices. Transistor T1 is an NPN transistor with its collector connected to a 15V power supply, and transistor T2 is a PNP transistor with its collector connected to a -10V power supply. The emitters of both transistors jointly drive the IGBT to turn on and off. During IGBT turn-on and turn-off, the drive power is increased to avoid IGBT false alarms caused by insufficient 2.5A drive current from the ACPL-332J driver chip.

[0024] The collector of transistor T1 is connected to resistor R6, capacitor C6, and the Vcc pin of the driver chip. The emitter of transistor T1 is connected to the emitter of transistor T2 and is also connected to resistor R5. The collector of transistor T2 is connected to resistor R7, capacitor C8, and the second Vcc pin of the driver chip. EE pins and V CLAMP Pin connections. In this embodiment, capacitor C8 is used to suppress sudden changes in the drive voltage waveform.

[0025] The other end of resistor R6 is connected to diode D2, the other end of diode D2 is connected to diode D3, and the other end of diode D3 is connected to resistor R7.

[0026] The bases of transistors T1 and T2 are connected to capacitor C8 and resistor R4, and the other end of resistor R4 is connected to the V of the driver chip. OUT Pin connections. In this embodiment, resistor R4 serves as the base resistor of the power amplifier circuit.

[0027] The other end of resistor R5 is connected to capacitor C9 and the IGBT, and the other end of capacitor C9 is connected to capacitor C7. In this embodiment, resistor R5 and capacitor C9 form the gate resistor and gate capacitor of the IGBT, coupling the gate voltage oscillation caused by reverse transmission current and the gate spike caused by line strays. Resistor R5 is used to limit the gate current of the IGBT, and capacitor C9 is used to suppress gate voltage oscillation.

[0028] In this embodiment, after the ACPL-332J optical isolation driver chip receives the pulse signal, V OUT As the voltage rises from low to high, it is output to the push-pull circuit through resistor R4. Transistor T2 is turned off, and transistor T1 is turned on. Due to the low capacitance C8 and the characteristics of the transistor, the IGBT gate voltage will not suddenly become high. Only after the base voltage of transistor T1 rises to 0.7V will transistor T1 change from the cutoff state to the amplification state. As the base voltage continues to rise, transistor T1 enters the saturation state from the amplification state. At this time, the IGBT gate voltage rises to the power supply voltage.

[0029] The embodiments described above are merely preferred embodiments of the present utility model and are not intended to limit the scope of the present utility model. Any modifications and improvements made to the technical solutions of the present utility model by those skilled in the art without departing from the spirit of the present utility model should fall within the protection scope defined by the claims of the present utility model.

Claims

1. A novel SVG power unit board driving circuit, characterized in that, include: Resistors R1, R2, R3, R4, R5, R6, R7; capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9; diodes D1, D2, D3; transistors T1 and T2; and a driver chip.

2. The novel SVG power unit board driving circuit according to claim 1, characterized in that, The driver chip is an ACPL-332J optically isolated driver chip. The primary side of the driver chip is powered by +5V, and the secondary side is powered by -10V and +15V.

3. The novel SVG power unit board driving circuit according to claim 2, characterized in that, The resistor R2 is connected to the ANODE pin of the driver chip, and the CATHODE pin of the driver chip is grounded.

4. The novel SVG power unit board driving circuit according to claim 2, characterized in that, The first Vs pin of the driver chip is connected to the capacitor C1 and grounded, and the other end of the capacitor C1 is connected to the +5V power supply. The second Vs pin of the driver chip is connected to capacitors C2 and C3 and grounded. The other end of capacitor C3 is connected to resistor R1 and pin FAULT. The other end of capacitor C2 and the other end of resistor R1 are connected to the +5V power supply and pin Vcc1.

5. The novel SVG power unit board driving circuit according to claim 2, characterized in that, The V of the driver chip E The pin is connected to capacitor C4, capacitor C5, the emitter of the IGBT, and capacitor C7; The other end of capacitor C4 is connected to capacitor C6 and the Vcc pin of the driver chip; the other end of capacitor C5 is connected to resistor R3 and the DESAT pin of the driver chip; the other end of resistor R3 is connected to diode D1; and the other end of diode D1 is connected to the collector of the IGBT. The other end of capacitor C6 is connected to the first V of the driver chip. EE Pin connection, the other end of capacitor C7 is connected to the second V of the driver chip. EE pins and V CLAMP Pin connection; The capacitor C4 is a +15V coupling capacitor, and the capacitor C6 is a -10V and +15V coupling capacitor.

6. The novel SVG power unit board driver circuit according to claim 5, characterized in that, The resistor R6, the resistor R7, the diode D2, the diode D3, the transistor T1, and the transistor T2 constitute a power amplifier circuit; The collector of transistor T1 is connected to resistor R6, capacitor C6, and the Vcc pin of the driver chip. The emitter of transistor T1 is connected to the emitter of transistor T2 and to resistor R5. The collector of transistor T2 is connected to resistor R7, capacitor C8, and the second Vcc pin of the driver chip. EE pins and V CLAMP Pin connection; The other end of resistor R6 is connected to diode D2, the other end of diode D2 is connected to diode D3, and the other end of diode D3 is connected to resistor R7; The bases of transistors T1 and T2 are connected to capacitor C8 and resistor R4, and the other end of resistor R4 is connected to the V of the driver chip. OUT Pin connection; The other end of the resistor R5 is connected to the capacitor C9 and the IGBT, and the other end of the capacitor C9 is connected to the capacitor C7.

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