A common ground type non-isolated inverter circuit

Abstract

The utility model discloses a common ground type non -isolated inverter circuit, including direct current voltage source, the direct current voltage source is photovoltaic module, direct current voltage source is converted to alternating voltage source through inverter topology, the inverter topology includes three inductances and four capacitors, the inverter topology includes positive half cycle inverter loop and negative half cycle inverter loop, the positive half cycle inverter loop includes MOSFET pipe Q1, MOSFET pipe Q3, inductance L1, inductance L3, capacitor C3 and capacitor C1, the negative half cycle inverter loop includes MOSFET pipe Q2, MOSFET pipe Q4, inductance L2, inductance L3, capacitor C4 and capacitor C1 constitute, photovoltaic array PV (i. e. photovoltaic module) negative pole directly connects the common ground type inverter topology of power grid, makes the common mode voltage (VCm) of DC side to ground keep constant (or approximately constant), thereby avoids the generation of dVCm / dt, fundamentally eliminates common mode current path.

Description

Technical Field

[0001] This utility model relates to the field of inverters, and in particular to a common-ground non-isolated inverter circuit. Background Technology

[0002] An inverter is a DC (direct current) to AC (alternating current) transformer; it is essentially a voltage inversion process, similar to a converter.

[0003] Non-isolated photovoltaic inverters (PV inverters) lack transformer isolation between the DC and AC sides. The photovoltaic modules, inverters, and grid are actually coupled to each other through parasitic capacitances (such as the photovoltaic module's capacitance to ground). This structure easily leads to the generation of high-frequency common-mode current (CMC) or leakage current, mainly in the frequency range of tens of kHz to several MHz. This not only affects system efficiency and electromagnetic compatibility (EMC), but may also pose safety hazards.

[0004] Currently, topologies that primarily sample stable common-mode voltage (such as H5, H6, HERIC, etc.) control the switching mode of the power transistors to keep the DC-side common-mode voltage (Vcm) to ground constant or with minimal variation, thereby significantly reducing the common-mode current through the parasitic capacitance to ground of the photovoltaic module.

[0005] The disadvantages are that the topology and control are more complex, and the requirements for devices are higher. Utility Model Content

[0006] The main purpose of this invention is to propose a common-ground non-isolated inverter circuit, which aims to connect the common-ground inverter topology directly to the power grid through the negative terminal of the photovoltaic array PV. That is, through circuit structure design, the common-mode voltage (Vcm) of the DC side to ground is kept constant (or approximately constant), thereby avoiding the generation of dVcm / dt and fundamentally eliminating the common-mode current path. dVcm / dt is an important parameter for evaluating the electromagnetic characteristics of a circuit, analyzing common-mode interference sources, and performing electromagnetic compatibility design. It also transfers energy to the power grid via capacitive coupling, thus isolating the battery from the power grid.

[0007] To achieve the above objectives, this utility model proposes a common-ground non-isolated inverter circuit, comprising: A DC voltage source, wherein the DC voltage source is a photovoltaic module, and the DC voltage source is converted into an AC voltage source through an inverter topology (i.e., the topology circuit is the core component of the electronic system to realize power management, energy conversion and signal processing, and its selection and design directly affect the system's performance, efficiency and reliability). The inverter topology includes three inductors and four capacitors; The inverter topology includes a positive half-cycle inverter circuit and a negative half-cycle inverter circuit; The positive half-cycle inverter circuit includes MOSFET Q1, MOSFET Q3, inductor L1, inductor L3, capacitor C3, and capacitor C1; The negative half-cycle inverter circuit consists of MOSFET Q2, MOSFET Q4, inductor L2, inductor L3, capacitor C4, and capacitor C1. A common-mode inverter topology in which the negative terminal of the photovoltaic array (PV) (i.e., photovoltaic module) is directly connected to the grid ensures that the common-mode voltage (VCm) on the DC side to ground remains constant (or approximately constant), thereby avoiding the generation of dVCm / dt and fundamentally eliminating the common-mode current path.

[0008] This invention couples the energy of the photovoltaic array (PV) to the power grid through a capacitor, thereby achieving isolation between the PV array and the power grid capacitor.

[0009] Specifically, in traditional topologies, the positive and negative electrodes of the photovoltaic array PV panels are "floating" and have no direct DC connection to the power grid.

[0010] In this topology, the negative terminal of the photovoltaic array PV panel is directly connected to the neutral line of the power grid (which can be considered as ground) through a circuit (such as the body diode of Q4 or the conduction path). This establishes a fixed reference point for the common-mode voltage.

[0011] Common-mode voltage constant analysis Since the photovoltaic array PV- is directly connected to the grid ground (GND) through a common ground structure, the voltage V_P- of the photovoltaic array PV- to ground is clamped at 0V (or approximately 0V) and remains constant.

[0012] The circuit controls the potential of V_P+ through a clever switching strategy and a Y-capacitor network composed of C3 / C4: Switch state A (e.g., Q1 and Q4 are on): Current path: PV+ photovoltaic array → Q1 → L2 → load / grid → L3 → C1 → Q4 → GND → PV- photovoltaic array.

[0013] At this time, the potential of the photovoltaic array PV+ is raised to close to the DC bus voltage, and the switch state B (such as Q2 and Q3 are turned on). Current path: PV+ photovoltaic array → ... (another path) → PV- photovoltaic array.

[0014] At this point, the potential of the photovoltaic array PV+ is pulled down to a certain negative potential.

[0015] Regardless of how the switching transistors are switched, since the midpoint of C3 and C4 (i.e. the midpoint of the Y capacitor) is forced to ground, they form a voltage divider.

[0016] This voltage divider works in conjunction with the switching action of the full bridge, so that the absolute value of the photovoltaic array PV+ voltage to ground V_P+ changes in any switching state, but its "DC bias" component relative to the grid ground is stabilized by the C3 / C4 network. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the present invention; Figure 2 A schematic diagram showing the wavelength of the circuit when modulated by different signals; Figure 3 This is a schematic diagram of an existing Heri capacitor C topology grid-connected inverter. Figure 4 This is a schematic diagram of an existing H5 topology grid-connected inverter. Detailed Implementation

[0018] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0019] It should be noted that if any directional indication (such as up, down, left, right, front, back, top, bottom, inside, outside, vertical, horizontal, longitudinal, counterclockwise, clockwise, circumferential, radial, axial, etc.) is involved in the embodiments of this utility model, the directional indication is only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0020] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0021] like Figures 1 to 4 As shown, a common-ground non-isolated inverter circuit includes: A DC voltage source, wherein the DC voltage source is a photovoltaic module, and the DC voltage source is converted into an AC voltage source through an inverter topology (i.e., the topology circuit is the core component of the electronic system to realize power management, energy conversion and signal processing, and its selection and design directly affect the system's performance, efficiency and reliability). The inverter topology includes three inductors and four capacitors; The inverter topology includes a positive half-cycle inverter circuit and a negative half-cycle inverter circuit; The positive half-cycle inverter circuit includes MOSFET Q1, MOSFET Q3, inductor L1, inductor L3, capacitor C3, and capacitor C1; The negative half-cycle inverter circuit consists of MOSFET Q2, MOSFET Q4, inductor L2, inductor L3, capacitor C4, and capacitor C1. A common-mode inverter topology in which the negative terminal of the photovoltaic array (PV) (i.e., photovoltaic module) is directly connected to the grid ensures that the common-mode voltage (VCm) on the DC side to ground remains constant (or approximately constant), thereby avoiding the generation of dVCm / dt and fundamentally eliminating the common-mode current path.

[0022] This invention couples the energy of the photovoltaic array (PV) to the power grid through a capacitor, thereby achieving isolation between the PV array and the power grid capacitor.

[0023] Specifically, in traditional topologies, the positive and negative electrodes of the photovoltaic array PV panels are "floating" and have no direct DC connection to the power grid.

[0024] In this topology, the negative terminal of the photovoltaic array PV panel is directly connected to the neutral line of the power grid (which can be considered as ground) through a circuit (such as the body diode of Q4 or the conduction path). This establishes a fixed reference point for the common-mode voltage.

[0025] Common-mode voltage constant analysis Since the photovoltaic array PV- is directly connected to the grid ground (GND) through a common ground structure, the voltage V_P- of the photovoltaic array PV- to ground is clamped at 0V (or approximately 0V) and remains constant.

[0026] The circuit controls the potential of V_P+ through a clever switching strategy and a Y-capacitor network composed of C3 / C4: Switching state A (e.g., Q1 and Q4 are on): Current path: PV+ photovoltaic array → Q1 → L2 → load / grid → L3 → C1 → Q4 → GND → PV- photovoltaic array.

[0027] At this time, the potential of the photovoltaic array PV+ is raised to close to the DC bus voltage, and the switch state B (such as Q2 and Q3 are turned on). Current path: PV+ photovoltaic array → ... (another path) → PV- photovoltaic array.

[0028] At this point, the potential of the photovoltaic array PV+ is pulled down to a certain negative potential.

[0029] Regardless of how the switching transistors are switched, since the midpoint of C3 and C4 (i.e. the midpoint of the Y capacitor) is forced to ground, they form a voltage divider.

[0030] This voltage divider works in conjunction with the switching action of the full bridge, so that the absolute value of the photovoltaic array PV+ voltage to ground V_P+ changes in any switching state, but its "DC bias" component relative to the grid ground is stabilized by the C3 / C4 network.

[0031] Specifically, a capacitor C2 is connected in parallel between the positive and negative branches of the DC voltage source.

[0032] In this embodiment of the invention, capacitor C2 is a BUS bus energy storage capacitor used for smoothing voltage fluctuations, energy storage, and filtering.

[0033] Specifically, during the positive half-cycle, MOSFETs Q1 and Q3 are complementary; when MOSFET Q1 is turned on, the input voltage charges inductor L1. At the same time, capacitor C3 releases energy, and inductor L3 and capacitor C1 form an LC filter. When MOSFET Q1 is turned off, inductor L1 and inductor L3 freewheel, while simultaneously charging capacitor C3 and capacitor C1.

[0034] In this embodiment of the invention, during the negative half-cycle, MOSFETs Q2 and Q4 are complementary; when MOSFET Q2 is turned on, the input voltage charges inductor L2. At the same time, capacitor C3 releases energy, inductor L3 and capacitor C1 form an LC filter, and when MOSFET Q2 is turned off, inductors L2 and L3 freewheel, while simultaneously charging capacitors C4 and C1.

[0035] Specifically, MOSFETs Q1, Q2, Q3, and Q4 are four inverter transistors.

[0036] In this embodiment of the invention, the signal terminals of MOSFETs Q1, Q2, Q3, and Q4 are respectively input with different PWM drive signals.

[0037] Assuming the input is VdC and the output is VaC, the duty cycle of MOSFET Q1 during the positive half-cycle is D1 = VaC / (VdC + VaC). The duty cycle of MOSFET Q3 is D3 = VdC / (VdC+VaC). MOSFET Q2 is turned off, and MOSFET Q4 is turned on. Similarly, during the negative half-cycle, the duty cycle of MOSFET Q2 is D2 = -VaC / (VdC - VaC). The duty cycle of MOSFET Q4 is D3 = VdC / (VdC-VaC). When MOSFET Q1 is turned off, MOSFET Q3 is turned on. In this embodiment of the invention, MOSFETs Q1, Q2, Q3, and Q4 perform bidirectional conversion between DC and AC and between DC and AC. MOSFETs Q1 and Q3 generate complementary waveforms, while MOSFETs Q2 and Q4 generate complementary waveforms. Specifically, inductors L1, L2, and L3, and capacitors C1, C2, C3, and C4 form an energy storage filter network to filter the high-frequency signal into a power frequency sine wave. The circuit's waveform modulation is as follows: Figure 2 As shown.

[0038] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the inventive concept of the present utility model using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. A common-ground non-isolated inverter circuit, characterized in that, include: A DC voltage source, wherein the DC voltage source is a photovoltaic module, and the DC voltage source is converted into an AC voltage source through an inverter topology; The inverter topology includes three inductors and four capacitors; The inverter topology includes a positive half-cycle inverter circuit and a negative half-cycle inverter circuit; The positive half-cycle inverter circuit includes MOSFET Q1, MOSFET Q3, inductor L1, inductor L3, capacitor C3, and capacitor C1; The negative half-cycle inverter circuit consists of MOSFET Q2, MOSFET Q4, inductor L2, inductor L3, capacitor C4, and capacitor C1.

2. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: A capacitor C2 is connected in parallel between the positive and negative branches of the DC voltage source.

3. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: The capacitor C2 is the BUS bus energy storage capacitor.

4. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: During the positive half-cycle, MOSFETs Q1 and Q3 are complementary. When MOSFET Q1 is turned on, the input voltage charges inductor L1. At the same time, capacitor C3 releases energy, and when MOSFET Q1 is turned off, inductors L1 and L3 freewheel, simultaneously charging capacitors C3 and C1.

5. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: During the negative half-cycle, MOSFETs Q2 and Q4 are complementary. When MOSFET Q2 is turned on, the input voltage charges inductor L2. At the same time, capacitor C3 releases energy, and when MOSFET Q2 is turned off, inductors L2 and L3 freewheel, while simultaneously charging capacitors C4 and C1.

6. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: MOSFETs Q1, Q2, Q3, and Q4 are four inverter transistors.

7. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: The signal terminals of MOSFETs Q1, Q2, Q3, and Q4 are respectively input with different PWM drive signals.

8. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: MOSFETs Q1, Q2, Q3, and Q4 perform bidirectional conversion between DC and AC. MOSFETs Q1 and Q3 generate complementary waveforms, while MOSFETs Q2 and Q4 generate complementary waveforms.

9. The common-ground non-isolated inverter circuit as described in claim 1, characterized in that: Inductors L1, L2, and L3, along with capacitors C1, C2, C3, and C4, form an energy storage and filtering network to filter high-frequency signals into power frequency sine waves.

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