A bias circuit for a power amplifier

Abstract

The embodiment of the present disclosure provides a bias circuit of a power amplifier, comprising: a current mirror circuit, a first adjusting circuit, a second adjusting circuit and a power supply; the power supply is connected with an input end of the current mirror circuit, and is used for supplying power for the current mirror circuit; a first output end of the current mirror circuit is connected with an input end of the first adjusting circuit; a second output end of the current mirror circuit and an input end of the second adjusting circuit are connected, and are connected with an output end of the bias circuit; the second output end of the current mirror circuit is used for providing a first bias voltage; the first adjusting circuit is used for adjusting the first bias voltage; the second adjusting circuit is used for providing a second bias voltage; the first bias voltage and the second bias voltage are superimposed to output a bias voltage; and impedance of the bias circuit is located in a preset impedance range.

Description

Technical Field

[0001] This disclosure relates to electronic technology, and more particularly to a bias circuit for a power amplifier. Background Technology

[0002] The bias circuit of an RF amplifier is used to provide a stable DC bias for the power transistor. For a MOS transistor amplifier, it mainly provides a DC bias voltage for the gate of the MOS transistor.

[0003] In related technologies, the development of wireless communication protocols from 3G to 5G requires a continuous increase in data transmission rate. Increasing channel bandwidth is one of the effective means to improve transmission speed. Therefore, wireless communication usually uses broadband high linearity power amplifiers. However, the increase in channel bandwidth places higher demands on the memory effect of power amplifiers. Excessive memory effect will lead to a decrease in linearity index, making it difficult to meet communication standards. Utility Model Content

[0004] This disclosure provides a bias circuit for a power amplifier, the bias circuit including: a current mirror circuit, a first adjustment circuit, a second adjustment circuit, and a power supply; The power supply is connected to the input terminal of the current mirror circuit and is used to supply power to the current mirror circuit. The first output terminal of the current mirror circuit is connected to the input terminal of the first adjustment circuit; The second output terminal of the current mirror circuit is connected to the input terminal of the second adjustment circuit, and is also connected to the output terminal of the bias circuit. The second output terminal of the current mirror circuit is used to provide a first bias voltage; the first adjustment circuit is used to adjust the first bias voltage; the second adjustment circuit is used to provide a second bias voltage; the first bias voltage and the second bias voltage are superimposed to output a bias voltage; The impedance of the bias circuit is within a preset impedance range.

[0005] In some embodiments, the current mirror circuit includes: a second transistor, a third transistor, and a first capacitor; In this configuration, the drain of the second transistor is connected to the power supply, and the drain of the second transistor is connected to its gate; the source of the second transistor is connected to the input terminal of the first adjustment circuit; and the gate of the second transistor is connected to the gate of the third transistor. The gate of the third transistor is also connected to the ground terminal through the first capacitor, the drain of the third transistor is connected to the power supply, the source of the third transistor is connected to the input terminal of the second adjustment circuit, and is also connected to the gate of the first transistor in the power amplifier.

[0006] In some embodiments, the third transistor is 2 to 10 times the size of the second transistor.

[0007] In some embodiments, the current mirror circuit further includes a first resistor, wherein the gate of the second transistor is connected to the gate of the third transistor through the first resistor.

[0008] In some embodiments, the first adjustment circuit includes: a fourth transistor; the drain of the fourth transistor is connected to a first output terminal of the current mirror circuit, and the drain of the fourth transistor is also connected to its gate; the source of the fourth transistor is grounded. And / or, the first adjustment circuit includes: a diode, the positive terminal of which is connected to the first output terminal of the current mirror circuit, and the negative terminal is grounded.

[0009] In some embodiments, the second adjustment circuit includes: a fifth transistor; the drain of the fifth transistor is connected to the second output terminal of the current mirror circuit; the gate of the fifth transistor is connected to its drain, and the gate of the fifth transistor is also connected to a ground terminal; the source of the fifth transistor is grounded.

[0010] In some embodiments, the second adjustment circuit further includes: a third resistor and a second capacitor. The gate of the fifth transistor is connected to its drain via the third resistor, and the gate is grounded via the second capacitor.

[0011] In some embodiments, the current mirror circuit further includes a fourth resistor, through which the first capacitor is connected to a ground terminal.

[0012] In some embodiments, the bias circuit further includes: a second resistor; The second output terminal of the current mirror circuit is connected to the output terminal of the bias circuit through the second resistor.

[0013] In some embodiments, the resistors and capacitors can be variable or fixed.

[0014] In some embodiments, there are multiple first adjustment circuits and / or second adjustment circuits, and the multiple adjustment circuits are connected in parallel.

[0015] This disclosure provides a bias circuit for a power amplifier, including: a current mirror circuit, a first adjustment circuit, a second adjustment circuit, and a power supply; the power supply is connected to the input terminal of the current mirror circuit to supply power to the current mirror circuit; the first output terminal of the current mirror circuit is connected to the input terminal of the first adjustment circuit; the second output terminal of the current mirror circuit is connected to the input terminal of the second adjustment circuit and to the output terminal of the bias circuit; the second output terminal of the current mirror circuit provides a first bias voltage; the first adjustment circuit adjusts the first bias voltage; the second adjustment circuit provides a second bias voltage; the first bias voltage and the second bias voltage are superimposed to output a bias voltage; the impedance of the bias circuit is within a preset impedance range. Thus, by using the first adjustment circuit to adjust the first bias voltage and the second adjustment circuit to provide the second bias voltage to the power amplifier, the first bias voltage and the second bias voltage can be superimposed, thereby providing a stable bias voltage to the power amplifier, and the impedance of the bias circuit is within a preset impedance range, ensuring the linearity performance of the power amplifier and reducing the memory effect of the power amplifier. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the composition of the bias circuit of an existing power amplifier. Figure 2 This is a schematic diagram of the first component structure of the bias circuit of the power amplifier in the embodiments of this application; Figure 3 This is a schematic diagram of the second component structure of the bias circuit of the power amplifier in the embodiments of this application; Figure 4 This is a schematic diagram illustrating the relationship between radio frequency power and bias voltage in an embodiment of this application; Figure 5 This is a schematic diagram showing the comparison between the impedance of the bias circuit in this embodiment and the impedance of a conventional bias circuit. Figure 6 This is a schematic diagram of the third component structure of the bias circuit of the power amplifier in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the variable resistor in the embodiments of this application; Figure 8 This is a schematic diagram of the variable capacitor structure in an embodiment of this application; Figure 9 This is a schematic diagram showing the relationship between RF power and gain amplitude and bias voltage in the embodiments of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0019] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0020] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0021] Currently, in the evolution of wireless communication protocols from 3G and 4G to 5G, the required data transmission rates are becoming increasingly faster, and increasing channel bandwidth is one of the effective means to improve transmission speed. With the increase in modulation channel bandwidth and the adoption of modulation methods such as QPSK / QAM, wireless communication requires wideband, high-linearity power amplifiers. In particular, the increased channel bandwidth requires power amplifiers to have low memory effects; otherwise, memory effects will lead to a decline in linearity indicators (such as ACPR), making it difficult to meet communication standards. Therefore, it is necessary to improve the memory effect of power amplifiers in circuit design.

[0022] Furthermore, Figure 1 This is a schematic diagram of the bias circuit structure of an existing power amplifier. Figure 1As shown, the bias circuit 10 includes: transistor M11, capacitor C11, resistor R11, and current source IBIAS. Specifically, the drain of transistor M11 is connected to current source IBIAS1, the source of transistor M11 is grounded, and the drain of transistor M11 is shorted to its gate. The gate of transistor M11 is connected to the gate of transistor M21 in the power amplifier through resistor R11, providing a bias voltage to the gate of transistor M21. The gate of transistor M11 is also grounded through capacitor C11. Capacitor C11 and resistor R11 form an RC circuit for isolating RF (radio frequency) signals. The M21 transistor is included in the signal amplifier circuit 20 for amplifying the input signal. The signal amplifier circuit 20 also includes capacitors C21 and C22, a voltage source VCC, and an inductor L. Specifically, the gate of the M21 transistor is connected to one end of capacitor C21, and the other end of capacitor C21 serves as the RF signal input terminal to input the RF signal RFin. The drain of the M21 transistor is connected to the voltage source VCC through the inductor L, and is also connected to one end of capacitor C22. The other end of capacitor C22 serves as the RF signal output terminal to output the RF signal RFout. The source of the M21 transistor is connected to the ground terminal.

[0023] Figure 1 The bias circuit shown has a high baseband impedance to ensure that the RC circuit can effectively isolate RF signals. This typically requires a large resistor value R, usually in the range of 1 to 10 kiloohms (K ohms). However, when the RC circuit has a high impedance at the baseband frequency, it can enhance the memory effect of the power amplifier, leading to poor linearity when amplifying broadband modulated signals, resulting in signal distortion and affecting communication quality.

[0024] Based on this, this disclosure provides a bias circuit for a power amplifier, including: a current mirror circuit, a first adjustment circuit, a second adjustment circuit, and a power supply; the power supply is connected to the input terminal of the current mirror circuit to supply power to the current mirror circuit; the first output terminal of the current mirror circuit is connected to the input terminal of the first adjustment circuit; the second output terminal of the current mirror circuit is connected to the input terminal of the second adjustment circuit and to the output terminal of the bias circuit; the second output terminal of the current mirror circuit provides a first bias voltage; the first adjustment circuit adjusts the first bias voltage; the second adjustment circuit provides a second bias voltage; the first bias voltage and the second bias voltage are superimposed to output a bias voltage; the impedance of the bias circuit is within a preset impedance range. Thus, by using the first adjustment circuit to adjust the first bias voltage and the second adjustment circuit to provide the second bias voltage to the power amplifier, the first bias voltage and the second bias voltage can be superimposed, thereby providing a stable bias voltage to the power amplifier, and the impedance of the bias circuit is within a preset impedance range, ensuring the linearity performance of the power amplifier and reducing the memory effect of the power amplifier.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0026] This disclosure provides a bias circuit 100 for a power amplifier, such as... Figure 2 As shown, the bias circuit 100 includes: a current mirror circuit 110, a first adjustment circuit 120, a second adjustment circuit 130, and a power supply 140; the power supply 140 is connected to the input terminal of the current mirror circuit 110 and is used to supply power to the current mirror circuit 110; the first output terminal of the current mirror circuit 110 is connected to the input terminal of the first adjustment circuit 120; the second output terminal of the current mirror circuit 110 and the input terminal of the second adjustment circuit 130 are simultaneously connected to the output terminal of the bias circuit 100; the output terminal of the bias circuit 100 is connected to the signal amplification circuit 200; the current mirror circuit 110 is used to provide a first bias voltage to the gate of the first transistor M1; the first adjustment circuit 120 is used to adjust the first bias voltage; the second adjustment circuit 130 is used to provide a second bias voltage to the gate of the first transistor M1; the first bias voltage and the second bias voltage are superimposed to output a bias voltage; the impedance of the bias circuit 100 is within a preset impedance range.

[0027] Here, the current mirror circuit 110 provides a first bias voltage to the power amplifier 210, and the second adjustment circuit 130 provides a second bias voltage to the power amplifier 210. When the input signal to the power amplifier 210 is coupled to the bias circuit, the first bias voltage increases and the second bias voltage decreases. In this way, the effect of the increase in the first bias voltage and the effect of the decrease in the second bias voltage can cancel each other out, thereby providing a stable bias voltage to the power amplifier 210 and improving the linearity of the power amplifier 210.

[0028] The preset impedance range refers to the range that will not cause a deterioration in the linearity of the power amplifier. Here, the preset impedance range can be less than... Figure 1 The impedance of the bias circuit. A lower impedance in the bias circuit can improve the linearity of the power amplifier. For example, in this application, the preset impedance range is 3 to 10 ohms; or, for example, the preset impedance range is 9 to 55 ohms.

[0029] It should be noted that the current mirror circuit 110, the first adjustment circuit 120, and the second adjustment circuit 130 also include other matching components, such as one or more combinations of resistors, capacitors, and transistors. Through the combination of one or more components in the current mirror circuit 110, the first adjustment circuit 120, and the second adjustment circuit 130, the first bias voltage of the current mirror circuit 110 and the second bias voltage of the second adjustment circuit 130 are superimposed to provide a stable bias voltage for the power amplifier. Furthermore, the impedance of the bias circuit 100 is within a preset impedance range, reducing the memory effect of the power amplifier 210, ensuring the linearity of the power amplifier 210, and thus effectively amplifying the input RF signal.

[0030] in addition, Figure 2 The signal amplification circuit 200 includes a power amplifier 210, which amplifies the radio frequency signal input at the signal input terminal and outputs the amplified radio frequency signal from the signal output terminal.

[0031] Thus, the first bias voltage is adjusted by the first adjustment circuit, and the second adjustment circuit provides the second bias voltage to the power amplifier, so that the first bias voltage and the second bias voltage can be superimposed, thereby providing a stable bias voltage to the power amplifier. Moreover, the impedance of the bias circuit is within the preset impedance range, ensuring the linearity performance of the power amplifier and reducing the memory effect of the power amplifier.

[0032] against Figure 2 A schematic diagram of the first component structure of the bias circuit of a power amplifier is provided in this disclosure, along with a specific circuit structure diagram. Figure 3 This is a schematic diagram of the second component structure of the bias circuit of the power amplifier in an embodiment of this disclosure.

[0033] like Figure 3 The bias circuit 100 shown includes: a current mirror circuit 110, a first adjustment circuit 120, a second adjustment circuit 130, and a power supply 140; wherein, the power supply 140 includes: a current source IBIAS, a first voltage source VCC1, and a second voltage source VCC2.

[0034] In some embodiments, please refer to Figure 3The current mirror circuit 110 includes: a second transistor M2, a third transistor M3, and a first capacitor C1; wherein, the drain of the second transistor M2 is connected to the second voltage source VCC2 through the current source IBIAS, and the drain of the second transistor M2 is connected to its gate; the source of the second transistor M2 is connected to the input terminal of the first adjustment circuit 120 (i.e., the drain of the fourth transistor M4); the gate of the second transistor M2 is connected to the gate of the third transistor M3; the gate of the third transistor M3 is also connected to the ground terminal through the first capacitor C1, the drain of the third transistor M3 is connected to the first voltage source VCC1, the source of the third transistor M3 is connected to the input terminal of the second adjustment circuit 130 (i.e., the drain of the fifth transistor M5), and is also connected to the gate of the first transistor M1.

[0035] In this embodiment, the second transistor M2 and the third transistor M3 form a current mirror structure, and the gate and drain of the second transistor M2 are connected in the current mirror circuit 110. When the input radio frequency signal is coupled to the current mirror circuit through node V1, the gate-source voltage of the third transistor M3 will gradually decrease due to the detection effect of the diode of the third transistor M3; here, the gate-source voltage of the third transistor M3 is equal to the gate voltage of the third transistor M3 minus the source voltage.

[0036] In some embodiments, please refer to Figure 3 The current mirror circuit 110 further includes: a first resistor R1, and the gate of the second transistor M2 is connected to the gate of the third transistor M3 through the first resistor R1.

[0037] In this embodiment, the first resistor R1 and the first capacitor C1 form a low-pass network circuit. During operation, when the swing of the input radio frequency signal is coupled to the gate of the third transistor M3, the presence of the first capacitor C1 ensures that the gate voltage of the third transistor M3 remains stable and does not change with the radio frequency signal. Simultaneously, the first resistor R1 isolates the radio frequency signal from coupling into the bias current circuit, and effectively isolates noise (DC power supply noise) in the current circuit from coupling into the radio frequency amplifier circuit. That is, by isolating the radio frequency signal from coupling into the bias current circuit through the first resistor R1 and the first capacitor C1, the gate voltage of the second transistor M2 is prevented from being affected, ensuring that the gate voltage of the second transistor M2 remains unchanged, thereby keeping the gate voltage of the third transistor M3 constant.

[0038] In other words, since the input signal will reduce the gate-source voltage of the third transistor M3, the gate voltage of the third transistor M3 will remain unchanged through the first capacitor C1. Therefore, the source voltage of the third transistor M3 will increase, that is, the current mirror circuit will increase the voltage of node V1.

[0039] It should be noted that the value of the first resistor R1 should not be too large. If the value of the first resistor R1 is too large, the resistive noise it generates will interfere with the RF power amplifier circuit. Typically, the first resistor R1 is taken from 1 to 10 k Ohms. For example, 10 Ohms, 100 Ohms, or 500 Ohms. In some embodiments, the first resistor R1 may be omitted.

[0040] In some embodiments, please refer to Figure 3 The first adjustment circuit 120 includes: a fourth transistor M4; the drain of the fourth transistor M4 is connected to the first output terminal of the current mirror circuit 110 (i.e., the source of the second transistor M2), the drain of the fourth transistor M4 is connected to its gate; and the source of the fourth transistor M4 is grounded.

[0041] In this embodiment, the second transistor M2 and the fourth transistor M4 are connected in series. The fourth transistor M4 is used to adjust the gate voltage of the third transistor M3, thereby adjusting the first bias voltage, which in turn improves the stability and control performance of the current mirror circuit 110. In other embodiments, the fourth transistor M4 can be replaced with a variable resistor and / or a diode to achieve the same function as the fourth transistor M4; specifically, the positive terminal of the diode is connected to the first output terminal of the current mirror circuit, and the negative terminal is grounded.

[0042] In other embodiments, the bias circuit 100 may include a plurality of first adjustment circuits 120 connected in parallel; each first adjustment circuit 120 includes a fourth transistor M4; the drain of each fourth transistor M4 is connected to the first output terminal of the current mirror circuit 110, the drain of each fourth transistor M4 is connected to its gate; and the source of each fourth transistor M4 is grounded.

[0043] It should be noted that the resistance values ​​of the multiple fourth transistors M4 can be different; thus, the first bias voltage can be adjusted to different values ​​by switching different first adjustment circuits 120 or by connecting multiple first adjustment circuits 120 in parallel. Alternatively, at least one fourth transistor M4 can be replaced with a variable resistor and / or a diode.

[0044] In some embodiments, please refer to Figure 3 The second adjustment circuit 130 includes: a fifth transistor M5; the drain of the fifth transistor M5 is connected to the second output terminal of the current mirror circuit 110 (i.e., the source of the third transistor M3); the gate of the fifth transistor M5 is connected to its drain, and the gate of the fifth transistor M5 is also connected to the ground terminal; the source of the fifth transistor M5 is grounded.

[0045] Here, since the input signal causes the gate-source voltage of the fifth transistor M5 to gradually decrease, and the source voltage (ground) of the fifth transistor M5 remains unchanged, the gate voltage of the fifth transistor M5 decreases, thereby causing the voltage of node V1 to decrease.

[0046] In some embodiments, please refer to Figure 3 The second adjustment circuit 130 may further include: a third resistor R3 and a second capacitor C2; wherein, the gate of the fifth transistor M5 is connected to its drain through the third resistor R3, and the gate of the fifth transistor M5 is also connected to the ground terminal through the second capacitor C2.

[0047] The third resistor R3 and the second capacitor C2 form a low-pass network circuit, which can ensure the stability of the gate voltage of the fifth transistor M5 during operation.

[0048] In some embodiments, the bias circuit 100 may include a plurality of second adjustment circuits 130 connected in parallel, wherein the input terminal of each second adjustment circuit 130 and the second output terminal of the current mirror circuit 110 are simultaneously connected to node V1. Each second adjustment circuit 130 includes a fifth transistor M5, and at least one second adjustment circuit 130 includes a third resistor R3 and a second capacitor C2. Here, the connection method of the fifth transistor M5, the third resistor R3 and the second capacitor C2 can refer to the above embodiments (e.g., Figure 3 The embodiments shown are illustrated here and will not be described in detail here.

[0049] It should be noted that the resistance values ​​of the multiple fifth transistors M5 can be different; thus, different values ​​of the second bias voltage can be provided by switching different second adjustment circuits 130 or by connecting multiple second adjustment circuits 130 in parallel. Additionally, the multiple third resistors R3 can have different resistance values, and the multiple second capacitors C2 can have different capacitance values, allowing for the selection of different operating modes.

[0050] In this embodiment, the voltage of node V1 increases due to the current mirror circuit 110 and the voltage of node V1 decreases due to the second adjustment circuit 130. The voltage rise and fall of the two circuits have equal magnitudes, and after superposition, node V1 can present a stable DC bias voltage.

[0051] Based on the above explanation, Figure 4 This is a schematic diagram illustrating the relationship between RF power and bias voltage in an embodiment of this disclosure, as shown below. Figure 4 As shown, with the increase of RF power, when the third transistor M3 acts alone, the bias voltage of node V1 increases; when the fifth transistor M5 acts alone, the bias voltage of node V1 decreases; when the third transistor M3 and the fifth transistor M5 act together, node V1 exhibits a stable DC bias voltage.

[0052] Furthermore, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 form an open-loop circuit. Compared to a closed-loop circuit, the open-loop circuit offers higher stability and lower noise. Simultaneously, the open-loop circuit in this embodiment can achieve a lower output impedance. The impedance of node V1 (i.e., the impedance of the bias circuit) is: The impedance of node V1 is... Where gm3 is the transconductance of the third transistor M3; here, the size of the third transistor M3 is 2 to 10 times that of the second transistor M2. This effectively increases the transconductance of the three transistors M3, thereby reducing the impedance of the V1 node to the order of a few ohms, far lower than in existing technologies (e.g., ...). Figure 1 The impedance of the circuit is reduced, thereby improving the frequency response and stability of the circuit and helping to improve the overall performance of the circuit.

[0053] Figure 5 This is a schematic diagram showing the comparison between the impedance of the bias circuit in this embodiment and the impedance of a conventional bias circuit, as shown below. Figure 5 As shown, the impedance of the bias circuit in this disclosure is lower than that of existing circuits (i.e., Figure 1 The impedance of the bias circuit.

[0054] In some embodiments, please refer to Figure 3 The bias circuit 100 further includes: a second resistor R2; the source of the third transistor M3 (i.e., the second output terminal of the current mirror circuit 110) is connected to the output terminal of the bias circuit 100 through the second resistor R2; the output terminal of the bias circuit 100 is connected to the gate of the first transistor M1.

[0055] It should be noted that the second resistor R2 is added to adjust the impedance-frequency characteristics and bandwidth of the gate node of the first transistor M1, so that the first transistor M1 has optimal linearity. Here, the second resistor R2 is usually taken as a value of tens of ohms.

[0056] In some embodiments, please refer to Figure 3 The signal amplification circuit 210 further includes: a third capacitor C3, a fourth capacitor C4, an inductor L1, and a third voltage source VCC3; the gate of the first transistor M1 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 serves as the signal input terminal; the drain of the first transistor M1 is connected to the third voltage source VCC3 through the inductor L1, and is also connected to one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 serves as the signal output terminal; the source of the first transistor M1 is grounded.

[0057] Here, it should be noted that for node V1, the aforementioned second transistor M2, third transistor M3, fourth transistor M4, and fifth transistor M5 are transistors with the same structure. However, the first transistor M1 can be a transistor with a different structure than the second transistor M2, third transistor M3, fourth transistor M4, and fifth transistor M5.

[0058] In some embodiments, please refer to Figure 3 The first resistor R1, the second resistor R2, and the third resistor R3 are all fixed resistors; the first capacitor C1 and the second capacitor C2 are also fixed capacitors. This simplifies the design process of the bias circuit 100, making it easier to determine suitable component values ​​to meet circuit requirements.

[0059] In other embodiments, at least one of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can be a variable resistor; at least one of the first capacitor C1 and the second capacitor C2 can be a variable capacitor; thus, by adjusting the size of the capacitors and resistors, the bias voltage can be controllably increased or decreased as the RF signal power increases, making the application range of the bias circuit 100 wider.

[0060] This disclosure also provides a specific circuit structure diagram. Figure 6 This is a schematic diagram of the third component structure of the bias circuit of the power amplifier in an embodiment of this disclosure. For example... Figure 6 As shown, the bias circuit 100 includes: a current mirror circuit 110, a first adjustment circuit 120, a second adjustment circuit 130, and a power supply 140.

[0061] In this embodiment of the disclosure, please continue to refer to Figure 6 The current mirror circuit 110 includes: a second transistor M2, a third transistor M3, a first resistor R1, and a first capacitor C1; wherein, the drain of the second transistor M2 is connected to the second voltage source VCC2 through the current source IBIAS, and the drain of the second transistor M2 is connected to its gate; the source of the second transistor M2 is connected to the input terminal of the first adjustment circuit 120 (i.e., the drain of the fourth transistor M4); the gate of the second transistor M2 is connected to the gate of the third transistor M3 through the first resistor R1; the gate of the third transistor M3 is also connected to the ground terminal through the first capacitor C1, the drain of the third transistor M3 is connected to the first voltage source VCC1, the source of the third transistor M3 is connected to the input terminal of the second adjustment circuit 130 (i.e., the drain of the fifth transistor M5), and is also connected to the gate of the first transistor M1.

[0062] In some embodiments, please refer to Figure 6The current mirror circuit 110 also includes: a fourth resistor R4; and the first capacitor C1 is connected to the ground terminal through the fourth resistor R4. In this way, by connecting the switchable fourth resistor R4 in series with the first capacitor C1, the strength of the effect of the third transistor M3 on the bias voltage increase can be controlled. For example, increasing the resistance value of the fourth resistor R4 will weaken the effect of the bias voltage increase at node V1.

[0063] In this embodiment of the disclosure, please continue to refer to Figure 6 The first adjustment circuit 120 includes: a fourth transistor M4; the drain of the fourth transistor M4 is connected to the first output terminal of the current mirror circuit 110 (i.e., the source of the second transistor M2), the drain of the fourth transistor M4 is connected to its gate; and the source of the fourth transistor M4 is grounded.

[0064] In this embodiment of the disclosure, please continue to refer to Figure 6 The second adjustment circuit 130 includes: a fifth transistor M5, a third resistor R3, and a second capacitor C2; the drain of the fifth transistor M5 is connected to the second output terminal (i.e., the source of the third transistor M3) of the current mirror circuit 110; the gate of the fifth transistor M5 is connected to its drain through the third resistor R3, and the gate of the fifth transistor M5 is also connected to the ground terminal through the second capacitor C2; the source of the fifth transistor M5 is grounded.

[0065] In this embodiment of the disclosure, please continue to refer to Figure 6 The bias circuit 100 further includes: a second resistor R2; the source of the third transistor M3 is connected to the gate of the first transistor M1 through the second resistor R2.

[0066] In this embodiment of the disclosure, please continue to refer to Figure 6 The first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can be variable resistors; the first capacitor C1 and the second capacitor C2 can be variable capacitors. Thus, by changing the values ​​of the resistors and capacitors, the strength of the effect on lowering or raising the bias voltage can be controlled. For example, increasing the values ​​of the third resistor R3 and the second capacitor C2 can weaken the effect of lowering the bias voltage at node V1. Similarly, larger values ​​of the first resistor R1 and the second resistor R2 result in better isolation between the RF signal and power supply noise. However, the first resistor R1 and the second resistor R2 cannot be too large, to prevent the resistive noise generated by the first resistor R1 itself from interfering with the RF power amplifier, and to prevent increasing the baseband impedance of the second resistor R2 from worsening the memory effect.

[0067] Figure 7 This is a schematic diagram of the structure of the variable resistor in an embodiment of this disclosure, as shown below. Figure 7As shown, the variable resistor includes n resistors R and n switches S. The specific connection method is as follows: R31 is connected in series with S1, then connected in parallel across the terminals of R32 and S2 connected in series, and so on, and then connected in parallel across the terminals of R3n and Sn connected in series.

[0068] Figure 8 This is a schematic diagram of the structure of the variable capacitor in an embodiment of this disclosure, as shown below. Figure 8 As shown, the variable capacitor includes n capacitors C and n switches S. The specific connection method is as follows: C31 is connected in series with S1, then connected in parallel across the terminals of C32 and S2 connected in series, and so on, and then connected in parallel across the terminals of C3n and Sn connected in series.

[0069] Based on the above embodiments, by adjusting the values ​​of the capacitor and resistor, the bias voltage can be controllably increased or decreased as the RF signal power increases. Thus, by selecting appropriate bias voltage characteristics in the power amplifier, optimized linearity can be achieved.

[0070] It should be noted that the bias circuit provided in this embodiment is similar to the bias circuit in the above embodiments. For technical features not disclosed in detail in this embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0071] Figure 9 This is a schematic diagram illustrating the relationship between RF power and gain amplitude and bias voltage in embodiments of this disclosure, as shown below. Figure 9 As shown, the horizontal axis represents RF power, and the curve above represents the relationship between RF power and the gain amplitude (AMAM) of the power amplifier. The dashed line (i.e., conventional bias) refers to the fixed resistors and capacitors (i.e.,...) set in the bias circuit. Figure 3 In the circuit, R3 and C2), the solid line (i.e., the preferred bias) refers to the use of variable resistors and capacitors in the bias circuit (i.e., ... Figure 6 The circuit contains resistors R3, R4, and capacitor C2. The lower section illustrates the relationship between RF power and bias voltage. Dashed lines indicate fixed resistors and capacitors in the bias circuit (i.e., conventional bias), while solid lines indicate variable resistors and capacitors in the bias circuit (i.e., optimal bias).

[0072] from Figure 9 As can be seen, under normal bias, as the RF power increases, the bias voltage remains constant, and AMAM decreases. Under optimal bias, by adjusting the variable resistor and capacitor in the bias circuit, as the RF power increases, the bias voltage increases, and AMAM also increases, thereby increasing the linearity of the power amplifier. In other words, the bias circuit 100 provided in this disclosure can be equipped with AMAM adjustment functionality, which is beneficial for the power amplifier to achieve better linearity performance.

[0073] In addition, setting variable resistors and capacitors mainly increases the flexibility of adjusting the linearity of the bias circuit. After the power amplifier is built, the resistor and capacitor values ​​with better linearity can be selected digitally. For example, the power amplifier can operate at different frequencies, and the optimal resistor and capacitor values ​​for linearity are different at each frequency. By using variable resistors and capacitors, different resistor and capacitor values ​​can be set at different frequencies, thus enabling the power amplifier to have optimal linearity performance.

[0074] This disclosure also discloses a power amplifier device, which includes a power amplifier 210 (i.e., a signal amplifier circuit 200) and a bias circuit 100 of any of the power amplifiers in the above embodiments.

[0075] This disclosure also discloses an electronic device, which includes: the power amplifier device described in the above embodiments of this disclosure.

[0076] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0077] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0078] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0079] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0080] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0081] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0082] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A bias circuit for a power amplifier, characterized in that, The bias circuit includes: a current mirror circuit, a first adjustment circuit, a second adjustment circuit, and a power supply; The power supply is connected to the input terminal of the current mirror circuit and is used to supply power to the current mirror circuit. The first output terminal of the current mirror circuit is connected to the input terminal of the first adjustment circuit; The second output terminal of the current mirror circuit is connected to the input terminal of the second adjustment circuit, and is also connected to the output terminal of the bias circuit. The second output terminal of the current mirror circuit is used to provide a first bias voltage; the first adjustment circuit is used to adjust the first bias voltage; the second adjustment circuit is used to provide a second bias voltage; the first bias voltage and the second bias voltage are superimposed to output a bias voltage; The impedance of the bias circuit is within a preset impedance range.

2. The circuit according to claim 1, characterized in that, The current mirror circuit includes: a second transistor, a third transistor, and a first capacitor; In this configuration, the drain of the second transistor is connected to the power supply, and the drain of the second transistor is connected to its gate; the source of the second transistor is connected to the input terminal of the first adjustment circuit; and the gate of the second transistor is connected to the gate of the third transistor. The gate of the third transistor is also connected to the ground terminal through the first capacitor, the drain of the third transistor is connected to the power supply, the source of the third transistor is connected to the input terminal of the second adjustment circuit, and is also connected to the gate of the first transistor in the power amplifier.

3. The circuit according to claim 2, characterized in that, The third transistor is 2 to 10 times the size of the second transistor.

4. The circuit according to claim 2, characterized in that, The current mirror circuit further includes a first resistor, and the gate of the second transistor is connected to the gate of the third transistor through the first resistor.

5. The circuit according to claim 1, characterized in that, The first adjustment circuit includes: a fourth transistor; the drain of the fourth transistor is connected to the first output terminal of the current mirror circuit, and the drain of the fourth transistor is also connected to its gate; the source of the fourth transistor is grounded. And / or, the first adjustment circuit includes: a diode, the positive terminal of which is connected to the first output terminal of the current mirror circuit, and the negative terminal is grounded.

6. The circuit according to claim 1, characterized in that, The second adjustment circuit includes: a fifth transistor; the drain of the fifth transistor is connected to the second output terminal of the current mirror circuit; the gate of the fifth transistor is connected to its drain, and the gate of the fifth transistor is also connected to a ground terminal; the source of the fifth transistor is grounded.

7. The circuit according to claim 6, characterized in that, The second adjustment circuit further includes: a third resistor and a second capacitor. The gate of the fifth transistor is connected to its drain via the third resistor, and the gate is grounded via the second capacitor.

8. The circuit according to claim 2, characterized in that, The current mirror circuit further includes a fourth resistor, through which the first capacitor is connected to the ground terminal.

9. The circuit according to claim 1, characterized in that, The bias circuit further includes: a second resistor; The second output terminal of the current mirror circuit is connected to the output terminal of the bias circuit through the second resistor.

10. The circuit according to claim 2, 4, 7 or 8, characterized in that, The resistors and capacitors can be variable or fixed.

11. The circuit according to claim 1, characterized in that, There are multiple first adjustment circuits and / or second adjustment circuits, and the multiple adjustment circuits are connected in parallel.

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