An amplifier circuit capable of lifting the output 1 dB compression point

Abstract

The application provides an amplifier circuit capable of improving an output 1dB compression point. A simple dynamic bias circuit is introduced in a gate bias branch of a final stage amplifier transistor, so that the amplifier maintains an original static bias state when working in a small signal mode, and a static current is almost unchanged. In a large signal working state, the dynamic bias circuit can automatically collect an anode AC signal and improve the gate voltage after rectification, so as to expand the linear working range of the amplifier tube and effectively improve the output 1dB compression point (OP1), and the technical effect of improving the linearity and output performance of the amplifier without increasing the power consumption and the circuit complexity is realized.

Description

Technical Field

[0001] This application relates to the field of radio frequency integrated circuit technology, and in particular to an amplifier circuit that can improve the output compression point by 1dB. Background Technology

[0002] Currently, in radio frequency and microwave communication circuits, low-noise amplifiers or driver amplifiers manufactured using gallium arsenide (GaAs) technology are often used to achieve low-noise amplification and high linearity output. These amplifiers typically require a balance between gain, noise figure, and power output performance under limited supply voltage conditions. Due to the process characteristics of GaAs devices and to meet the low-power design requirements of the system, multi-stage common-source or Cascode structures are often used in engineering to achieve the required gain and noise performance. However, in multi-stage amplification structures, each stage transistor shares the supply voltage, reducing the drain-source voltage of each stage die and thus limiting the voltage dynamic range. When the input signal amplitude is large, the final stage die is prone to entering the nonlinear compression region, causing the amplifier's output 1dB compression point (OP1) to drop, thereby limiting the linear output power performance of the entire amplifier.

[0003] To improve OP1 performance, traditional solutions typically employ two methods: one is to increase the die's operating current by increasing the gate bias voltage, thereby expanding the dynamic range. However, this method leads to a significant increase in quiescent current, increasing power consumption and violating low-power design goals. The other method uses an adaptive active dynamic bias circuit. This method detects the amplifier's input or output signals and uses digital control logic to dynamically adjust the gate bias voltage, thereby automatically raising the operating point under large signal conditions to improve linearity. While such circuits can effectively improve OP1, their implementation requires complex signal detection, control, and bias tracking functions, resulting in complex circuit structures, large areas, high design costs, and stability issues. Utility Model Content

[0004] In view of this, the purpose of this application is to provide an amplifier circuit that can improve the output compression point by 1dB. By introducing a simple dynamic bias circuit into the gate bias branch of the amplifier's final stage transistor, the amplifier maintains its original static bias state during small-signal operation, and the static current remains almost unchanged. During large-signal operation, the dynamic bias circuit can automatically collect the drain AC signal and improve the gate voltage after rectification, thereby expanding the linear operating range of the transistor and effectively improving the output compression point (OP1). This achieves the technical effect of improving the amplifier's linearity and output performance without increasing power consumption and circuit complexity.

[0005] In a first aspect, embodiments of this application provide an amplifier circuit that can improve the output compression point by 1dB, including: an amplification unit, a static bias circuit, and a dynamic bias circuit; The amplification unit includes at least two first amplifying transistors and second amplifying transistors connected in series between the positive terminal of the power supply and ground. The first amplifying transistor is a pre-amplifier transistor, and the second amplifying transistor is a final amplifier transistor. The static bias circuit includes a first bias branch that provides a gate voltage for the first amplifying transistor and a second bias branch that provides a gate voltage for the second amplifying transistor. The second bias branch is located between the positive terminal of the power supply and ground, and has a gate power supply node connected to the gate of the second amplifying transistor. The dynamic bias circuit, connected between the drain of the second amplifying transistor and the gate power supply node, is configured to increase the gate voltage of the second amplifying transistor when the amplifier is in a large-signal operating state.

[0006] In conjunction with the first aspect, the embodiments of this application provide a first possible implementation of the first aspect, wherein the dynamic bias circuit includes a signal sampling branch, a rectification unit, and a bias resistor branch; The signal sampling branch has its input terminal connected to the drain of the second amplifying transistor and its output terminal connected to the rectifier unit. The rectifier unit is connected between the signal sampling branch and the gate power supply node; The bias resistor branch is located between the positive terminal of the power supply and ground, and connects the connection node between the signal sampling branch and the rectifier unit.

[0007] In conjunction with the first aspect, this application provides a second possible implementation of the first aspect, wherein the signal sampling branch is used to conduct the drain AC signal of the second amplifying transistor to the rectifier unit; The rectifier unit is used to forward rectify the drain AC signal into a pulsating current; The bias resistor branch is used to provide DC bias for the rectifier unit.

[0008] In conjunction with the first aspect, this application provides a third possible implementation of the first aspect, wherein the second bias branch includes a first resistor and a second resistor; The first resistor and the second resistor are connected in series; The series connection node between the first resistor and the second resistor serves as the gate power supply node.

[0009] In conjunction with the first aspect, this application provides a fourth possible implementation of the first aspect, wherein the signal sampling branch includes a first inductor and a first capacitor; The first inductor is connected at one end to the drain of the second amplifying transistor and at the other end to the first capacitor; The first capacitor is connected at one end to the first inductor and at the other end to the rectifier unit.

[0010] In conjunction with the first aspect, this application provides a fifth possible implementation of the first aspect, wherein the rectifier unit includes a diode; The diode has its anode connected to the signal sampling branch and its cathode connected to the gate power supply node.

[0011] In conjunction with the first aspect, this application provides a sixth possible implementation of the first aspect, wherein the bias resistor branch includes a third resistor and a fourth resistor; The third resistor is connected in series with the fourth resistor; The series connection node between the third resistor and the fourth resistor is connected to the connection node between the signal sampling branch and the rectifier unit.

[0012] In conjunction with the first aspect, this application provides a seventh possible implementation of the first aspect, wherein the drain of the first amplifying transistor is connected to the source of the second amplifying transistor, the gate is connected to the first bias branch, and the source is grounded; The drain of the second amplifying transistor is connected to the positive terminal of the power supply.

[0013] In conjunction with the first aspect, this application provides an eighth possible implementation of the first aspect, wherein the dynamic bias circuit further includes a second capacitor; The second capacitor has one end as the connection node between the gate power supply node and the rectifier unit, and the other end as ground.

[0014] In conjunction with the first aspect, this application provides a ninth possible implementation of the first aspect, wherein the gate of the first amplifying transistor serves as a radio frequency input terminal; The drain of the second amplifying transistor serves as the radio frequency output terminal.

[0015] This application provides an amplifier circuit capable of increasing the output compression point by 1dB, comprising: an amplification unit, a static bias circuit, and a dynamic bias circuit; the amplification unit includes at least two first amplifying transistors and a second amplifying transistor connected in series between the positive terminal of the power supply and ground, wherein the first amplifying transistor is a pre-amplifier and the second amplifying transistor is a final amplifier; the static bias circuit includes a first bias branch providing a gate voltage to the first amplifying transistor and a second bias branch providing a gate voltage to the second amplifying transistor, wherein the second bias branch is disposed between the positive terminal of the power supply and ground and has a gate power supply node connected to the gate of the second amplifying transistor; the dynamic bias circuit is connected between the drain of the second amplifying transistor and the gate power supply node, and is configured to increase the gate voltage of the second amplifying transistor when the amplifier is in a large-signal operating state. By introducing a simple dynamic bias circuit into the gate bias branch of the amplifier's final stage transistor, the amplifier maintains its original static bias state during small-signal operation, with the static current remaining almost unchanged. During large-signal operation, the dynamic bias circuit can automatically acquire the drain AC signal and, after rectification, boost the gate voltage, thereby expanding the linear operating range of the amplifier transistor and effectively improving the output compression point (OP1) by 1dB. This achieves the technical effect of improving the amplifier's linearity and output performance without increasing power consumption or circuit complexity. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 One of the schematic diagrams of an amplifier circuit that can improve the output compression point by 1dB is provided in an embodiment of this utility model; Figure 2 A second schematic diagram of an amplifier circuit that can improve the output compression point by 1dB, provided for an embodiment of this utility model; Figure 3 The third schematic diagram of an amplifier circuit that can improve the output compression point by 1dB, provided for an embodiment of this utility model. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this utility model and to simplify the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0022] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0023] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0024] In existing designs to improve OP1 performance, traditional approaches typically employ two methods: one is to increase the gate bias voltage to raise the die's operating current, thereby expanding the dynamic range. However, this method leads to a significant increase in quiescent current, increasing power consumption and violating low-power design goals. The other method uses an adaptive active dynamic bias circuit. This method detects the amplifier's input or output signals and uses digital control logic to dynamically adjust the gate bias voltage, thereby automatically raising the operating point under large signal conditions to improve linearity. While such circuits can effectively improve OP1, their implementation requires complex signal detection, control, and bias tracking functions, resulting in complex circuit structures, large areas, high design costs, and stability issues.

[0025] This application provides an amplifier circuit capable of increasing the output compression point by 1dB, comprising: an amplification unit, a static bias circuit, and a dynamic bias circuit; the amplification unit includes at least two first amplifying transistors and a second amplifying transistor connected in series between the positive terminal of the power supply and ground, wherein the first amplifying transistor is a pre-amplifier and the second amplifying transistor is a final amplifier; the static bias circuit includes a first bias branch providing a gate voltage to the first amplifying transistor and a second bias branch providing a gate voltage to the second amplifying transistor, wherein the second bias branch is disposed between the positive terminal of the power supply and ground and has a gate power supply node connected to the gate of the second amplifying transistor; the dynamic bias circuit is connected between the drain of the second amplifying transistor and the gate power supply node, and is configured to increase the gate voltage of the second amplifying transistor when the amplifier is in a large-signal operating state. By introducing a simple dynamic bias circuit into the gate bias branch of the amplifier's final stage transistor, the amplifier maintains its original static bias state during small-signal operation, with the static current remaining almost unchanged. During large-signal operation, the dynamic bias circuit can automatically acquire the drain AC signal and, after rectification, boost the gate voltage, thereby expanding the linear operating range of the amplifier transistor and effectively improving the output compression point (OP1) by 1dB. This achieves the technical effect of improving the amplifier's linearity and output performance without increasing power consumption or circuit complexity.

[0026] Please see Figure 1 , Figure 1 This is one of the schematic diagrams of an amplifier circuit that can improve the output compression point by 1dB, as provided in this embodiment.

[0027] like Figure 1 As shown in the illustration, the power amplifier with integrated transceiver switch provided in this embodiment includes: an amplification unit 10, a static bias circuit 20, and a dynamic bias circuit 30. The entire circuit forms a working loop between the positive power supply terminal VD and ground, used to achieve high gain, low noise, and excellent linearity RF signal amplification.

[0028] Specifically, the amplification unit 10 includes at least two first amplifying transistors M1 and M2 connected in series between the positive power supply terminal VD and ground. The first amplifying transistor M1 is a pre-amplifier, and the second amplifying transistor M2 is a final amplifier. The static bias circuit 20 includes a first bias branch 21 that provides the gate voltage to the first amplifying transistor M1 and a second bias branch 22 that provides the gate voltage to the second amplifying transistor M2. The second bias branch 22 is located between the positive power supply terminal VD and ground and has a gate power supply node connected to the gate of the second amplifying transistor M2. The dynamic bias circuit 30 is connected between the drain of the second amplifying transistor M2 and the gate power supply node and is configured to increase the gate voltage of the second amplifying transistor M2 when the amplifier is in a large-signal operating state.

[0029] Here, the amplification unit 10 adopts a multi-stage cascaded structure. This embodiment uses a two-stage example for illustration, including a first amplifying transistor M1 and a second amplifying transistor M2. The first amplifying transistor M1 serves as the pre-amplifier, used for primary amplification of the input RF signal; the second amplifying transistor M2 serves as the final amplifier, used for power amplification of the signal at higher power output. The source of the first amplifying transistor M1 is connected to ground, and its drain is electrically connected to the source of the second amplifying transistor M2, thus forming a typical cascaded amplification structure. The gate of the first amplifying transistor M1 is connected to the RF input port for receiving external RF signals; the drain of the second amplifying transistor M2 is connected to the positive power supply terminal VD and also serves as the RF output port of the amplifier, outputting the amplified signal to the subsequent circuit through a load network.

[0030] In the small-signal operation mode, the operating point of the amplification unit 10 is set by the static bias circuit 20. The static bias circuit 20 provides stable gate bias voltages for the first amplifying transistor M1 and the second amplifying transistor M2, thereby ensuring that the two amplification units are in the appropriate linear operating range. The first bias branch 21 provides bias voltage to M1, which can be source self-biased or fixed biased. Its voltage value is determined according to the device threshold voltage and the required quiescent current to ensure that the front-end amplification section obtains sufficient gain and maintains a low noise figure.

[0031] Here, the second bias branch 22 is used to form the static bias voltage of the second amplifying transistor M2. In this embodiment, it is located between the positive power supply terminal VD and ground, and the gate potential is determined by a resistor voltage divider structure. The second bias branch 22 includes a first resistor R1 and a second resistor R2, which are connected in series. One end of R1 is connected to the positive power supply terminal VD, and one end of R2 is grounded. The connection node between R1 and R2 constitutes the gate power supply node. This node is directly connected to the gate terminal of the second amplifying transistor M2, thereby providing a static bias voltage for M2.

[0032] By adjusting the resistance ratio of R1 and R2, the potential of the gate power supply node can be set, achieving bias voltage adjustment under different operating conditions. For example, when the resistances of R1 and R2 are equal, the gate voltage is approximately half the power supply voltage; when the resistance of R1 is larger, the gate bias voltage decreases, and the quiescent current decreases; conversely, it increases. Through this simple resistor voltage division method, the quiescent operating point of the final stage amplifier transistor M2 can be accurately set, ensuring that the amplifier has good linearity and stability within the small signal input range.

[0033] Furthermore, the static bias circuit 20 plays a crucial role in the entire circuit. On the one hand, it ensures that each stage of the transistors has a stable bias operating point under small-signal conditions, preventing current drift caused by temperature or process fluctuations. On the other hand, it provides a reference for the dynamic bias circuit 30. When the circuit operates under normal small-signal input, the operating voltage and current of M1 and M2 remain constant, the dynamic bias circuit 30 is in a non-conducting state, and the overall power consumption of the circuit is extremely low.

[0034] Here, when the input signal amplitude increases and the output voltage approaches the nonlinear region, the drain voltage of M2 changes significantly, and the dynamic bias circuit 30 starts to work. The path connected between the drain of M2 and the gate power supply node will dynamically compensate the gate bias voltage, causing the gate potential of M2 to rise instantaneously, which is equivalent to temporarily increasing the operating current, thereby expanding the linear operating range of M2.

[0035] In this process, the static bias circuit 20 and the dynamic bias circuit 30 work together. The static bias circuit 20 is responsible for setting a stable initial operating point to ensure the noise performance and power consumption of the circuit under small signal conditions; the dynamic bias circuit 30 is responsible for voltage compensation under large signal conditions, so that the output power maintains a longer linear response range before entering the compression region, thereby significantly improving the output compression point by 1dB.

[0036] Thus, through the above structural design, the entire amplifier behaves as a traditional two-stage amplifier structure when operating with small signals, with almost constant quiescent current, low power consumption, and low noise; while in the large signal state, the dynamic bias circuit can adaptively adjust the gate voltage of the final stage transistor without the need for external control circuits or digital logic adjustment modules, thereby achieving automatic dynamic gain control and linearity improvement.

[0037] Preferably, in this embodiment, the first amplifying transistor M1 and the second amplifying transistor M2 are GaAs HEMT devices, but GaN, InP, or other high-frequency, high-linearity field-effect transistors can also be used. The bias resistor can be a thin-film resistor or a chip resistor to ensure resistance stability and temperature consistency.

[0038] Preferably, the entire circuit can be implemented in a single power supply mode and can be integrated into the RF front-end module or power amplifier chip. It has the advantages of simple structure, easy implementation, low power consumption and high linearity. It is particularly suitable for high-frequency applications that require an output compression point of 1dB, such as wireless communication systems, radar transmitting modules, and power drive amplifiers. Please see Figure 2 , Figure 2 This is the second schematic diagram of an amplifier circuit that can improve the output compression point by 1dB, as provided in this embodiment.

[0039] exist Figure 1 Based on the same concept, such as Figure 2 As shown, the dynamic bias circuit 30 includes a signal sampling branch 31, a rectification unit 32, and a bias resistor branch 33. Figure 1 Based on the amplifier circuit shown, the dynamic bias circuit 30 is further implemented as including a signal sampling branch 31, a rectification unit 32, and a bias resistor branch 33. The dynamic bias circuit 30 is connected to the drain and gate power supply node of the second amplifying transistor M2, forming a dynamic bias structure that can automatically adjust the gate voltage under large signal operating conditions. The design of the entire dynamic bias circuit 30 is based on the same overall concept as the amplifying unit 10 and the static bias circuit 20, aiming to dynamically improve the gate bias of M2 through signal self-feedback without changing the original static characteristics and power consumption of the amplifier.

[0040] Specifically, the input terminal of the signal sampling branch 31 is connected to the drain of the second amplifying transistor M2, and the output terminal is connected to the rectifier unit 32; the rectifier unit 32 is connected between the signal sampling branch 31 and the gate power supply node; the bias resistor branch 33 is located between the positive power supply terminal VD and ground, and is connected to the connection node between the signal sampling branch 31 and the rectifier unit 32.

[0041] Here, the input terminal of the signal sampling branch 31 is connected to the drain of the second amplifying transistor M2 to acquire the high-frequency AC signal at the amplifier output. When the amplifier operates in a large-signal state, there is a significant AC voltage swing at the drain of M2. The signal sampling branch 31, through its electrical connection to the drain, couples this AC signal to the rectifier unit 32. The output terminal of the signal sampling branch 31 is connected to the input terminal of the rectifier unit 32, transmitting only the AC component and blocking the DC component when the radio frequency signal passes through, thereby ensuring that the quiescent operating point is unaffected.

[0042] Here, the input of rectifier unit 32 is connected to the output of signal sampling branch 31, and the output is connected to the gate power supply node. The function of rectifier unit 32 is to convert the AC signal from the drain of M2 into a unidirectional pulsating current, so that a momentary positive voltage increment can be formed when the AC signal peak occurs, and this increment acts on the gate bias voltage of M2 through its connection with the gate power supply node. Through this signal rectification and superposition method, when the amplifier is operating in a high-power output state, the gate voltage of M2 will be increased accordingly, thereby expanding its linear operating range and improving the output 1dB compression point.

[0043] Here, the bias resistor branch 33 is positioned between the positive terminal VD of the power supply and ground to provide a DC bias reference for the rectifier unit 32 and to limit the quiescent current of the rectifier path. The bias resistor branch 33 is connected to the connection node between the signal sampling branch 31 and the rectifier unit 32. This connection node provides a pre-bias potential to the rectifier unit 32, enabling the rectifier to quickly turn on without significant delay when an AC signal arrives.

[0044] In this circuit, the bias resistor branch 33 provides only a very small quiescent current when the amplifier is operating with a small signal, thus not significantly increasing the overall power consumption of the amplifier. When the amplifier is operating with a large signal input, the drain AC signal is coupled through the signal sampling branch 31 and converted into a DC bias signal by the rectifier unit 32. The bias resistor branch 33 works in conjunction to form a stable current path, thereby generating a voltage boost effect at the gate power supply node and realizing dynamic bias adjustment of the second amplifying transistor M2.

[0045] Thus, through the above structural design, the dynamic bias circuit 30 can remain silent in the small signal state, without affecting the normal static bias and low noise performance of the amplifier; in the large signal state, it will automatically activate and increase the gate voltage of the final stage transistor through the self-inductive adjustment of the drain signal, thereby improving the output linearity and suppressing the compression effect.

[0046] Please see Figure 3 , Figure 3 This is the third schematic diagram of a power amplifier with an integrated transceiver switch provided in this embodiment.

[0047] exist Figures 1-2 Based on the same concept, such as Figure 3As shown, the signal sampling branch 31 includes a first inductor L1 and a first capacitor C1; the rectifier unit 32 includes a diode D1; and the bias resistor branch includes a third resistor R3 and a fourth resistor R4. Based on the aforementioned overall concept, this circuit introduces specific passive and active components to form a complete signal detection and dynamic adjustment path, thereby realizing the automatic boosting function of the gate bias voltage of the second amplifying transistor M2. The three circuits work together to form a signal feedback path from the drain of M2 to its gate power supply node.

[0048] Specifically, one end of the first inductor L1 is connected to the drain of the second amplifying transistor M2, and the other end is connected to the first capacitor C1; one end of the first capacitor C1 is connected to the first inductor L1, and the other end is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the gate power supply node.

[0049] Here, the signal sampling branch 31 collects the AC signal from the drain of the second amplifying transistor M2 and introduces it into the rectifier unit. One end of the first inductor L1 is connected to the drain of M2, and the other end is connected to the first capacitor C1. L1 serves to block DC and conduct AC, and its inductance value needs to be selected to balance AC coupling bandwidth and resonance suppression. In the radio frequency band, L1 exhibits low impedance, allowing the drain AC voltage to be effectively coupled through; while it exhibits high impedance to the DC component, thereby preventing the drain DC voltage from leaking to the subsequent circuit.

[0050] In this circuit, one end of the first capacitor C1 is connected to L1, and the other end is connected to the anode of diode D1, forming an AC coupling channel. The main function of C1 is to isolate the DC component, allowing only high-frequency AC signals to pass through. Together with L1, C1 forms an impedance matching network, ensuring good energy coupling efficiency of the drain signal when it reaches the rectifier unit. Through the filtering characteristics of L1 and C1 connected in series, the signal sampling branch can efficiently separate the AC component of the drain signal and transmit it to the rectifier stage without affecting the DC stability of the main amplifier path.

[0051] Here, the core component of the rectifier unit 32 is diode D1. The anode of D1 is connected to the first capacitor C1, and the cathode is connected to the gate power supply node. D1 performs rectification; when the instantaneous voltage of the drain AC signal exceeds its conduction threshold, D1 is driven to conduct, converting the positive half-cycle of the AC signal into a DC pulse current. This current is superimposed on the static bias voltage formed by the second bias branch through the gate power supply node, thereby causing the gate voltage of M2 to rise for a short time. When the amplitude of the drain signal is small, D1 remains in the off state, the circuit maintains a static bias state, and does not affect the gate bias voltage.

[0052] Preferably, D1 is typically an RF Schottky diode or other high-frequency fast-response device to ensure that it has extremely low reverse recovery time and small junction capacitance under high-frequency operating conditions, thereby achieving fast response and low-distortion rectification.

[0053] Here, bias resistor branch 33 is used to provide a suitable DC bias for the rectifier unit and stabilize its operating state. This branch consists of the third resistor R3 and the fourth resistor R4 connected in series. One end of R3 is connected to the positive terminal VD of the power supply, and one end of R4 is grounded. The connection node between R3 and R4 is connected to the anode of D1. This structure forms a stable voltage divider network, providing a bias voltage slightly higher than ground potential to the anode of D1, enabling D1 to enter the conduction state more quickly when a signal arrives.

[0054] Optionally, the resistance values ​​of R3 and R4 are generally chosen to be relatively high to ensure that the current generated in the bias branch is minimal, thereby maintaining rectification sensitivity without increasing the system's static power consumption. This bias network can also suppress mis-conduction of D1 under weak signal or noise conditions, ensuring that the dynamic bias only functions under large signal operating conditions.

[0055] Specifically, during amplifier operation, when the input signal is small, the AC voltage at the drain of M2 is insufficient to drive D1 to conduct, and the entire dynamic bias circuit 30 is in a static state. The gate bias voltage of M2 is determined only by the second bias branch, and the amplifier maintains normal small-signal gain and noise performance. As the input signal increases, the amplitude of the AC voltage at the drain of M2 gradually increases. L1 and C1 couple this AC signal to the anode of D1. When the signal peak exceeds the conduction threshold of D1, D1 begins to conduct, and the positive component of the drain signal is converted into current flowing to the gate power supply node through D1, causing the gate voltage of M2 to rise instantaneously. The bias resistor branch 33 forms a current loop at this time, stabilizing the rectified output and providing a return path for D1. As the signal period changes, D1 periodically turns on and off, and the gate voltage exhibits a characteristic of dynamically changing with the input signal strength, thereby automatically raising the operating point and expanding the linear range when the amplifier outputs a large signal.

[0056] Through the above structural design, the signal sampling branch 31, the rectifier unit 32, and the bias resistor branch 33 work together to achieve an adaptive feedback mechanism from the drain signal to the gate bias voltage. Compared with traditional digital control dynamic bias schemes, this circuit relies entirely on the analog signal path to complete the bias adjustment, requiring no external control logic, resulting in fast response, simple structure, and extremely low power consumption. In small-signal states, it does not participate in bias adjustment and does not affect amplifier performance; in large-signal states, it automatically enhances the bias voltage of the final stage transistor, raising the amplifier output compression point by 1dB, thus enabling the amplifier to have higher linearity and output dynamic range.

[0057] As one possible implementation, the connection node between the gate power supply node and the cathode of D1 is grounded through the second capacitor C2.

[0058] It should be noted that the structure described in this embodiment can be widely applied in the design of RF, microwave, and millimeter-wave power amplifiers, and is particularly suitable for wireless communication systems with strict requirements for power consumption, linearity, and output performance. The gate of the first amplifying transistor M1 serves as the RF input terminal RFIN, and the drain of the second amplifying transistor M2 serves as the RF output terminal RFOUT. By reasonably selecting the parameters of L1, C1, R3, R4, and D1, the dynamic response rate and bias amplitude can be flexibly adjusted according to different frequency bands and device characteristics, so that the entire amplifier can obtain the best linear output characteristics while ensuring low power consumption.

[0059] This embodiment provides an amplifier circuit that can increase the output compression point by 1dB, comprising: an amplification unit, a static bias circuit, and a dynamic bias circuit; the amplification unit includes at least two first amplifying transistors and a second amplifying transistor connected in series between the positive terminal of the power supply and ground, wherein the first amplifying transistor is a pre-amplifier and the second amplifying transistor is a final amplifier; the static bias circuit includes a first bias branch providing a gate voltage to the first amplifying transistor and a second bias branch providing a gate voltage to the second amplifying transistor, wherein the second bias branch is disposed between the positive terminal of the power supply and ground and has a gate power supply node connected to the gate of the second amplifying transistor; the dynamic bias circuit is connected between the drain of the second amplifying transistor and the gate power supply node, and is configured to increase the gate voltage of the second amplifying transistor when the amplifier is in a large-signal operating state. By introducing a simple dynamic bias circuit into the gate bias branch of the amplifier's final stage transistor, the amplifier maintains its original static bias state during small-signal operation, with the static current remaining almost unchanged. During large-signal operation, the dynamic bias circuit can automatically acquire the drain AC signal and, after rectification, boost the gate voltage, thereby expanding the linear operating range of the amplifier transistor and effectively improving the output compression point (OP1) by 1dB. This achieves the technical effect of improving the amplifier's linearity and output performance without increasing power consumption or circuit complexity.

[0060] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. An amplifier circuit capable of increasing the output compression point by 1 dB, characterized in that, include: Amplification unit, static bias circuit and dynamic bias circuit; The amplification unit includes at least two first amplifying transistors and second amplifying transistors connected in series between the positive terminal of the power supply and ground. The first amplifying transistor is a pre-amplifier transistor, and the second amplifying transistor is a final amplifier transistor. The static bias circuit includes a first bias branch that provides a gate voltage for the first amplifying transistor and a second bias branch that provides a gate voltage for the second amplifying transistor. The second bias branch is located between the positive terminal of the power supply and ground, and has a gate power supply node connected to the gate of the second amplifying transistor. The dynamic bias circuit, connected between the drain of the second amplifying transistor and the gate power supply node, is configured to increase the gate voltage of the second amplifying transistor when the amplifier is in a large-signal operating state.

2. The amplifier circuit that can improve the output compression point by 1dB according to claim 1, characterized in that, The dynamic bias circuit includes a signal sampling branch, a rectification unit, and a bias resistor branch. The signal sampling branch has its input terminal connected to the drain of the second amplifying transistor and its output terminal connected to the rectifier unit. The rectifier unit is connected between the signal sampling branch and the gate power supply node; The bias resistor branch is located between the positive terminal of the power supply and ground, and connects the connection node between the signal sampling branch and the rectifier unit.

3. The amplifier circuit that can improve the output compression point by 1dB according to claim 2, characterized in that: The signal sampling branch is used to conduct the drain AC signal of the second amplifying transistor to the rectifier unit; The rectifier unit is used to forward rectify the drain AC signal into a pulsating current; The bias resistor branch is used to provide DC bias for the rectifier unit.

4. The amplifier circuit that can improve the output compression point by 1dB according to claim 1, characterized in that, The second bias branch includes a first resistor and a second resistor; The first resistor and the second resistor are connected in series; The series connection node between the first resistor and the second resistor serves as the gate power supply node.

5. The amplifier circuit that can improve the output compression point by 1dB according to claim 2, characterized in that, The signal sampling branch includes a first inductor and a first capacitor; The first inductor is connected at one end to the drain of the second amplifying transistor and at the other end to the first capacitor; The first capacitor is connected at one end to the first inductor and at the other end to the rectifier unit.

6. The amplifier circuit capable of increasing the output compression point by 1dB according to claim 2, characterized in that, The rectifier unit includes diodes; The diode has its anode connected to the signal sampling branch and its cathode connected to the gate power supply node.

7. The amplifier circuit capable of increasing the output compression point by 1dB according to claim 2, characterized in that, The bias resistor branch includes a third resistor and a fourth resistor; The third resistor is connected in series with the fourth resistor; The series connection node between the third resistor and the fourth resistor is connected to the connection node between the signal sampling branch and the rectifier unit.

8. The amplifier circuit that can improve the output compression point by 1dB according to claim 1, characterized in that: The drain of the first amplifying transistor is connected to the source of the second amplifying transistor, the gate is connected to the first bias branch, and the source is grounded. The drain of the second amplifying transistor is connected to the positive terminal of the power supply.

9. The amplifier circuit capable of increasing the output compression point by 1 dB according to claim 1, characterized in that, The dynamic bias circuit also includes a second capacitor; The second capacitor has one end as the connection node between the gate power supply node and the rectifier unit, and the other end as ground.

10. The amplifier circuit capable of increasing the output compression point by 1 dB according to claim 1, characterized in that: The gate of the first amplifying transistor serves as the radio frequency input terminal; The drain of the second amplifying transistor serves as the radio frequency output terminal.

Images