Semiconductor switching device driven by negative voltage

Abstract

The application provides a negative voltage driven semiconductor switching device, and belongs to the technical field of semiconductors. The semiconductor switching device comprises at least one forward conduction array and at least one reverse conduction array, each forward conduction array and each reverse conduction array is arranged on the same semiconductor substrate; each forward / reverse conduction array comprises a plurality of high electron mobility transistors, the structure and process parameters of each high electron mobility transistor are the same; the gate of each forward conduction array is connected with the output end of an external driving circuit, the gate of each reverse conduction array is connected with the source, the drain of each forward / reverse conduction array is connected with a main power loop, and the source of each forward / reverse conduction array is grounded. The application can solve the contradiction between improving the anti-interference ability and reducing the reverse current flow loss of a gallium nitride semiconductor switching device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a negative voltage driven semiconductor switching device. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs), as lateral conductivity devices, lack the intrinsic body diode for reverse freewheeling formed by the PN junction, as found in silicon metal-oxide-semiconductor field-effect transistors (Si MOSFETs). Although the GaN HEMT channel itself possesses reverse conduction capability, its reverse conduction voltage drop is not an intrinsic body diode voltage drop, but rather a voltage drop strongly correlated with the gate drive voltage. To avoid high freewheeling losses due to excessively high reverse conduction voltage drops, GaN HEMTs typically employ zero-voltage turn-off. However, since the threshold voltage of GaN HEMTs is only around 1.4V, GaN HEMTs are susceptible to noise interference.

[0003] Currently, to address the gate noise interference problem of GaN HEMTs, a negative voltage turn-off drive method is often used to provide a larger noise margin for the GaN HEMT, thereby reducing noise interference. However, this method results in a high reverse conduction voltage drop during the dead time when the GaN HEMT needs reverse freewheeling, leading to significant freewheeling losses and affecting the overall efficiency of the power system. Conversely, using a zero-voltage turn-off drive method to reduce the freewheeling losses of the GaN HEMT reduces the noise margin, making it more susceptible to noise interference. Therefore, the inherent frame characteristics of GaN HEMTs make it difficult to reconcile noise immunity with low reverse freewheeling losses. To circumvent this contradiction, most manufacturers often connect a Schottky diode in parallel with the GaN HEMT to provide a low-voltage-drop reverse freewheeling path. However, this increases the production cost and design complexity of the GaN HEMT and may also degrade its high-frequency switching performance, generating additional voltage ringing and losses.

[0004] Therefore, there is an urgent need for a low-parasitic and reliable method to reconcile the contradiction between the anti-interference capability and low reverse freewheeling loss of GaN HEMT, thereby improving the performance of the power supply system. Utility Model Content

[0005] The purpose of this application is to provide a negative voltage driven semiconductor switching device that can resolve the contradiction between improving the anti-interference capability and reducing the reverse freewheeling loss of gallium nitride semiconductor switching devices.

[0006] The embodiments of this application are implemented as follows: A first aspect of the present application provides a negative voltage driven semiconductor switching device, the semiconductor switching device comprising: at least one forward conducting array and at least one reverse conducting array, wherein each forward conducting array and each reverse conducting array are deployed on the same semiconductor substrate; Each forward-conducting array includes multiple first high electron mobility transistors, and each reverse-conducting array includes multiple second high electron mobility transistors. The first high electron mobility transistors and the second high electron mobility transistors have the same structure and process parameters. The gate of each forward-conducting array is connected to the output terminal of the external driving circuit, the gate of each reverse-conducting array is connected to the source of each reverse-conducting array, the drain of each forward-conducting array and the drain of each reverse-conducting array are connected to the main power circuit, and the source of each forward-conducting array and the source of each reverse-conducting array are grounded.

[0007] As one possible implementation, each forward-conducting array and each reverse-conducting array are arranged side-by-side on the same semiconductor substrate.

[0008] As one possible implementation, the drain of each forward-conducting array is connected to the drain of each reverse-conducting array, and the total channel width occupied by each forward-conducting array is greater than the total channel width occupied by each reverse-conducting array.

[0009] As one possible implementation, each forward-conducting array and each reverse-conducting array are alternately distributed on the same semiconductor substrate.

[0010] As one possible implementation, each forward-conducting array is deployed in a first region on a semiconductor substrate, and each reverse-conducting array is deployed in a second region on a semiconductor substrate, with a transition isolation region provided between the first region and the second region.

[0011] As one possible implementation, the first area occupied by the first region on the semiconductor substrate and the second area occupied by the second region on the semiconductor substrate satisfy a preset ratio.

[0012] As one possible implementation, the same semiconductor substrate includes: a substrate, a buffer layer, and a gallium nitride channel, wherein the buffer layer is generally located on the substrate, and the gallium nitride channel is generally located on the buffer layer.

[0013] As one possible implementation, the gate of each first high electron mobility transistor in each forward-conducting array is connected to the output terminal of the external driving circuit, the drain of each first high electron mobility transistor in each forward-conducting array is connected to the main power circuit, and the source of each first high electron mobility transistor in each forward-conducting array is grounded. When the external driving circuit outputs a high level to the gate of each first high electron mobility transistor in each forward-conducting array, each first high electron mobility transistor is turned on under the action of the high level. Conversely, when the external driving circuit outputs a negative voltage signal to the gate of each first high electron mobility transistor in each forward-conducting array, each first high electron mobility transistor is turned off under the action of the high level.

[0014] As one possible implementation, the gate of each second high electron mobility transistor in each reverse conduction array is connected to the source of each second high electron mobility transistor in each reverse conduction array, the drain of each second high electron mobility transistor in each reverse conduction array is connected to the main power circuit, and the source of each second high electron mobility transistor in each reverse conduction array is grounded. When the external driving circuit outputs a negative voltage signal to the gate of the forward-conducting array, a reverse voltage is formed between the source and drain of each second high electron mobility transistor in each reverse-conducting array. When the reverse voltage is greater than the conduction voltage threshold of each second high electron mobility transistor, each second high electron mobility transistor is turned on, providing a reverse freewheeling path for the semiconductor switching device.

[0015] The beneficial effects of the embodiments of this application include: The present application provides a negative voltage driven semiconductor switching device, which is formed by deploying multiple high electron mobility transistors with the same structure and parameters on the same semiconductor substrate. The device is divided into a forward conduction array by the electrical connection relationship of the high electron mobility transistors, and a small part of the second high electron mobility transistors are divided into a reverse conduction array. In the forward-conducting array, the gates of multiple first high electron mobility transistors are connected together to form the gate of the forward-conducting array. The sources of multiple first high electron mobility transistors in the forward-conducting array are connected together to form the source of the forward-conducting array. The drains of multiple first high electron mobility transistors in the forward-conducting array are connected together to form the source of the forward-conducting array. The gate of the forward-conducting array is connected to the output terminal of the external driving circuit. In the reverse-conducting array, the gates of multiple second high electron mobility transistors are connected together to form the gate of the reverse-conducting array. The sources of multiple second high electron mobility transistors in the reverse-conducting array are connected together to form the source of the reverse-conducting array. The drains of multiple second high electron mobility transistors in the reverse-conducting array are connected together to form the source of the reverse-conducting array. The gate and source of the reverse-conducting array are shorted. The drains of both the forward-conducting and reverse-conducting arrays are connected to the main power circuit. The sources of both the forward-conducting and reverse-conducting arrays are grounded. Furthermore, when the external driving circuit outputs a positive voltage drive signal, the forward-conducting array turns on, and the reverse-conducting array turns off, allowing the current in the main power circuit to flow from the drain to the source of the forward-conducting array. When the external driving circuit outputs a negative voltage drive signal, the forward-conducting array turns off until the reverse voltage between the source and drain of the reverse-conducting array reaches the conduction threshold of the reverse-conducting array, at which point the reverse-conducting array turns on, providing a low-loss reverse freewheeling path for the semiconductor switching device. Thus, the reverse conduction of the semiconductor switching device is unaffected by the gate voltage and can provide a low-loss reverse freewheeling path even under a negative voltage signal. This resolves the contradiction between improving the anti-interference capability and reducing the reverse freewheeling loss of gallium nitride semiconductor switching devices. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the structure of a first type of negative voltage driven semiconductor switching device provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of a second type of negative voltage driven semiconductor switching device provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of a third type of negative voltage driven semiconductor switching device provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of a fourth type of negative voltage driven semiconductor switching device provided in the embodiments of this application; Figure 5 A schematic diagram of a flyback switching power supply provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an existing negative voltage driven flyback switching power supply circuit. Figure 7 This is a graph showing the change in conduction voltage provided in an embodiment of this application.

[0018] Figure descriptions: 10: Semiconductor switching device; 101: Forward conduction array; 1011: First high electron mobility transistor; 102: Reverse conduction array; 1021: Second high electron mobility transistor; 20: Flyback switching power supply; 201: Drive circuit; 2011: Positive power supply drive circuit; 2012: Negative power supply drive circuit; 202: Flyback converter; 2021: Transformer; 203: Spike absorption circuit; 204: Rectifier and filter circuit. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In the description of this application, it should be noted that the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] As modern power electronics technology continues to advance towards higher efficiency, higher power density, and higher switching frequencies, semiconductor materials such as silicon nitride (SiN) and gallium nitride (GaN) are gradually replacing traditional silicon-based materials as core materials in the field of power devices. Among them, high electron mobility transistors (HEMs) built on gallium nitride semiconductor materials enjoy advantages such as lower on-resistance and lower parasitic inductance due to their unique two-dimensional electron gas channel characteristics. This advantage has led to their widespread application in consumer fast charging, data center power supplies, and on-board chargers for new energy vehicles. However, when these HEMs are used in switching power supply systems, the lack of an intrinsic body diode for reverse freewheeling prevents them from achieving reverse freewheeling.

[0025] Specifically, as a lateral conductivity device, the gallium nitride (GaN) high electron mobility transistor (HEMT) lacks an intrinsic body diode for reverse freewheeling, unlike the longitudinal PN junction in a traditional silicon metal-oxide-semiconductor (SiO2) transistor. This means that the GaNH transistor cannot perform reverse freewheeling through an intrinsic body diode. Although the channel of the GaNH transistor itself possesses reverse conductivity, its reverse conduction voltage drop is strongly correlated with the gate drive voltage. This makes the reverse conduction capability of the GaNH transistor susceptible to the gate drive voltage, resulting in poor interference immunity.

[0026] To address the vulnerability of gallium nitride (GaN) high electron mobility transistors (HETTs) to gate drive voltage interference, some semiconductor factories employ negative voltage drive to turn off GaNTs. While this method provides a larger noise margin to reduce gate drive voltage interference, it also results in a high reverse conduction voltage drop during the dead time when the GaNT requires reverse freewheeling. This leads to significant freewheeling losses and impacts the overall efficiency of the power system. Other semiconductor factories use zero-voltage drive to turn off GaNTs. While this reduces the reverse conduction voltage drop, it lowers the noise margin, making the GaNT susceptible to noise-induced false triggering and reducing its reliability.

[0027] Therefore, the inherent framework characteristics of gallium nitride (GaN) high electron mobility transistors (HEP transistors) create a seemingly irreconcilable contradiction between their noise immunity and low reverse freewheeling loss. Furthermore, in the event of unexpected failure or under certain extreme operating conditions, the reverse conduction capability of a GaN HEP transistor may be limited. Without external protection, the inductive load current may cause a severe reverse overvoltage spike, which can permanently damage the GaN HEP transistor.

[0028] To circumvent the trade-off between noise immunity and low reverse freewheeling loss in gallium nitride (GaN) high electron mobility transistors (HEP transistors), most manufacturers typically connect a Schottky diode in parallel with the external GaN HEP transistor. This Schottky diode provides a low-dropout reverse freewheeling path for the GaN HEP transistor. However, this approach not only increases the packaging cost, printed circuit board layout area, and design complexity of the GaN HEP transistor, but also introduces external parasitic inductance. This deteriorates the high-frequency switching performance of the GaN HEP transistor, resulting in additional voltage ringing and losses.

[0029] To address this, this application provides a negative-voltage driven semiconductor switching device. Multiple high-electron-mobility transistors (HEMTs) with identical structures and process parameters are deployed on the same semiconductor substrate. The HEMTs are divided into at least one forward-conducting array and at least one reverse-conducting array based on their electrical connections. In each forward-conducting array, the gates of all HEMTs are connected to the output of an external driving circuit. In each reverse-conducting array, the gates of all HEMTs are connected to their own sources. The drains of all HEMTs are connected to the main power circuit, and the sources of all HEMTs are grounded. Furthermore, when the external driving circuit outputs a negative voltage signal, each forward-conducting array is turned off, and a reverse voltage is formed between the sources and drains of each reverse-conducting array. Once the reverse voltage reaches a conduction threshold, the HEMTs in each reverse-conducting array provide a reverse freewheeling path for the semiconductor switching device. This resolves the contradiction between improving the anti-interference capability and reducing reverse freewheeling losses in gallium nitride semiconductor switching devices.

[0030] The negative voltage driven semiconductor switching device provided in the embodiments of this application will be explained in detail below with reference to the accompanying drawings.

[0031] It is worth noting that this application takes the application of semiconductor switching devices in flyback switching power supplies as an example, which does not mean that the semiconductor switching devices provided in the embodiments of this application can only be applied to flyback switching power supplies. The semiconductor switching devices provided in the embodiments of this application can also be applied to bridge circuits, drive circuits, etc., and this application does not make specific limitations in this regard.

[0032] When semiconductor switching devices are used in flyback switching power supplies, the main power circuit is provided by the transformer and other main power devices in the flyback switching power supply.

[0033] Figure 1 A schematic diagram of a negative voltage driven semiconductor switching device provided in this application is shown below. Figure 1 This application provides a negative voltage driven semiconductor switching device 10, including at least one forward conducting array 101 and at least one reverse conducting array 102, wherein each forward conducting array 101 and each reverse conducting array 102 are deployed on the same semiconductor substrate.

[0034] Optionally, the semiconductor switching device 10 is an electronic switching device made of semiconductor material. The semiconductor switching device 10 is used to control the current flow of the main power circuit, specifically by switching the conductivity state of its internal semiconductor structure under the control of a control signal applied by an external driving circuit. The semiconductor material can be silicon, silicon carbide, gallium nitride, etc. In this application, high-performance gallium nitride is used as the semiconductor material for the semiconductor switching device 10.

[0035] Each forward-conducting array 101 includes multiple first high electron mobility transistors 1011, and each reverse-conducting array 102 includes multiple second high electron mobility transistors 1021. The first high electron mobility transistors 1011 and the second high electron mobility transistors 1021 have the same structure and process parameters.

[0036] Optionally, both the first high electron mobility transistor 1011 and the second high electron mobility transistor 1021 are high electron mobility transistors fabricated under the same manufacturing process. The same manufacturing process is specifically a standard semiconductor processing process with the same processing formula. The same manufacturing process makes the internal structure of the first high electron mobility transistor 1011 and the second high electron mobility transistor 1021 completely identical, and also makes the conduction thresholds of the first high electron mobility transistor 1011 and the second high electron mobility transistor 1021 the same. There is no need to introduce any additional process steps (such as trench etching, plasma implantation, etc.) to adjust the conduction thresholds of the first high electron mobility transistor 1011 and the second high electron mobility transistor 1021, which can greatly improve the uniformity and yield of the semiconductor switching device 10.

[0037] It can be seen that the first high electron mobility transistor 1011 and the second high electron mobility transistor 1021 in the negative voltage driven semiconductor switching device 10 are both compatible with existing process platforms and have the same unit cell structure.

[0038] Optionally, the semiconductor switching device 10 is specifically an integrated chip that integrates multiple high electron mobility transistors. Each high electron mobility transistor on the semiconductor switching device 10 is divided into a forward conduction array 101 and a reverse conduction array 102 based on its own electrical connection method.

[0039] Among them, the high electron mobility transistors on the semiconductor switching device 10 that are controlled by the signal output from the external driving circuit are divided into the forward conduction array 101, and these high electron mobility transistors controlled by the signal output from the external driving circuit are the first high electron mobility transistors 1011; the high electron mobility transistors on the semiconductor switching device 10 that are not controlled by the signal output from the external driving circuit are divided into the reverse conduction array 102, and these high electron mobility transistors not controlled by the signal output from the external driving circuit are the second high electron mobility transistors 1021.

[0040] Specifically, the forward conduction array 101 is used to realize the main function of the semiconductor switching device 10. The forward conduction array 101 is controlled by the external driving circuit and is turned on or off under the control of the driving signal output by the external driving circuit. The reverse conduction array 102 is used to realize the reverse freewheeling function of the semiconductor switching device 10. The reverse conduction array 102 is equivalent to a diode implemented by multiple transistors in parallel. The reverse conduction array 102 is not controlled by the driving signal output by the external driving circuit. The reverse conduction array 102 serves as a self-driven protection structure for the semiconductor switching device 10.

[0041] The gate of each forward-conducting array 101 is connected to the output terminal of the external driving circuit, the gate of each reverse-conducting array 102 is connected to the source of each reverse-conducting array 102, the drain of each forward-conducting array 101 and the drain of each reverse-conducting array 102 are connected to the main power circuit, and the source of each forward-conducting array 101 and the source of each reverse-conducting array 102 are grounded.

[0042] Optionally, most of the high electron mobility transistors on the semiconductor switching device 10 form a forward-conducting array 101. The gates of multiple first high electron mobility transistors 1011 in the forward-conducting array 101 are all connected together to form a common terminal as the external gate terminal of the entire forward-conducting array 101. The sources of multiple first high electron mobility transistors 1011 in the forward-conducting array 101 are all connected together to form a common terminal as the external source terminal of the entire forward-conducting array 101. The drains of multiple first high electron mobility transistors 1011 in the forward-conducting array 101 are all connected together to form a common terminal as the external drain terminal of the entire forward-conducting array 101. Here, the external gate terminal is the gate of the entire forward-conducting array 101, the external source terminal is the source of the entire forward-conducting array 101, and the external drain terminal is the drain of the entire forward-conducting array 101.

[0043] In this circuit, the gate of the forward-conducting array 101 is connected to the output terminal of the external driving circuit, the drain of the forward-conducting array 101 is connected to the main power circuit, and the source of the forward-conducting array 101 is grounded.

[0044] For example, when an external driving circuit applies a forward conduction signal to the gate of the forward conduction array 101, the forward conduction array 101 is turned on under the action of the forward conduction signal, that is, all the first high electron mobility transistors 1011 in the forward conduction array 101 are turned on, and the main power circuit current provided by the flyback converter flows from the drain of the forward conduction array 101 to the source of the forward conduction array 101; conversely, when an external driving circuit applies a negative voltage driving signal to the gate of the forward conduction array 101, the forward conduction array 101 is reliably turned off under the action of the negative voltage driving signal, that is, all the first high electron mobility transistors 1011 in the forward conduction array 101 are turned off, and the main power circuit current provided by the flyback converter is cut off by the forward conduction array 101.

[0045] It should be noted that the external drive circuit is a circuit that provides drive signals to the semiconductor switching device 10. The external drive circuit can provide a positive high-level drive signal to the semiconductor switching device 10, and it can also provide a negative voltage signal to the semiconductor switching device 10.

[0046] Optionally, a small portion of the high electron mobility transistors on the semiconductor switching device 10 form a reverse conduction array 102. That is, all high electron mobility transistors in the reverse conduction array 102 other than the multiple first high electron mobility transistors 1011 are second high electron mobility transistors 1021. The gates of all the multiple second high electron mobility transistors 1021 in the reverse conduction array 102 are connected together to lead out a common terminal as the external gate terminal of the entire reverse conduction array 102. The sources of all the multiple second high electron mobility transistors 1021 in the reverse conduction array 102 are connected together to lead out a common terminal as the external source terminal of the entire reverse conduction array 102. The drains of all the multiple second high electron mobility transistors 1021 in the reverse conduction array 102 are connected together to lead out a common terminal as the external drain terminal of the entire reverse conduction array 102. The external gate terminal is the gate of the entire reverse conduction array 102, the external source terminal is the source of the entire reverse conduction array 102, and the external drain terminal is the drain of the entire reverse conduction array 102.

[0047] Specifically, the gate of the reverse conduction array 102 is connected to the source of the reverse conduction array 102, that is, the gate and source of each second high electron mobility transistor 1021 in the reverse conduction array 102 are shorted together, which makes the gate-source voltage Vgs of the reverse conduction array 102 = 0V. The drain of the reverse conduction array 102 is connected to the main power circuit, and the source of the reverse conduction array 102 is grounded. Since the gate-source voltage Vgs of the reverse conduction array 102 is 0V, the reverse conduction array 102 will never be controlled by the drive signal output by the external drive circuit. However, when the main power circuit needs reverse freewheeling, that is, when the main power circuit needs current to flow from the source to the drain of the semiconductor switching device 10, the reverse voltage between the source and drain of the reverse conduction array 102 exceeds the conduction threshold of the second high electron mobility transistor 1021 in the reverse conduction array 102. Then, each of the second high electron mobility transistors 1021 in the reverse conduction array 102 is turned on, providing a low-loss reverse current path for the semiconductor switching device 10.

[0048] In this embodiment, a semiconductor switching device is formed by deploying multiple high electron mobility transistors with the same structure and parameters on the same semiconductor substrate. The electrical connection relationship of the high electron mobility transistors divides most of the first high electron mobility transistors into a forward conducting array and a small portion of the second high electron mobility transistors into a reverse conducting array. In the forward-conducting array, the gates of multiple first high electron mobility transistors are connected together to form the gate of the forward-conducting array. The sources of multiple first high electron mobility transistors in the forward-conducting array are connected together to form the source of the forward-conducting array. The drains of multiple first high electron mobility transistors in the forward-conducting array are connected together to form the source of the forward-conducting array. The gate of the forward-conducting array is connected to the output terminal of the external driving circuit. In the reverse-conducting array, the gates of multiple second high electron mobility transistors are connected together to form the gate of the reverse-conducting array. The sources of multiple second high electron mobility transistors in the reverse-conducting array are connected together to form the source of the reverse-conducting array. The drains of multiple second high electron mobility transistors in the reverse-conducting array are connected together to form the source of the reverse-conducting array. The gate and source of the reverse-conducting array are shorted. The drains of both the forward-conducting and reverse-conducting arrays are connected to the main power circuit. The sources of both the forward-conducting and reverse-conducting arrays are grounded. Furthermore, when the external drive circuit outputs a positive voltage drive signal, the forward conduction array is turned on, and the reverse conduction array is turned off. The main power circuit current flows from the drain of the forward conduction array to the source through the primary winding of the transformer. When the external drive circuit outputs a negative voltage drive signal, the forward conduction array is turned off until the reverse voltage between the source and drain of the reverse conduction array reaches the conduction threshold of the reverse conduction array. At this point, the reverse conduction array turns on, providing a low-loss reverse freewheeling path for the semiconductor switching device. Therefore, the reverse conduction of the semiconductor switching device is unaffected by the gate voltage and can provide a low-loss reverse freewheeling path even under a negative voltage signal. This resolves the contradiction between improving the anti-interference capability and reducing the reverse freewheeling loss of gallium nitride semiconductor switching devices.

[0049] In one optional embodiment, the gate of each first high electron mobility transistor 1011 in each forward conduction array 101 of the semiconductor switching device 10 provided in this application is connected to the output terminal of an external driving circuit, the drain of each first high electron mobility transistor 1011 in each forward conduction array 101 is connected to the main power circuit, and the source of each first high electron mobility transistor 1011 in each forward conduction array 101 is grounded. When the external driving circuit outputs a high level to the gate of each first high electron mobility transistor 1011 in each forward-conducting array 101, each first high electron mobility transistor 1011 is turned on under the action of the high level. Conversely, when the external driving circuit outputs a negative voltage signal to the gate of each first high electron mobility transistor 1011 in each forward-conducting array 101, each first high electron mobility transistor 1011 is turned off under the action of the high level.

[0050] Optionally, the external driving circuit includes two driving circuits: one is a positive power supply driving circuit, and the other is a negative power supply driving circuit. The external driving circuit outputs a positive high-level signal to the forward-conducting array 101 via the positive power supply driving circuit, and outputs a negative voltage signal to the forward-conducting array 101 via the negative power supply driving circuit.

[0051] In one optional embodiment, in the semiconductor switching device 10 provided in this application, the gate of each second high electron mobility transistor 1021 in each reverse conduction array 102 is connected to the source of each second high electron mobility transistor 1021 in each reverse conduction array 102, the drain of each second high electron mobility transistor 1021 in each reverse conduction array 102 is connected to the main power circuit, and the source of each second high electron mobility transistor 1021 in each reverse conduction array 102 is grounded; When the external driving circuit outputs a negative voltage signal to the gate of the forward conduction array 101, a reverse voltage is formed between the source and drain of each second high electron mobility transistor 1021 in each reverse conduction array 102. When the reverse voltage is greater than the conduction voltage threshold of each second high electron mobility transistor 1021, each second high electron mobility transistor 1021 is turned on, providing a reverse freewheeling path for the semiconductor switching device 10.

[0052] For example, when the external driving circuit applies a positive high level to the gate of the forward-conducting array 101, all the first high electron mobility transistors 1011 in the forward-conducting array 101 are turned on. The main power circuit current provided by the flyback converter flows from the primary winding of the transformer into the drain of the forward-conducting array 101 and from the drain of the forward-conducting array 101 to the source of the forward-conducting array 101 to the ground. At this time, since all the second high electron mobility transistors 1021 inside the reverse-conducting array 102 are short-circuited, the gate-source voltage Vgs of the reverse-conducting array 102 is 0V. All the second high electron mobility transistors 1021 in the reverse-conducting array 102 are turned off. The reverse-conducting array 102 does not participate in the operation of the semiconductor switching device 10 and does not affect the main power circuit.

[0053] Optionally, when an external driving circuit applies a negative voltage signal to the gate of the forward-conducting array 101, all the first high electron mobility transistors 1011 in the forward-conducting array 101 are reliably turned off, which can effectively prevent the forward-conducting array 101 from being accidentally turned on. At this time, if the main power circuit needs reverse freewheeling, that is, when the semiconductor switching device 10 is in the dead time, the main power circuit current attempts to flow from the source to the drain of the semiconductor switching device 10. When the reverse voltage between the source and drain of the reverse-conducting array 102 reaches the conduction threshold of the second high electron mobility transistor 1021 in the reverse-conducting array 102, the reverse-conducting array 102 is turned on with low loss, effectively clamping the reverse voltage within a safe voltage range determined by the conduction voltage threshold of the reverse-conducting array 102, so as to provide reverse freewheeling for the main power circuit, thereby protecting the semiconductor switching device 10.

[0054] The on-voltage threshold is determined by the physical structure of the second high electron mobility transistor 1021, and can also be regarded as the turn-on voltage threshold of the second high electron mobility transistor 1021. The reverse voltage refers to the voltage generated when the potential of the source of the reverse conduction array 102 is higher than the potential of the drain. The reverse voltage occurs during the freewheeling phase or dead time. At this time, due to the effect of energy storage elements such as inductors, the main power circuit current needs to be maintained. The main power circuit current changes from flowing from the drain to the source to flowing from the source to the drain, and a reverse voltage is generated between the source and drain of the reverse conduction array 102.

[0055] In one alternative implementation, see [link to implementation details]. Figure 2 In the semiconductor switching device 10 provided in this application embodiment, each forward conduction array 101 and each reverse conduction array 102 are arranged side by side on the same semiconductor substrate.

[0056] Optionally, the parallel arrangement refers to the forward-conducting array and the reverse-conducting array being arranged in multiple parallel columns on the same semiconductor substrate.

[0057] In one optional implementation, the drain of each forward-conducting array in the semiconductor switching device 10 provided in this application is connected to the drain of each reverse-conducting array, and the total channel width occupied by each forward-conducting array is greater than the total channel width occupied by each reverse-conducting array.

[0058] Optionally, when the forward conduction array 101 and the reverse conduction array 102 are arranged side by side in the chip layout design of the semiconductor switching device 10, the forward conduction array 101 and the adjacent reverse conduction array 102 share the drain.

[0059] Optionally, the total channel width occupied by the forward conducting array 101 refers to the sum of the channel widths of each of the first high electron mobility transistors 1011 in the forward conducting array 101, and the total channel width occupied by the reverse conducting array 102 refers to the sum of the channel widths of each of the second high electron mobility transistors 1021 in the reverse conducting array 102. Since the forward conducting array 101 needs to bear the main conduction losses of the semiconductor switching device 10, it needs to have a high conduction impedance. Since channel width is inversely proportional to conduction impedance (i.e., the larger the channel width, the smaller the impedance), the total channel width occupied by the forward conducting array 101 is greater than the total channel width occupied by the reverse conducting array 102.

[0060] In one alternative implementation, see [link to implementation details]. Figure 3 In the semiconductor switching device 10 provided in this application embodiment, each forward conduction array and each reverse conduction array are alternately distributed on the same semiconductor substrate.

[0061] Alternatively, alternating distribution refers to a checkerboard pattern in which the forward-conducting array and the reverse-conducting array are staggered on the same semiconductor substrate.

[0062] In one alternative implementation, see [link to implementation details]. Figure 4 In the semiconductor switching device 10 provided in this application embodiment, each forward conduction array is deployed in a first region on a semiconductor substrate, and each reverse conduction array is deployed in a second region on a semiconductor substrate, with a transition isolation region provided between the first region and the second region.

[0063] Optionally, a transition isolation region is used to isolate adjacent forward-conducting arrays and reverse-conducting arrays. The first region refers to the distribution area of ​​the forward-conducting array 101 on the semiconductor substrate of the semiconductor switching device 10, and the second region refers to the distribution area of ​​the reverse-conducting array 102 on the semiconductor substrate of the semiconductor switching device. When the forward-conducting array 101 and the reverse-conducting array 102 are alternately distributed in the chip layout design of the semiconductor switching device 10, a transition isolation region is provided between the first region where the forward-conducting array 101 is located and the second region where the adjacent reverse-conducting array 102 is located. In this way, the current sharing and thermal stability of the semiconductor switching device 10 can be improved.

[0064] In one optional embodiment, the first area occupied by the first region on the semiconductor substrate and the second area occupied by the second region on the semiconductor substrate in the semiconductor switching device 10 provided in this application embodiment satisfy a preset ratio.

[0065] Optionally, the first area refers to the area of ​​the semiconductor substrate of the semiconductor switching device 10 occupied by the forward conducting array 101, and the second area refers to the area of ​​the semiconductor substrate of the semiconductor switching device 10 occupied by the reverse conducting array 102.

[0066] Optionally, the preset ratio is the area ratio of the forward conducting array 101 and the reverse conducting array 102 set by the user according to the application scenario of the semiconductor switching device 10. Based on the preset ratio, it can be ensured that the forward conducting array 101 has a sufficiently large conduction capability, while limiting the reverse conducting array 102 to have a certain reverse current carrying capacity, thereby balancing the relationship between anti-interference capability and current carrying loss. The preset ratio can be 3:2, 5:2, 3:1, etc., which is determined by the actual application scenario of the semiconductor switching device 10, and this application does not make a specific limitation on it.

[0067] It should be noted that the forward conduction array 101 has a significant impact on the performance of the semiconductor switching device 10. Therefore, the first area occupied by the first region where the forward conduction array 101 is located is larger than the second area occupied by the second region where the reverse conduction array 102 is located, in order to ensure that the mainstream conduction performance of the semiconductor switching device 10 is optimal.

[0068] In one optional embodiment, the semiconductor switching device 10 provided in this application includes a semiconductor substrate, a buffer layer, and a gallium nitride channel, wherein the buffer layer is generally located on the substrate and the gallium nitride channel is generally located on the buffer layer.

[0069] Optionally, the substrate is mainly used to provide mechanical support for the semiconductor switching device 10 and to provide heat dissipation for the semiconductor switching device 10. The substrate is often made of silicon. The buffer layer is usually placed on the substrate. The buffer layer is specifically a transition layer between the substrate and the gallium nitride channel. The buffer layer is often made of materials such as aluminum nitride and aluminum gallium nitride. The buffer layer is mainly used to absorb and block the stress transmitted from the substrate, prevent defects from extending upward, and prevent the current flowing through the upper gallium nitride channel from leaking to the substrate. At the same time, it also provides a suitable seed layer for the upper gallium nitride channel. The gallium nitride channel is used to generate a two-dimensional electron gas and provide excellent switching performance for the semiconductor switching device 10.

[0070] Optionally, a barrier layer can be further grown on the gallium nitride channel to form a two-dimensional electron gas channel with high mobility at the interface.

[0071] In one alternative implementation, see [link to implementation details]. Figure 5 This application provides a flyback switching power supply 20 including: a driving circuit 201, a flyback converter 202, and the aforementioned negative voltage driven semiconductor switching device 10. The driving circuit includes: a positive power supply driving circuit 2011 and a negative power supply driving circuit 2012. The semiconductor switching device 10 includes: at least one forward conduction array 101 and at least one reverse conduction array 102. The flyback converter 202 includes: a transformer 2021. The output terminals of the positive power supply drive circuit 2011 and the negative power supply drive circuit 2012 are both connected to the control terminals of each forward conduction array 101. The drains of each forward conduction array 101 and each reverse conduction array 102 are both connected to one end of the primary winding of the transformer 2021 in the flyback converter 202. The gates of each reverse conduction array 102 are connected to the sources of each reverse conduction array 102. The other end of the primary winding of the transformer 2021 is connected to the input voltage. The sources of each forward conduction array 101 and each reverse conduction array 102 are both grounded. The two ends of the secondary winding of the transformer 2021 in the flyback converter 202 are connected to the external load.

[0072] Specifically, when each forward conduction array 101 is turned on under the action of the high level output by the positive power supply drive circuit 2011, each reverse conduction array 102 is turned off. At the same time, the transformer 2021 in the flyback converter 202 is charged under the action of the input voltage. When each forward conduction array 101 is turned off under the action of the negative voltage signal output by the negative power supply drive circuit 2012, and the reverse voltage between the source and drain of each reverse conduction array 102 reaches the conduction voltage threshold of each reverse conduction array 102, each reverse conduction array 102 is turned on, and the transformer 2021 in the flyback converter 202 is discharged under the action of the input voltage.

[0073] Furthermore, the aforementioned driving circuit 201 also includes a controller and resistors. The positive power supply driving circuit 2011 includes a positive voltage power supply, an inverter, and a P-type metal-oxide-semiconductor transistor (MOSFET). The negative power supply driving circuit 2012 includes a negative voltage power supply, an inverter, and an N-type MOSFET. The input terminals of the inverters in both the positive and negative power supply driving circuits 2011 and 2012 are connected to the controller. The output terminal of the inverter in the positive power supply driving circuit 2011 is connected to the source of the P-type MOSFET, and the output terminal of the inverter in the negative power supply driving circuit 2012 is connected to the gate of the N-type MOSFET. The output terminal of the positive voltage power supply is connected to the source of the P-type MOSFET, and the drain of the P-type MOSFET is connected to the gate of each forward-conducting array via a resistor. The output terminal of the negative voltage power supply is connected to the source of the N-type MOSFET, and the drain of the N-type MOSFET is connected to the gate of each forward-conducting array via a resistor.

[0074] In addition, the flyback switching power supply 20 provided in this application embodiment further includes: a spike absorption circuit 203 and a rectifier filter circuit 204. The rectifier filter circuit 204 includes: a rectifier diode and a capacitor. The input terminal of the spike absorption circuit 203 is connected to the other end of the primary winding of the transformer 2021 in the flyback converter 202, and the output terminal of the spike absorption circuit 203 is connected to one end of the primary winding of the transformer 2021 in the flyback converter 202. The input terminal of the rectifier diode in the rectifier filter circuit 204 is connected to one end of the secondary winding of the transformer 2021 in the flyback converter 202, and the output terminal of the rectifier diode is connected to one end of the capacitor and an external load, respectively. The other end of the secondary winding of the transformer 2021 in the flyback converter 202 is connected to the other end of the capacitor and an external load, respectively.

[0075] Figure 6 This is a schematic diagram of a conventional negative-voltage driven flyback switching power supply circuit. (See attached diagram.) Figure 6 In existing flyback switching power supply circuits, the reverse conduction voltage of the semiconductor switching device depends on the gate voltage and the turn-on voltage threshold of the semiconductor switching device. When the semiconductor switching device is reverse-conducting under negative voltage drive, it needs to reach a large reverse voltage for the channel of the semiconductor switching device to be forcibly opened and freewheeling current can be generated. This means that the semiconductor switching device itself will experience a very high reverse voltage drop each time freewheeling current is generated, which will generate a large freewheeling power and thus restrict the operating efficiency of the power supply system.

[0076] In one alternative implementation, see [link to implementation details]. Figure 7 Compared with existing flyback switching power supplies, the semiconductor switching device disclosed in this application requires a smaller reverse voltage, withstands a smaller reverse voltage drop, and has a smaller reverse freewheeling loss when achieving negative voltage turn-off under the same negative voltage drive mode.

[0077] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0078] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A negative voltage driven semiconductor switching device, characterized in that, The semiconductor switching device includes at least one forward conducting array and at least one reverse conducting array, wherein each of the forward conducting arrays and each of the reverse conducting arrays are deployed on the same semiconductor substrate; Each of the forward conduction arrays includes a plurality of first high electron mobility transistors, and each of the reverse conduction arrays includes a plurality of second high electron mobility transistors. The first high electron mobility transistors and the second high electron mobility transistors have the same structure and process parameters. The gate of each of the forward-conducting arrays is connected to the output terminal of the external driving circuit, the gate of each of the reverse-conducting arrays is connected to the source of each of the reverse-conducting arrays, the drain of each of the forward-conducting arrays and the drain of each of the reverse-conducting arrays are connected to the main power circuit, and the source of each of the forward-conducting arrays and the source of each of the reverse-conducting arrays are grounded.

2. The negative voltage driven semiconductor switching device according to claim 1, characterized in that, Each of the forward conducting arrays and each of the reverse conducting arrays are arranged side by side on the same semiconductor substrate.

3. The negative voltage driven semiconductor switching device according to claim 2, characterized in that, The drain of each of the forward conducting arrays is connected to the drain of each of the reverse conducting arrays, and the total channel width occupied by each of the forward conducting arrays is greater than the total channel width occupied by each of the reverse conducting arrays.

4. The negative voltage driven semiconductor switching device according to claim 1, characterized in that, Each of the forward conducting arrays and each of the reverse conducting arrays are alternately distributed on the same semiconductor substrate.

5. The negative voltage driven semiconductor switching device according to claim 4, characterized in that, Each of the forward conducting arrays is deployed in a first region on the semiconductor substrate, and each of the reverse conducting arrays is deployed in a second region on the semiconductor substrate, with a transition isolation region provided between the first region and the second region.

6. The negative voltage driven semiconductor switching device according to claim 5, characterized in that, The first area occupied by the first region on the semiconductor substrate and the second area occupied by the second region on the semiconductor substrate satisfy a preset ratio.

7. The negative voltage driven semiconductor switching device according to claim 1, characterized in that, The same semiconductor substrate includes: a substrate, a buffer layer, and a gallium nitride channel, wherein the buffer layer is generally located on the substrate, and the gallium nitride channel is generally located on the buffer layer.

8. The negative voltage driven semiconductor switching device according to claim 1, characterized in that, The gate of each of the first high electron mobility transistors in each of the forward conduction arrays is connected to the output terminal of the external driving circuit, the drain of each of the first high electron mobility transistors in each of the forward conduction arrays is connected to the main power circuit, and the source of each of the first high electron mobility transistors in each of the forward conduction arrays is grounded. When the external driving circuit outputs a high level to the gate of each of the first high electron mobility transistors in each of the forward-conducting arrays, each of the first high electron mobility transistors is turned on under the action of the high level. Conversely, when the external driving circuit outputs a negative voltage signal to the gate of each of the first high electron mobility transistors in each of the forward-conducting arrays, each of the first high electron mobility transistors is turned off under the action of the high level.

9. The negative voltage driven semiconductor switching device according to claim 1, characterized in that, The gate of each of the second high electron mobility transistors in each of the reverse conduction arrays is connected to the source of each of the second high electron mobility transistors in each of the reverse conduction arrays, the drain of each of the second high electron mobility transistors in each of the reverse conduction arrays is connected to the main power circuit, and the source of each of the second high electron mobility transistors in each of the reverse conduction arrays is grounded. When the external driving circuit outputs a negative voltage signal to the gate of the forward-conducting array, a reverse voltage is formed between the source and drain of each second high electron mobility transistor in each of the reverse-conducting arrays. When the reverse voltage is greater than the conduction voltage threshold of each second high electron mobility transistor, each second high electron mobility transistor is turned on, providing a reverse freewheeling path for the semiconductor switching device.

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