A high-precision phase-locked clock circuit

Abstract

The utility model discloses a kind of high-precision phase-locked clock circuit, the high-precision phase-locked clock circuit is passed through capacitor C1 and is inputted to isolation, then after entering frequency multiplier U1 by the filter shaping circuit of resistance R1, resistance R2, resistance R3 and capacitor C2, capacitor C3, it is set to 4 times frequency output by frequency multiplier U1, and the required frequency is obtained by band-pass filter U2.Frequency multiplication number of matching frequency multiplier U3 realizes the frequency required by user.Resistance R6 and resistance R7 provide enough driving current and are outputted to isolation by capacitor C6.The high-precision phase-locked clock circuit solves clock long-distance transmission, system clock is not synchronized, the amplitude of pulse is low, cannot satisfy system and system clock synchronization precision and high-frequency long-distance transmission anti-interference problem.Frequency reduction transmission guarantees the clock of each system is unified and can satisfy system demand.Simple circuit design can prolong service life, reduce failure.EMC / EMI design guarantees normal and stable work in complex electromagnetic environment.

Description

Technical Field

[0001] This utility model relates to the field of signal processing, specifically to a high-precision phase-locked clock circuit. Background Technology

[0002] The clock system consists of a master control device that sends standard clock signals to each system and slave clock, detects the working status of slave clocks, and provides a standard unified clock signal to slave clocks within the system and computers on the local area network to achieve time synchronization of the entire system.

[0003] Phase-locked loops (PLLs) are widely used in clock system design, including applications such as phase synchronization and clock multiplication. Typically, when a chip's operating frequency exceeds a certain range, it's necessary to eliminate the phase difference between the on-chip and off-chip clocks caused by the chip's internal clock drive. An internal PLL can eliminate this clock delay. Furthermore, many chip control chain logics require a 50% duty cycle clock, thus necessitating a clock source twice that frequency. An internal PLL can synthesize this clock source from an external clock.

[0004] However, when the clock is transmitted over long distances or the system clock is out of sync or the pulse amplitude is low, it will affect the system. Therefore, it is necessary to balance the clock synchronization accuracy and the anti-interference of high-frequency long-distance transmission. However, the existing technology cannot balance the cost and electromagnetic compatibility of clock synchronization accuracy and high-frequency long-distance transmission anti-interference. Utility Model Content

[0005] In view of the above-mentioned shortcomings in the prior art, the high-precision phase-locked clock circuit provided by this utility model solves the problem that the existing solutions that take into account both clock synchronization accuracy and high-frequency long-distance transmission anti-interference are difficult to balance cost and electromagnetic compatibility.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0007] A high-precision phase-locked clock circuit is provided, comprising a frequency multiplier U1, a bandpass filter U2, and a frequency multiplier U3. The input terminal of the frequency multiplier U1 is connected to one end of resistor R2 and one end of resistor R3 via capacitor C2. The other end of resistor R2 is connected to one end of capacitor C1 and one end of resistor R1. The other end of capacitor C1 is the input terminal of a high-amplitude drive circuit. The other end of resistor R3 is connected to one end of capacitor C3. The other end of capacitor C3, the other end of resistor R1, the negative terminal of frequency multiplier U1, the negative terminal of bandpass filter U2, and the negative terminal of frequency multiplier U3 are connected and grounded.

[0008] The output of frequency multiplier U1 is connected to the input of bandpass filter U2 through capacitor C4; the positive terminal of frequency multiplier U1 is connected to the positive terminal of bandpass filter U2 and connected to an external first power supply; the output of bandpass filter U2 is connected to the input of frequency multiplier U3 through capacitor C5.

[0009] The output terminal of frequency multiplier U3 is connected to one end of capacitor C6, one end of resistor R6, and one end of resistor R7 respectively; the other end of capacitor C6 is the output terminal of the high amplitude drive circuit; the positive terminal of frequency multiplier U3, the other end of resistor R6, and the other end of resistor R7 are connected to an external second power supply.

[0010] Furthermore, the external first power supply includes transformer chip U4. The VIN pin of transformer chip U4 is connected to grounding capacitor C7, grounding capacitor C8, the EN pin of transformer chip U4, and 5V voltage, respectively. The SS pin of transformer chip U4 is connected to grounding capacitor C9. The EP pin of transformer chip U4 is grounded. The GND pin of transformer chip U4 is grounded. The FB pin of transformer chip U4 is connected to one end of resistor R8, one end of resistor R10, and one end of resistor R11, respectively. The other end of resistor R8 is connected to the grounding resistor. The VOUT pin of transformer chip U4 is connected to the other end of resistor R10, one end of capacitor C10, grounding capacitors C11, C12, C13, C14, C15, C16, and C17, respectively, and serves as the output terminal of the external first power supply. The other end of resistor R11 is connected to the other end of capacitor C10.

[0011] Furthermore, the external second power supply includes transformer chip U5; the IN pin of transformer chip U5 is connected to the EN pin, BIAS pin, grounding capacitor C19, grounding capacitor C18 and 5V voltage respectively; the SS pin of transformer chip U5 is connected to grounding capacitor C20; the GND pin of transformer chip U5 is grounded; the FB pin of transformer chip U5 is connected to one end of resistor R12 and one end of resistor R14 respectively; the other end of resistor R14 is connected to grounding resistor R15; the PG pin of transformer chip U5 is connected to 5V voltage through resistor R13; the OUT pin of transformer chip U5 is connected to the other end of resistor R12, grounding capacitors C21, C22, C23, C24, C25, C26 and C27 respectively and serves as the output terminal of the external second power supply.

[0012] The beneficial effects of this invention are as follows: This high-precision phase-locked clock circuit inputs a pulse signal through capacitor C1 (DC blocking), then through a filtering and shaping circuit composed of resistors R1, R2, R3, and capacitors C2 and C3 before entering frequency multiplier U1. Frequency multiplier U1 is set to output at 4x frequency, and the desired frequency is obtained through bandpass filter U2. The frequency multiplication factor of frequency multiplier U3 is matched to achieve the frequency required by the user. Resistors R6 and R7 provide sufficient drive current, which is output through DC blocking by capacitor C6. This high-precision phase-locked clock circuit solves the problems of long-distance clock transmission, system clock asynchrony, low pulse amplitude, inability to meet the clock synchronization accuracy between systems, and high-frequency long-distance transmission anti-interference issues. Frequency reduction transmission ensures clock uniformity across systems, meeting system requirements. The simplified circuit design extends service life and reduces failures. EMC / EMI design ensures normal and stable operation in complex electromagnetic environments. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of a high-precision phase-locked clock circuit.

[0014] Figure 2 Circuit diagram of the external first power supply;

[0015] Figure 3 This is a circuit diagram for an external second power supply. Detailed Implementation

[0016] The specific embodiments of this utility model are described below to enable those skilled in the art to understand this utility model. However, it should be understood that this utility model is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of this utility model as defined and determined by the appended claims, these changes are obvious. All inventions utilizing the concept of this utility model are protected.

[0017] like Figure 1 As shown, the high-precision phase-locked clock circuit includes a frequency multiplier U1, a bandpass filter U2, and a frequency multiplier U3. The input terminal of the frequency multiplier U1 is connected to one end of resistor R2 and one end of resistor R3 through capacitor C2. The other end of resistor R2 is connected to one end of capacitor C1 and one end of resistor R1. The other end of capacitor C1 is the input terminal of the high-amplitude drive circuit. The other end of resistor R3 is connected to one end of capacitor C3. The other end of capacitor C3, the other end of resistor R1, the negative terminal of frequency multiplier U1, the negative terminal of bandpass filter U2, and the negative terminal of frequency multiplier U3 are connected and grounded.

[0018] The output of frequency multiplier U1 is connected to the input of bandpass filter U2 through capacitor C4; the positive terminal of frequency multiplier U1 is connected to the positive terminal of bandpass filter U2 and connected to an external first power supply; the output of bandpass filter U2 is connected to the input of frequency multiplier U3 through capacitor C5.

[0019] The output terminal of frequency multiplier U3 is connected to one end of capacitor C6, one end of resistor R6, and one end of resistor R7 respectively; the other end of capacitor C6 is the output terminal of the high amplitude drive circuit; the positive terminal of frequency multiplier U3, the other end of resistor R6, and the other end of resistor R7 are connected to an external second power supply.

[0020] like Figure 2 As shown, the external first power supply includes transformer chip U4. The VIN pin of transformer chip U4 is connected to grounding capacitor C7, grounding capacitor C8, the EN pin of transformer chip U4, and 5V voltage, respectively. The SS pin of transformer chip U4 is connected to grounding capacitor C9. The EP pin of transformer chip U4 is grounded. The GND pin of transformer chip U4 is grounded. The FB pin of transformer chip U4 is connected to one end of resistor R8, one end of resistor R10, and one end of resistor R11, respectively. The other end of resistor R8 is connected to the grounding resistor. The VOUT pin of transformer chip U4 is connected to the other end of resistor R10, one end of capacitor C10, grounding capacitors C11, C12, C13, C14, C15, C16, and C17, respectively, and serves as the output terminal of the external first power supply. The other end of resistor R11 is connected to the other end of capacitor C10.

[0021] like Figure 3 As shown, the external second power supply includes transformer chip U5; the IN pin of transformer chip U5 is connected to the EN pin, BIAS pin, grounding capacitor C19, grounding capacitor C18 and 5V voltage respectively; the SS pin of transformer chip U5 is connected to grounding capacitor C20; the GND pin of transformer chip U5 is grounded; the FB pin of transformer chip U5 is connected to one end of resistor R12 and one end of resistor R14 respectively; the other end of resistor R14 is connected to grounding resistor R15; the PG pin of transformer chip U5 is connected to 5V voltage through resistor R13; the OUT pin of transformer chip U5 is connected to the other end of resistor R12, grounding capacitors C21, C22, C23, C24, C25, C26 and C27 respectively and serves as the output terminal of the external second power supply.

[0022] The high-precision phase-locked clock circuit inputs a pulse signal through capacitor C1 (DC blocking), then passes it through a filtering and shaping circuit composed of resistors R1, R2, R3, and capacitors C2 and C3 before entering frequency multiplier U1. Frequency multiplier U1 is set to output a 4x frequency, which is then passed through bandpass filter U2 to obtain the desired frequency. The multiplication factor of frequency multiplier U3 is matched to achieve the user-required frequency. Resistors R6 and R7 provide sufficient drive current, which is then DC blocked by capacitor C6.

[0023] In a specific embodiment, this high-precision phase-locked clock circuit has the following characteristics:

[0024] Wide output frequency range, with frequencies ranging from 1GHz to 20GHz;

[0025] The output frequency is stable, with a temperature range of ±0.001GHz;

[0026] Low impulse response, 10-50mV;

[0027] Multi-pulse mode adaptation;

[0028] Low in-band oscillation;

[0029] Typical high synchronization accuracy is 8 ps;

[0030] Strict EMC / EMI design.

[0031] This high-precision phase-locked clock circuit can be used as a clock source for phase modulators, precision synchronization systems, and arbitrary waveform generators.

[0032] In conclusion, this high-precision phase-locked clock circuit solves the problems of long-distance clock transmission, system clock asynchrony, low pulse amplitude, and inability to meet the clock synchronization accuracy requirements between systems and the anti-interference issues of high-frequency long-distance transmission. Frequency reduction transmission ensures clock uniformity across all systems, meeting system requirements. The simplified circuit design extends service life and reduces failures. EMC / EMI design guarantees normal and stable operation in complex electromagnetic environments.

Claims

1. A high-precision phase-locked clock circuit, characterized in that, It includes a frequency multiplier U1, a bandpass filter U2, and a frequency multiplier U3; the input terminal of the frequency multiplier U1 is connected to one end of resistor R2 and one end of resistor R3 through capacitor C2; the other end of resistor R2 is connected to one end of capacitor C1 and one end of resistor R1; the other end of capacitor C1 is the input terminal of the high-amplitude drive circuit; the other end of resistor R3 is connected to one end of capacitor C3; the other end of capacitor C3, the other end of resistor R1, the negative terminal of frequency multiplier U1, the negative terminal of bandpass filter U2, and the negative terminal of frequency multiplier U3 are connected and grounded; The output of frequency multiplier U1 is connected to the input of bandpass filter U2 through capacitor C4; the positive terminal of frequency multiplier U1 is connected to the positive terminal of bandpass filter U2 and connected to an external first power supply; the output of bandpass filter U2 is connected to the input of frequency multiplier U3 through capacitor C5. The output terminal of frequency multiplier U3 is connected to one end of capacitor C6, one end of resistor R6, and one end of resistor R7 respectively; the other end of capacitor C6 is the output terminal of the high amplitude drive circuit; the positive terminal of frequency multiplier U3, the other end of resistor R6, and the other end of resistor R7 are connected to an external second power supply.

2. The high-precision phase-locked clock circuit according to claim 1, characterized in that, The external first power supply includes transformer chip U4. The VIN pin of transformer chip U4 is connected to grounding capacitor C7, grounding capacitor C8, the EN pin of transformer chip U4, and 5V voltage, respectively. The SS pin of transformer chip U4 is connected to grounding capacitor C9. The EP pin of transformer chip U4 is grounded. The GND pin of transformer chip U4 is grounded. The FB pin of transformer chip U4 is connected to one end of resistor R8, one end of resistor R10, and one end of resistor R11, respectively. The other end of resistor R8 is connected to the grounding resistor. The VOUT pin of transformer chip U4 is connected to the other end of resistor R10, one end of capacitor C10, grounding capacitors C11, C12, C13, C14, C15, C16, and C17, respectively, and serves as the output terminal of the external first power supply. The other end of resistor R11 is connected to the other end of capacitor C10.

3. The high-precision phase-locked clock circuit according to claim 1, characterized in that, The external second power supply includes transformer chip U5; the IN pin of transformer chip U5 is connected to the EN pin, BIAS pin, ground capacitor C19, ground capacitor C18 and 5V voltage respectively; the SS pin of transformer chip U5 is connected to ground capacitor C20; the GND pin of transformer chip U5 is grounded; the FB pin of transformer chip U5 is connected to one end of resistor R12 and one end of resistor R14 respectively; the other end of resistor R14 is connected to ground resistor R15; the PG pin of transformer chip U5 is connected to 5V voltage through resistor R13; the OUT pin of transformer chip U5 is connected to the other end of resistor R12, ground capacitors C21, C22, C23, C24, C25, C26 and C27 respectively and serves as the output terminal of the external second power supply.

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