An RFID data collection device integrating WiFi 5G
Patent Information
- Application Number
- CN202522289468.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-29
- Publication Date
- 2026-09-29
- Estimated Expiration
- 2035-10-29
AI Technical Summary
[0003]用户通过RFID设备识别畜生的身份从而获取畜生信息时，为了将RFID设备读取到的相关信息发送到手机或者电脑或者其他电子设备上，通过WiFi模块无线传输实现信息的共享，但信号在传输过程中，如果信号线的阻抗与信号源或接收端的阻抗不匹配，会导致信号反射，产生过冲或振铃现象，导致信号质量的恶化
[0012]本实用新型的有益效果在于：在WiFi芯片U7与主芯片U1之间串联第一电阻，通过第一电阻实现阻抗匹配、优化信号完整性，并提供基础限流保护，实现传输线阻抗匹配，减少高速信号传输中的反射、过冲和电磁干扰，改善高频信号完整性，同时辅助限制异常电流以保护接口电路，避免信号质量的恶化。
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Figure CN224818239U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of livestock RFID identification, and more specifically, to an RFID data collection device integrating WiFi 5G. Background Technology
[0002] To facilitate easier identification of livestock and enable more precise breeding practices, livestock farmers are introducing and applying RFID technology to livestock management. During the breeding process, RFID technology assigns each animal a unique identification number, facilitating the management of all information related to livestock breeding and thus improving the level of intelligence in livestock farming.
[0003] When users identify livestock using RFID devices to obtain livestock information, they can wirelessly transmit the information read by the RFID device to their mobile phones, computers, or other electronic devices via WiFi modules to achieve information sharing. However, if the impedance of the signal line does not match the impedance of the signal source or receiver during signal transmission, it can cause signal reflection, overshoot, or ringing, leading to a deterioration in signal quality. Utility Model Content
[0004] To address the aforementioned shortcomings of existing technologies, an RFID data collection device integrating WiFi 5G is provided.
[0005] The technical solution adopted by this utility model to solve its technical problem is as follows: an RFID acquisition device integrating WiFi 5G, including a device body, an extension rod provided on the device body, a reading antenna provided on the extension rod, a circuit board provided inside the device body, and the acquisition device further including a WiFi 5G circuit located on the circuit board. The WiFi 5G circuit includes a main chip U1, the main chip U1 is connected to a power control circuit, the power control circuit is connected to a WiFi chip U7, the WiFi chip U7 is grounded, and the WiFi chip U7 is grounded and connected to an RF signal receiving circuit and a power wake-up circuit. The pins SDIO_DATA_2, SDIO_DATA_3, SDIO_DATA_CMD, SDIO_DATA_CLK, SDIO_DATA_D0, and SDIO_DATA_D1 of the WiFi chip U7 are all connected to first resistors for impedance matching and signal current limiting, and multiple first resistors are all connected to the main chip U1.
[0006] Preferably, the first resistor connected to the SDIO_DATA_CLK pin of the WiFi chip U7 is also connected in parallel with a capacitor C39, and the capacitor C39 is grounded.
[0007] Preferably, the power wake-up circuit includes two OR second resistors, and the WL_REG_ON and WL_HOST_WAKE pins of the WiFi chip U7 are respectively connected to the two second resistors, and the two second resistors are connected to the main chip U1.
[0008] Preferably, the WiFi chip U7's pins WL_REG_ON and WL_HOST_WAKE are also connected to two third resistors, which are connected to the power supply VCC_3.3V.
[0009] Preferably, the radio frequency signal receiving circuit includes a fourth resistor connected to the RF pin of the WiFi chip U7. The fourth resistor is connected to capacitors C20 and C10. Capacitor C20 is grounded. Capacitor C10 is connected to capacitor C23, diode D5, and antenna interface ANT1. Capacitor C23 and diode D5 are both grounded. Antenna interface ANT1 is connected to a fifth resistor, which is grounded.
[0010] Preferably, the power control circuit includes a MOSFET Q2, the drain of which is connected to the WiFi chip U7, the gate of which is connected to a sixth resistor and connected to the power supply VCC_3.3V, and both the sixth resistor and the source of the MOSFET Q2 are connected to the main chip U1.
[0011] Preferably, the WiFi chip U7 has a seventh resistor connected to its VDIO pin, and the seventh resistor is connected to the drain of the MOSFET Q2.
[0012] The beneficial effects of this utility model are as follows: By connecting a first resistor in series between the WiFi chip U7 and the main chip U1, impedance matching is achieved, signal integrity is optimized, and basic current limiting protection is provided. This achieves impedance matching of the transmission line, reduces reflection, overshoot and electromagnetic interference in high-speed signal transmission, improves high-frequency signal integrity, and at the same time helps to limit abnormal current to protect the interface circuit and avoid signal quality deterioration. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of the overall structure of the RFID device according to an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of the device body according to an embodiment of the present utility model; Figure 3 This is the overall circuit diagram of an embodiment of the present utility model; Figure 4 This is a circuit diagram of the power-on wake-up circuit according to an embodiment of this utility model; Figure 5This is a circuit diagram of the radio frequency signal receiving circuit according to an embodiment of this utility model; Figure 6 This is a circuit diagram of the power control circuit of an embodiment of this utility model; Figure 7 This is a circuit diagram of the main chip U1 in an embodiment of this utility model.
[0014] Reference numerals: 1. Device body, 2. Extension rod, 3. Reading antenna, 4. Circuit board. Detailed Implementation
[0015] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model. In addition, the directional terms mentioned in this utility model, such as "up," "down," "front," "back," "left," "right," "inner," and "outer," are only for reference to the directions in the accompanying drawings. The directional terms are used to better and more clearly explain and understand this utility model, and are not intended to indicate or imply the necessary orientation of this utility model. Therefore, they should not be construed as limitations on this utility model.
[0016] Examples of embodiments of this utility model Figures 1 to 7 As shown, an RFID data acquisition device integrating WiFi 5G includes a device body 1, an extension rod 2 on the device body 1, a reading antenna 3 on the extension rod 2, a circuit board 4 inside the device body 1, and a WiFi 5G circuit located on the circuit board 4. The WiFi 5G circuit includes a main chip U1 connected to an RFID circuit, which is a common existing circuit. The main chip U1 is connected to a power control circuit, which is connected to a WiFi chip U7. The WiFi chip U7 is grounded and grounded to a radio frequency signal receiving circuit and a power wake-up circuit. Pins SDIO_DATA_2, SDIO_DATA_3, SDIO_DATA_CMD, SDIO_DATA_CLK, SDIO_DATA_D0, and SDIO_DATA_D1 of the WiFi chip U7 are all connected to a first resistor for impedance matching and signal current limiting. The first resistor has a specification of 22Ω, and multiple first resistors are connected to the main chip U1.
[0017] A first resistor is connected in series between the WiFi chip U7 and the main chip U1. The first resistor achieves impedance matching, optimizes signal integrity, and provides basic current limiting protection. It realizes transmission line impedance matching, reduces reflection, overshoot and electromagnetic interference in high-speed signal transmission, improves high-frequency signal integrity, and at the same time helps limit abnormal current to protect the interface circuit and avoid signal quality deterioration.
[0018] Further improvements, such as Figure 3 As shown, the first resistor connected to the SDIO_DATA_CLK pin of the WiFi chip U7 is also connected in parallel with a capacitor C39. The capacitor C39 is grounded and has a specification of 10pF. The capacitor C39 further filters out high-frequency noise.
[0019] Further improvements, such as Figure 4 As shown, the power wake-up circuit includes two OR second resistors, meaning the second resistors are of OR specification. The WL_REG_ON and WL_HOST_WAKE pins of the WiFi chip U7 are respectively connected to the two second resistors. The two second resistors are connected to the main chip U1. The OR second resistors ensure low-power control and communication triggering of the module. In SMT production, the packaging of the second resistors is the same as that of ordinary resistors, and they can be automatically soldered by a pick-and-place machine. This is more standardized than directly using flying wires or shorting pads, reducing production errors and short-circuit risks. When the WiFi module needs to communicate, a low level is input through the WL_REG_ON pin, and the WiFi module enters a sleep state to reduce power consumption. The WL_HOST_WAKE pin outputs a wake-up signal to wake up the WiFi module.
[0020] Further improvements, such as Figure 5 As shown, the WiFi chip U7's pins WL_REG_ON and WL_HOST_WAKE are also connected to two third resistors, each with a specification of 10K. The two third resistors are connected to the power supply VCC_3.3V. Current limiting through the third resistors can prevent signal overshoot or interference.
[0021] Further improvements, such as Figure 5As shown, the RF signal receiving circuit includes a fourth resistor connected to the RF pin of the WiFi chip U7. The fourth resistor has an OR rating. The fourth resistor is connected to capacitors C20 and C10. Capacitor C20 is grounded. Capacitor C10 is connected to capacitor C23, diode D5, and antenna interface ANT1. Capacitor C23 and diode D5 are both grounded. Diode D5 is connected in parallel between the signal path and ground to suppress electrostatic discharge or transient overvoltage and protect the subsequent circuit from damage. The antenna interface ANT1 is connected to a fifth resistor, which is grounded. The positions of the fifth resistor, capacitor C23, and capacitor C20 are reserved positions where no components are installed. The circuit is adjusted by soldering the fifth resistor, capacitor C23, and capacitor C20 according to the actual situation. Preferably, capacitors C23, C10, and C20 are all high-frequency ceramic capacitors with a capacitance of 10pF, forming a low-pass filter network. Capacitors C23 and C10 are connected in series in the signal path, and capacitor C20 is grounded to filter out high-frequency noise and spurious signals in the signal and retain the target frequency band signal.
[0022] Further improvements, such as Figure 6 As shown, the power control circuit includes a MOSFET Q2, the drain of which is connected to the WiFi chip U7, and the gate of which is connected to a sixth resistor and a power supply VCC_3.3V. The sixth resistor has a specification of 10K. Both the sixth resistor and the source of the MOSFET Q2 are connected to the main chip U1. This power control circuit realizes the switching control of power supply to the WiFi module.
[0023] Further improvements, such as Figure 3 and Figure 6 As shown, the WiFi chip U7 has a seventh resistor connected to its VDIO pin. The seventh resistor is rated 0R and is connected to the drain of the MOSFET Q2. During the research and development phase, if it is necessary to isolate the path, divide the voltage, or add filtering components, this can be achieved by replacing the 0R seventh resistor with other components without redesigning the circuit board layout.
[0024] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. An RFID data collection device integrating WiFi 5G, comprising a device body, characterized in that, The device body is provided with an extension rod; the extension rod is provided with a reading antenna; the device body is provided with a circuit board; the acquisition device also includes a WiFi 5G circuit; the WiFi 5G circuit is located on the circuit board; the WiFi 5G circuit includes a main chip U1, the main chip U1 is connected to a power control circuit; the power control circuit is connected to a WiFi chip U7; the WiFi chip U7 is grounded; the WiFi chip U7 is grounded and connected to an RF signal receiving circuit and a power wake-up circuit; pins SDIO_DATA_2, SDIO_DATA_3, SDIO_DATA_CMD, SDIO_DATA_CLK, SDIO_DATA_D0, and SDIO_DATA_D1 of the WiFi chip U7 are all connected to first resistors for impedance matching and signal current limiting; multiple first resistors are all connected to the main chip U1.
2. The RFID data collection device integrating WiFi 5G according to claim 1, characterized in that, The first resistor connected to the SDIO_DATA_CLK pin of the WiFi chip U7 is also connected in parallel with a capacitor C39; the capacitor C39 is grounded.
3. The RFID data collection device integrating WiFi 5G according to claim 1, characterized in that, The power wake-up circuit includes two OR second resistors; the WL_REG_ON and WL_HOST_WAKE pins of the WiFi chip U7 are respectively connected to the two second resistors; the two second resistors are connected to the main chip U1.
4. The RFID data collection device integrating WiFi 5G according to claim 3, characterized in that, The WiFi chip U7 has two third resistors connected to its pins WL_REG_ON and WL_HOST_WAKE respectively; the two third resistors are connected to the power supply VCC_3.3V.
5. The RFID data collection device integrating WiFi 5G according to claim 1, characterized in that, The radio frequency signal receiving circuit includes a fourth resistor connected to the RF pin of the WiFi chip U7; the fourth resistor is connected to capacitors C20 and C10; capacitor C20 is grounded; capacitor C10 is connected to capacitor C23, diode D5 and antenna interface ANT1; capacitor C23 and diode D5 are both grounded; the antenna interface ANT1 is connected to a fifth resistor; the fifth resistor is grounded.
6. The RFID data collection device integrating WiFi 5G according to claim 1, characterized in that, The power control circuit includes a MOSFET Q2; the drain of the MOSFET Q2 is connected to the WiFi chip U7; the gate of the MOSFET Q2 is connected to a sixth resistor and is connected to the power supply VCC_3.3V; the sixth resistor and the source of the MOSFET Q2 are both connected to the main chip U1.
7. The RFID data collection device integrating WiFi 5G according to claim 6, characterized in that, The WiFi chip U7 has a seventh resistor connected to its VDIO pin; the seventh resistor is connected to the drain of the MOS transistor Q2.